1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import chipsalliance.rocketchip.config._ 20import chisel3._ 21import chisel3.util._ 22import device.{EnableJtag, XSDebugModuleParams} 23import freechips.rocketchip.devices.debug._ 24import freechips.rocketchip.tile.{MaxHartIdBits, XLen} 25import system._ 26import utility._ 27import utils._ 28import huancun._ 29import xiangshan._ 30import xiangshan.backend.dispatch.DispatchParameters 31import xiangshan.backend.regfile.{IntPregParams, VfPregParams} 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 34import xiangshan.frontend.icache.ICacheParameters 35 36class BaseConfig(n: Int) extends Config((site, here, up) => { 37 case XLen => 64 38 case DebugOptionsKey => DebugOptions() 39 case SoCParamsKey => SoCParameters() 40 case PMParameKey => PMParameters() 41 case XSTileKey => Seq.tabulate(n){ i => XSCoreParameters(HartId = i) } 42 case ExportDebug => DebugAttachParams(protocols = Set(JTAG)) 43 case DebugModuleKey => Some(XSDebugModuleParams(site(XLen))) 44 case JtagDTMKey => JtagDTMKey 45 case MaxHartIdBits => 2 46 case EnableJtag => true.B 47}) 48 49// Synthesizable minimal XiangShan 50// * It is still an out-of-order, super-scalaer arch 51// * L1 cache included 52// * L2 cache NOT included 53// * L3 cache included 54class MinimalConfig(n: Int = 1) extends Config( 55 new BaseConfig(n).alter((site, here, up) => { 56 case XSTileKey => up(XSTileKey).map( 57 _.copy( 58 DecodeWidth = 2, 59 RenameWidth = 2, 60 CommitWidth = 2, 61 FetchWidth = 4, 62 NRPhyRegs = 96, 63 IntPhyRegs = 96, 64 VfPhyRegs = 96, 65 LoadQueueSize = 16, 66 LoadQueueNWriteBanks = 4, 67 StoreQueueSize = 12, 68 StoreQueueNWriteBanks = 4, 69 RobSize = 32, 70 FtqSize = 8, 71 IBufSize = 16, 72 StoreBufferSize = 4, 73 StoreBufferThreshold = 3, 74 dpParams = DispatchParameters( 75 IntDqSize = 12, 76 FpDqSize = 12, 77 LsDqSize = 12, 78 IntDqDeqWidth = 4, 79 FpDqDeqWidth = 4, 80 LsDqDeqWidth = 4 81 ), 82 intPreg = IntPregParams( 83 numEntries = 128, 84 numRead = 14, 85 numWrite = 8, 86 ), 87 vfPreg = VfPregParams( 88 numEntries = 128, 89 numRead = 14, 90 numWrite = 8, 91 ), 92 icacheParameters = ICacheParameters( 93 nSets = 64, // 16KB ICache 94 tagECC = Some("parity"), 95 dataECC = Some("parity"), 96 replacer = Some("setplru"), 97 nMissEntries = 2, 98 nReleaseEntries = 1, 99 nProbeEntries = 2, 100 nPrefetchEntries = 2, 101 hasPrefetch = false 102 ), 103 dcacheParametersOpt = Some(DCacheParameters( 104 nSets = 64, // 32KB DCache 105 nWays = 8, 106 tagECC = Some("secded"), 107 dataECC = Some("secded"), 108 replacer = Some("setplru"), 109 nMissEntries = 4, 110 nProbeEntries = 4, 111 nReleaseEntries = 8, 112 )), 113 EnableBPD = false, // disable TAGE 114 EnableLoop = false, 115 itlbParameters = TLBParameters( 116 name = "itlb", 117 fetchi = true, 118 useDmode = false, 119 normalReplacer = Some("plru"), 120 superReplacer = Some("plru"), 121 normalNWays = 4, 122 normalNSets = 1, 123 superNWays = 2 124 ), 125 ldtlbParameters = TLBParameters( 126 name = "ldtlb", 127 normalNSets = 16, // when da or sa 128 normalNWays = 1, // when fa or sa 129 normalAssociative = "sa", 130 normalReplacer = Some("setplru"), 131 superNWays = 4, 132 normalAsVictim = true, 133 partialStaticPMP = true, 134 outsideRecvFlush = true, 135 outReplace = false 136 ), 137 sttlbParameters = TLBParameters( 138 name = "sttlb", 139 normalNSets = 16, // when da or sa 140 normalNWays = 1, // when fa or sa 141 normalAssociative = "sa", 142 normalReplacer = Some("setplru"), 143 normalAsVictim = true, 144 superNWays = 4, 145 partialStaticPMP = true, 146 outsideRecvFlush = true, 147 outReplace = false 148 ), 149 pftlbParameters = TLBParameters( 150 name = "pftlb", 151 normalNSets = 16, // when da or sa 152 normalNWays = 1, // when fa or sa 153 normalAssociative = "sa", 154 normalReplacer = Some("setplru"), 155 normalAsVictim = true, 156 superNWays = 4, 157 partialStaticPMP = true, 158 outsideRecvFlush = true, 159 outReplace = false 160 ), 161 btlbParameters = TLBParameters( 162 name = "btlb", 163 normalNSets = 1, 164 normalNWays = 8, 165 superNWays = 2 166 ), 167 l2tlbParameters = L2TLBParameters( 168 l1Size = 4, 169 l2nSets = 4, 170 l2nWays = 4, 171 l3nSets = 4, 172 l3nWays = 8, 173 spSize = 2, 174 ), 175 L2CacheParamsOpt = None, // remove L2 Cache 176 prefetcher = None // if L2 pf_recv_node does not exist, disable SMS prefetcher 177 ) 178 ) 179 case SoCParamsKey => 180 val tiles = site(XSTileKey) 181 up(SoCParamsKey).copy( 182 L3CacheParamsOpt = Some(up(SoCParamsKey).L3CacheParamsOpt.get.copy( 183 sets = 1024, 184 inclusive = false, 185 clientCaches = tiles.map{ p => 186 CacheParameters( 187 "dcache", 188 sets = 2 * p.dcacheParametersOpt.get.nSets, 189 ways = p.dcacheParametersOpt.get.nWays + 2, 190 blockGranularity = log2Ceil(2 * p.dcacheParametersOpt.get.nSets), 191 aliasBitsOpt = None 192 ) 193 }, 194 simulation = !site(DebugOptionsKey).FPGAPlatform 195 )), 196 L3NBanks = 1 197 ) 198 }) 199) 200 201// Non-synthesizable MinimalConfig, for fast simulation only 202class MinimalSimConfig(n: Int = 1) extends Config( 203 new MinimalConfig(n).alter((site, here, up) => { 204 case XSTileKey => up(XSTileKey).map(_.copy( 205 dcacheParametersOpt = None, 206 softPTW = true 207 )) 208 case SoCParamsKey => up(SoCParamsKey).copy( 209 L3CacheParamsOpt = None 210 ) 211 }) 212) 213 214class WithNKBL1D(n: Int, ways: Int = 8) extends Config((site, here, up) => { 215 case XSTileKey => 216 val sets = n * 1024 / ways / 64 217 up(XSTileKey).map(_.copy( 218 dcacheParametersOpt = Some(DCacheParameters( 219 nSets = sets, 220 nWays = ways, 221 tagECC = Some("secded"), 222 dataECC = Some("secded"), 223 replacer = Some("setplru"), 224 nMissEntries = 16, 225 nProbeEntries = 8, 226 nReleaseEntries = 18 227 )) 228 )) 229}) 230 231class WithNKBL2 232( 233 n: Int, 234 ways: Int = 8, 235 inclusive: Boolean = true, 236 banks: Int = 1, 237 alwaysReleaseData: Boolean = false 238) extends Config((site, here, up) => { 239 case XSTileKey => 240 val upParams = up(XSTileKey) 241 val l2sets = n * 1024 / banks / ways / 64 242 upParams.map(p => p.copy( 243 L2CacheParamsOpt = Some(HCCacheParameters( 244 name = "L2", 245 level = 2, 246 ways = ways, 247 sets = l2sets, 248 inclusive = inclusive, 249 alwaysReleaseData = alwaysReleaseData, 250 clientCaches = Seq(CacheParameters( 251 "dcache", 252 sets = 2 * p.dcacheParametersOpt.get.nSets / banks, 253 ways = p.dcacheParametersOpt.get.nWays + 2, 254 blockGranularity = log2Ceil(2 * p.dcacheParametersOpt.get.nSets / banks), 255 aliasBitsOpt = p.dcacheParametersOpt.get.aliasBitsOpt 256 )), 257 reqField = Seq(PreferCacheField()), 258 echoField = Seq(DirtyField()), 259 prefetch = Some(huancun.prefetch.PrefetchReceiverParams()), 260 enablePerf = true, 261 sramDepthDiv = 2, 262 tagECC = Some("secded"), 263 dataECC = Some("secded"), 264 simulation = !site(DebugOptionsKey).FPGAPlatform 265 )), 266 L2NBanks = banks 267 )) 268}) 269 270class WithNKBL3(n: Int, ways: Int = 8, inclusive: Boolean = true, banks: Int = 1) extends Config((site, here, up) => { 271 case SoCParamsKey => 272 val sets = n * 1024 / banks / ways / 64 273 val tiles = site(XSTileKey) 274 val clientDirBytes = tiles.map{ t => 275 t.L2NBanks * t.L2CacheParamsOpt.map(_.toCacheParams.capacity).getOrElse(0) 276 }.sum 277 up(SoCParamsKey).copy( 278 L3NBanks = banks, 279 L3CacheParamsOpt = Some(HCCacheParameters( 280 name = "L3", 281 level = 3, 282 ways = ways, 283 sets = sets, 284 inclusive = inclusive, 285 clientCaches = tiles.map{ core => 286 val l2params = core.L2CacheParamsOpt.get.toCacheParams 287 l2params.copy(sets = 2 * clientDirBytes / core.L2NBanks / l2params.ways / 64) 288 }, 289 enablePerf = true, 290 ctrl = Some(CacheCtrl( 291 address = 0x39000000, 292 numCores = tiles.size 293 )), 294 sramClkDivBy2 = true, 295 sramDepthDiv = 4, 296 tagECC = Some("secded"), 297 dataECC = Some("secded"), 298 simulation = !site(DebugOptionsKey).FPGAPlatform 299 )) 300 ) 301}) 302 303class WithL3DebugConfig extends Config( 304 new WithNKBL3(256, inclusive = false) ++ new WithNKBL2(64) 305) 306 307class MinimalL3DebugConfig(n: Int = 1) extends Config( 308 new WithL3DebugConfig ++ new MinimalConfig(n) 309) 310 311class DefaultL3DebugConfig(n: Int = 1) extends Config( 312 new WithL3DebugConfig ++ new BaseConfig(n) 313) 314 315class MinimalAliasDebugConfig(n: Int = 1) extends Config( 316 new WithNKBL3(512, inclusive = false) ++ 317 new WithNKBL2(256, inclusive = false, alwaysReleaseData = true) ++ 318 new WithNKBL1D(128) ++ 319 new MinimalConfig(n) 320) 321 322class MediumConfig(n: Int = 1) extends Config( 323 new WithNKBL3(4096, inclusive = false, banks = 4) 324 ++ new WithNKBL2(512, inclusive = false, alwaysReleaseData = true) 325 ++ new WithNKBL1D(128) 326 ++ new BaseConfig(n) 327) 328 329class DefaultConfig(n: Int = 1) extends Config( 330 new WithNKBL3(6 * 1024, inclusive = false, banks = 4, ways = 6) 331 ++ new WithNKBL2(2 * 512, inclusive = false, banks = 4, alwaysReleaseData = true) 332 ++ new WithNKBL1D(128) 333 ++ new BaseConfig(n) 334) 335