1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import xiangshan.ExceptionNO._ 24import xiangshan._ 25import xiangshan.backend.fu.PMPRespBundle 26import xiangshan.cache.mmu.{TlbCmd, TlbReq, TlbRequestIO, TlbResp} 27 28// Store Pipeline Stage 0 29// Generate addr, use addr to query DCache and DTLB 30class StoreUnit_S0(implicit p: Parameters) extends XSModule { 31 val io = IO(new Bundle() { 32 val in = Flipped(Decoupled(new ExuInput)) 33 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 34 val isFirstIssue = Input(Bool()) 35 val out = Decoupled(new LsPipelineBundle) 36 val dtlbReq = DecoupledIO(new TlbReq) 37 }) 38 39 // send req to dtlb 40 // val saddr = io.in.bits.src(0) + SignExt(io.in.bits.uop.ctrl.imm(11,0), VAddrBits) 41 val imm12 = WireInit(io.in.bits.uop.ctrl.imm(11,0)) 42 val saddr_lo = io.in.bits.src(0)(11,0) + Cat(0.U(1.W), imm12) 43 val saddr_hi = Mux(saddr_lo(12), 44 Mux(imm12(11), io.in.bits.src(0)(VAddrBits-1, 12), io.in.bits.src(0)(VAddrBits-1, 12)+1.U), 45 Mux(imm12(11), io.in.bits.src(0)(VAddrBits-1, 12)+SignExt(1.U, VAddrBits-12), io.in.bits.src(0)(VAddrBits-1, 12)), 46 ) 47 val saddr = Cat(saddr_hi, saddr_lo(11,0)) 48 49 io.dtlbReq.bits.vaddr := saddr 50 io.dtlbReq.valid := io.in.valid 51 io.dtlbReq.bits.cmd := TlbCmd.write 52 io.dtlbReq.bits.size := LSUOpType.size(io.in.bits.uop.ctrl.fuOpType) 53 io.dtlbReq.bits.kill := DontCare 54 io.dtlbReq.bits.debug.robIdx := io.in.bits.uop.robIdx 55 io.dtlbReq.bits.debug.pc := io.in.bits.uop.cf.pc 56 io.dtlbReq.bits.debug.isFirstIssue := io.isFirstIssue 57 58 io.out.bits := DontCare 59 io.out.bits.vaddr := saddr 60 61 // Now data use its own io 62 // io.out.bits.data := genWdata(io.in.bits.src(1), io.in.bits.uop.ctrl.fuOpType(1,0)) 63 io.out.bits.data := io.in.bits.src(1) // FIXME: remove data from pipeline 64 io.out.bits.uop := io.in.bits.uop 65 io.out.bits.miss := DontCare 66 io.out.bits.rsIdx := io.rsIdx 67 io.out.bits.mask := genWmask(io.out.bits.vaddr, io.in.bits.uop.ctrl.fuOpType(1,0)) 68 io.out.bits.isFirstIssue := io.isFirstIssue 69 io.out.bits.wlineflag := io.in.bits.uop.ctrl.fuOpType === LSUOpType.cbo_zero 70 io.out.valid := io.in.valid 71 io.in.ready := io.out.ready 72 73 // exception check 74 val addrAligned = LookupTree(io.in.bits.uop.ctrl.fuOpType(1,0), List( 75 "b00".U -> true.B, //b 76 "b01".U -> (io.out.bits.vaddr(0) === 0.U), //h 77 "b10".U -> (io.out.bits.vaddr(1,0) === 0.U), //w 78 "b11".U -> (io.out.bits.vaddr(2,0) === 0.U) //d 79 )) 80 81 io.out.bits.uop.cf.exceptionVec(storeAddrMisaligned) := !addrAligned 82 83 XSPerfAccumulate("in_valid", io.in.valid) 84 XSPerfAccumulate("in_fire", io.in.fire) 85 XSPerfAccumulate("in_fire_first_issue", io.in.fire && io.isFirstIssue) 86 XSPerfAccumulate("addr_spec_success", io.out.fire() && saddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12)) 87 XSPerfAccumulate("addr_spec_failed", io.out.fire() && saddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12)) 88 XSPerfAccumulate("addr_spec_success_once", io.out.fire() && saddr(VAddrBits-1, 12) === io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue) 89 XSPerfAccumulate("addr_spec_failed_once", io.out.fire() && saddr(VAddrBits-1, 12) =/= io.in.bits.src(0)(VAddrBits-1, 12) && io.isFirstIssue) 90} 91 92// Store Pipeline Stage 1 93// TLB resp (send paddr to dcache) 94class StoreUnit_S1(implicit p: Parameters) extends XSModule { 95 val io = IO(new Bundle() { 96 val in = Flipped(Decoupled(new LsPipelineBundle)) 97 val out = Decoupled(new LsPipelineBundle) 98 val lsq = ValidIO(new LsPipelineBundle()) 99 val dtlbResp = Flipped(DecoupledIO(new TlbResp())) 100 val rsFeedback = ValidIO(new RSFeedback) 101 }) 102 103 // mmio cbo decoder 104 val is_mmio_cbo = io.in.bits.uop.ctrl.fuOpType === LSUOpType.cbo_clean || 105 io.in.bits.uop.ctrl.fuOpType === LSUOpType.cbo_flush || 106 io.in.bits.uop.ctrl.fuOpType === LSUOpType.cbo_inval 107 108 val s1_paddr = io.dtlbResp.bits.paddr(0) 109 val s1_tlb_miss = io.dtlbResp.bits.miss 110 val s1_mmio = is_mmio_cbo 111 val s1_exception = ExceptionNO.selectByFu(io.out.bits.uop.cf.exceptionVec, staCfg).asUInt.orR 112 113 io.in.ready := true.B 114 115 io.dtlbResp.ready := true.B // TODO: why dtlbResp needs a ready? 116 117 // Send TLB feedback to store issue queue 118 // Store feedback is generated in store_s1, sent to RS in store_s2 119 io.rsFeedback.valid := io.in.valid 120 io.rsFeedback.bits.hit := !s1_tlb_miss 121 io.rsFeedback.bits.flushState := io.dtlbResp.bits.ptwBack 122 io.rsFeedback.bits.rsIdx := io.in.bits.rsIdx 123 io.rsFeedback.bits.sourceType := RSFeedbackType.tlbMiss 124 XSDebug(io.rsFeedback.valid, 125 "S1 Store: tlbHit: %d robIdx: %d\n", 126 io.rsFeedback.bits.hit, 127 io.rsFeedback.bits.rsIdx 128 ) 129 io.rsFeedback.bits.dataInvalidSqIdx := DontCare 130 131 // get paddr from dtlb, check if rollback is needed 132 // writeback store inst to lsq 133 io.out.valid := io.in.valid && !s1_tlb_miss 134 io.out.bits := io.in.bits 135 io.out.bits.paddr := s1_paddr 136 io.out.bits.miss := false.B 137 io.out.bits.mmio := s1_mmio 138 io.out.bits.uop.cf.exceptionVec(storePageFault) := io.dtlbResp.bits.excp(0).pf.st 139 io.out.bits.uop.cf.exceptionVec(storeAccessFault) := io.dtlbResp.bits.excp(0).af.st 140 141 io.lsq.valid := io.in.valid 142 io.lsq.bits := io.out.bits 143 io.lsq.bits.miss := s1_tlb_miss 144 145 // mmio inst with exception will be writebacked immediately 146 // io.out.valid := io.in.valid && (!io.out.bits.mmio || s1_exception) && !s1_tlb_miss 147 148 XSPerfAccumulate("in_valid", io.in.valid) 149 XSPerfAccumulate("in_fire", io.in.fire) 150 XSPerfAccumulate("in_fire_first_issue", io.in.fire && io.in.bits.isFirstIssue) 151 XSPerfAccumulate("tlb_miss", io.in.fire && s1_tlb_miss) 152 XSPerfAccumulate("tlb_miss_first_issue", io.in.fire && s1_tlb_miss && io.in.bits.isFirstIssue) 153} 154 155class StoreUnit_S2(implicit p: Parameters) extends XSModule { 156 val io = IO(new Bundle() { 157 val in = Flipped(Decoupled(new LsPipelineBundle)) 158 val pmpResp = Flipped(new PMPRespBundle) 159 val static_pm = Input(Valid(Bool())) 160 val out = Decoupled(new LsPipelineBundle) 161 }) 162 val pmp = WireInit(io.pmpResp) 163 when (io.static_pm.valid) { 164 pmp.ld := false.B 165 pmp.st := false.B 166 pmp.instr := false.B 167 pmp.mmio := io.static_pm.bits 168 } 169 170 val s2_exception = ExceptionNO.selectByFu(io.out.bits.uop.cf.exceptionVec, staCfg).asUInt.orR 171 val is_mmio = io.in.bits.mmio || pmp.mmio 172 173 io.in.ready := true.B 174 io.out.bits := io.in.bits 175 io.out.bits.mmio := is_mmio && !s2_exception 176 io.out.bits.uop.cf.exceptionVec(storeAccessFault) := io.in.bits.uop.cf.exceptionVec(storeAccessFault) || pmp.st 177 io.out.valid := io.in.valid && (!is_mmio || s2_exception) 178} 179 180class StoreUnit_S3(implicit p: Parameters) extends XSModule { 181 val io = IO(new Bundle() { 182 val in = Flipped(Decoupled(new LsPipelineBundle)) 183 val stout = DecoupledIO(new ExuOutput) // writeback store 184 }) 185 186 io.in.ready := true.B 187 188 io.stout.valid := io.in.valid 189 io.stout.bits.uop := io.in.bits.uop 190 io.stout.bits.data := DontCare 191 io.stout.bits.redirectValid := false.B 192 io.stout.bits.redirect := DontCare 193 io.stout.bits.debug.isMMIO := io.in.bits.mmio 194 io.stout.bits.debug.paddr := io.in.bits.paddr 195 io.stout.bits.debug.vaddr := io.in.bits.vaddr 196 io.stout.bits.debug.isPerfCnt := false.B 197 io.stout.bits.fflags := DontCare 198 199} 200 201class StoreUnit(implicit p: Parameters) extends XSModule { 202 val io = IO(new Bundle() { 203 val stin = Flipped(Decoupled(new ExuInput)) 204 val redirect = Flipped(ValidIO(new Redirect)) 205 val feedbackSlow = ValidIO(new RSFeedback) 206 val tlb = new TlbRequestIO() 207 val pmp = Flipped(new PMPRespBundle()) 208 val rsIdx = Input(UInt(log2Up(IssQueSize).W)) 209 val isFirstIssue = Input(Bool()) 210 val lsq = ValidIO(new LsPipelineBundle) 211 val lsq_replenish = Output(new LsPipelineBundle()) 212 val stout = DecoupledIO(new ExuOutput) // writeback store 213 // store mask, send to sq in store_s0 214 val storeMaskOut = Valid(new StoreMaskBundle) 215 }) 216 217 val store_s0 = Module(new StoreUnit_S0) 218 val store_s1 = Module(new StoreUnit_S1) 219 val store_s2 = Module(new StoreUnit_S2) 220 val store_s3 = Module(new StoreUnit_S3) 221 222 store_s0.io.in <> io.stin 223 store_s0.io.dtlbReq <> io.tlb.req 224 io.tlb.req_kill := false.B 225 store_s0.io.rsIdx := io.rsIdx 226 store_s0.io.isFirstIssue := io.isFirstIssue 227 228 io.storeMaskOut.valid := store_s0.io.in.valid 229 io.storeMaskOut.bits.mask := store_s0.io.out.bits.mask 230 io.storeMaskOut.bits.sqIdx := store_s0.io.out.bits.uop.sqIdx 231 232 PipelineConnect(store_s0.io.out, store_s1.io.in, true.B, store_s0.io.out.bits.uop.robIdx.needFlush(io.redirect)) 233 234 235 store_s1.io.dtlbResp <> io.tlb.resp 236 io.lsq <> store_s1.io.lsq 237 238 PipelineConnect(store_s1.io.out, store_s2.io.in, true.B, store_s1.io.out.bits.uop.robIdx.needFlush(io.redirect)) 239 240 // feedback tlb miss to RS in store_s2 241 io.feedbackSlow.bits := RegNext(store_s1.io.rsFeedback.bits) 242 io.feedbackSlow.valid := RegNext(store_s1.io.rsFeedback.valid && !store_s1.io.out.bits.uop.robIdx.needFlush(io.redirect)) 243 244 store_s2.io.pmpResp <> io.pmp 245 store_s2.io.static_pm := RegNext(io.tlb.resp.bits.static_pm) 246 io.lsq_replenish := store_s2.io.out.bits // mmio and exception 247 PipelineConnect(store_s2.io.out, store_s3.io.in, true.B, store_s2.io.out.bits.uop.robIdx.needFlush(io.redirect)) 248 249 store_s3.io.stout <> io.stout 250 251 private def printPipeLine(pipeline: LsPipelineBundle, cond: Bool, name: String): Unit = { 252 XSDebug(cond, 253 p"$name" + p" pc ${Hexadecimal(pipeline.uop.cf.pc)} " + 254 p"addr ${Hexadecimal(pipeline.vaddr)} -> ${Hexadecimal(pipeline.paddr)} " + 255 p"op ${Binary(pipeline.uop.ctrl.fuOpType)} " + 256 p"data ${Hexadecimal(pipeline.data)} " + 257 p"mask ${Hexadecimal(pipeline.mask)}\n" 258 ) 259 } 260 261 printPipeLine(store_s0.io.out.bits, store_s0.io.out.valid, "S0") 262 printPipeLine(store_s1.io.out.bits, store_s1.io.out.valid, "S1") 263} 264