1package xiangshan.backend.issue 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3.util._ 5import xiangshan.backend.Bundles.{ExuInput, ExuOutput} 6import xiangshan.backend.datapath.WbConfig.WbConfig 7 8case class SchdBlockParams( 9 issueBlockParams: Seq[IssueBlockParams], 10 numPregs : Int, 11 numRfReadWrite : Option[(Int, Int)], 12 numDeqOutside : Int, 13 schdType : SchedulerType, 14 rfDataWidth : Int, 15 numUopIn : Int, 16) { 17 def isMemSchd: Boolean = schdType == MemScheduler() 18 19 def isIntSchd: Boolean = schdType == IntScheduler() 20 21 def isVfSchd: Boolean = schdType == VfScheduler() 22 23 def JmpCnt: Int = issueBlockParams.map(_.JmpCnt).sum 24 25 def BrhCnt: Int = issueBlockParams.map(_.BrhCnt).sum 26 27 def I2fCnt: Int = issueBlockParams.map(_.I2fCnt).sum 28 29 def CsrCnt: Int = issueBlockParams.map(_.CsrCnt).sum 30 31 def AluCnt: Int = issueBlockParams.map(_.AluCnt).sum 32 33 def MulCnt: Int = issueBlockParams.map(_.MulCnt).sum 34 35 def DivCnt: Int = issueBlockParams.map(_.DivCnt).sum 36 37 def FenceCnt: Int = issueBlockParams.map(_.FenceCnt).sum 38 39 def BkuCnt: Int = issueBlockParams.map(_.BkuCnt).sum 40 41 def VsetCnt: Int = issueBlockParams.map(_.VsetCnt).sum 42 43 def FmacCnt: Int = issueBlockParams.map(_.FmacCnt).sum 44 45 def FmiscCnt: Int = issueBlockParams.map(_.FmiscCnt).sum 46 47 def FDivSqrtCnt: Int = issueBlockParams.map(_.fDivSqrtCnt).sum 48 49 def LduCnt: Int = issueBlockParams.map(_.LduCnt).sum 50 51 def StaCnt: Int = issueBlockParams.map(_.StaCnt).sum 52 53 def StdCnt: Int = issueBlockParams.map(_.StdCnt).sum 54 55 def MouCnt: Int = issueBlockParams.map(_.MouCnt).sum 56 57 def VipuCnt: Int = issueBlockParams.map(_.VipuCnt).sum 58 59 def VfpuCnt: Int = issueBlockParams.map(_.VfpuCnt).sum 60 61 def VlduCnt: Int = issueBlockParams.map(_.VlduCnt).sum 62 63 def VstuCnt: Int = issueBlockParams.map(_.VstuCnt).sum 64 65 def numExu: Int = issueBlockParams.map(_.exuBlockParams.count(!_.hasStdFu)).sum 66 67 def hasCSR = CsrCnt > 0 68 69 def hasFence = FenceCnt > 0 70 71 def numWriteIntRf: Int = issueBlockParams.map(_.numWriteIntRf).sum 72 73 def numWriteFpRf: Int = issueBlockParams.map(_.numWriteFpRf).sum 74 75 def numWriteVecRf: Int = issueBlockParams.map(_.numWriteVecRf).sum 76 77 def numWriteVfRf: Int = issueBlockParams.map(_.numWriteVfRf).sum 78 79 def numNoDataWB: Int = issueBlockParams.map(_.numNoDataWB).sum 80 81 def numPcReadPort = { 82 val bjIssueQueues = issueBlockParams.filter(x => (x.JmpCnt + x.BrhCnt + x.FenceCnt) > 0) 83 if (bjIssueQueues.map(x => x.numEnq).sum > 0) numUopIn else 0 84 } 85 86 def needSrcFrm: Boolean = issueBlockParams.map(_.needSrcFrm).reduce(_ || _) 87 88 def numRedirect: Int = issueBlockParams.map(_.numRedirect).sum 89 90 def pregIdxWidth: Int = log2Up(numPregs) 91 92 def numWakeupFromWB: Int = schdType match { 93 case IntScheduler() | VfScheduler() => 8 94 case MemScheduler() => 16 // Todo 95 case _ => 0 96 } 97 98 def numIntRfReadByExu: Int = issueBlockParams.map(_.exuBlockParams.map(_.numIntSrc).sum).sum 99 100 def numVfRfReadByExu: Int = issueBlockParams.map(_.exuBlockParams.map(x => x.numFpSrc + x.numVecSrc).sum).sum 101 102 // Todo: 14R8W 103 def numIntRfRead: Int = numIntRfReadByExu 104 105 def genExuInputBundle(implicit p: Parameters): MixedVec[MixedVec[DecoupledIO[ExuInput]]] = { 106 MixedVec(this.issueBlockParams.map(_.genExuInputDecoupledBundle)) 107 } 108 109 def genExuOutputDecoupledBundle(implicit p: Parameters): MixedVec[MixedVec[DecoupledIO[ExuOutput]]] = { 110 MixedVec(this.issueBlockParams.map(_.genExuOutputDecoupledBundle)) 111 } 112 113 def genExuOutputValidBundle(implicit p: Parameters): MixedVec[MixedVec[ValidIO[ExuOutput]]] = { 114 MixedVec(this.issueBlockParams.map(_.genExuOutputValidBundle)) 115 } 116 117 // cfgs(issueIdx)(exuIdx)(set of exu's wb) 118 def getWbCfgs: Seq[Seq[Set[WbConfig]]] = { 119 this.issueBlockParams.map(_.getWbCfgs) 120 } 121} 122