1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utility._ 23import utils._ 24import xiangshan._ 25import xiangshan.backend.rob.RobLsqIO 26import xiangshan.cache._ 27import xiangshan.mem._ 28import xiangshan.v2backend.Bundles.{DynInst, MemExuOutput} 29 30class ExceptionAddrIO(implicit p: Parameters) extends XSBundle { 31 val isStore = Input(Bool()) 32 val vaddr = Output(UInt(VAddrBits.W)) 33} 34 35class FwdEntry extends Bundle { 36 val validFast = Bool() // validFast is generated the same cycle with query 37 val valid = Bool() // valid is generated 1 cycle after query request 38 val data = UInt(8.W) // data is generated 1 cycle after query request 39} 40 41// inflight miss block reqs 42class InflightBlockInfo(implicit p: Parameters) extends XSBundle { 43 val block_addr = UInt(PAddrBits.W) 44 val valid = Bool() 45} 46 47class LsqEnqIO(implicit p: Parameters) extends XSBundle { 48 val canAccept = Output(Bool()) 49 val needAlloc = Vec(backendParams.LsExuCnt, Input(UInt(2.W))) 50 val req = Vec(backendParams.LsExuCnt, Flipped(ValidIO(new DynInst))) 51 val resp = Vec(backendParams.LsExuCnt, Output(new LSIdx)) 52} 53 54// Load / Store Queue Wrapper for XiangShan Out of Order LSU 55class LsqWrappper(implicit p: Parameters) extends XSModule with HasDCacheParameters with HasPerfEvents { 56 val io = IO(new Bundle() { 57 val hartId = Input(UInt(8.W)) 58 val enq = new LsqEnqIO 59 val brqRedirect = Flipped(ValidIO(new Redirect)) 60 val loadPaddrIn = Vec(LoadPipelineWidth, Flipped(Valid(new LqPaddrWriteBundle))) 61 val loadVaddrIn = Vec(LoadPipelineWidth, Flipped(Valid(new LqVaddrWriteBundle))) 62 val replayFast = Vec(LoadPipelineWidth, Flipped(new LoadToLsqFastIO)) 63 val replaySlow = Vec(LoadPipelineWidth, Flipped(new LoadToLsqSlowIO)) 64 val loadOut = Vec(LoadPipelineWidth, Decoupled(new LsPipelineBundle)) 65 val loadIn = Vec(LoadPipelineWidth, Flipped(Valid(new LqWriteBundle))) 66 val storeIn = Vec(StorePipelineWidth, Flipped(Valid(new LsPipelineBundle))) 67 val storeInRe = Vec(StorePipelineWidth, Input(new LsPipelineBundle())) 68 val storeDataIn = Vec(StorePipelineWidth, Flipped(Valid(new MemExuOutput))) // store data, send to sq from rs 69 val storeMaskIn = Vec(StorePipelineWidth, Flipped(Valid(new StoreMaskBundle))) // store mask, send to sq from rs 70 val s2_load_data_forwarded = Vec(LoadPipelineWidth, Input(Bool())) 71 val s3_delayed_load_error = Vec(LoadPipelineWidth, Input(Bool())) 72 val s2_dcache_require_replay = Vec(LoadPipelineWidth, Input(Bool())) 73 val s3_replay_from_fetch = Vec(LoadPipelineWidth, Input(Bool())) 74 val sbuffer = Vec(EnsbufferWidth, Decoupled(new DCacheWordReqWithVaddr)) 75 val ldout = Vec(LoadPipelineWidth, DecoupledIO(new MemExuOutput)) // writeback int load 76 val ldRawDataOut = Vec(LoadPipelineWidth, Output(new LoadDataFromLQBundle)) 77 val uncacheOutstanding = Input(Bool()) 78 val mmioStout = DecoupledIO(new MemExuOutput) // writeback uncached store 79 val forward = Vec(LoadPipelineWidth, Flipped(new PipeLoadForwardQueryIO)) 80 val loadViolationQuery = Vec(LoadPipelineWidth, Flipped(new LoadViolationQueryIO)) 81 val rob = Flipped(new RobLsqIO) 82 val rollback = Output(Valid(new Redirect)) 83 val refill = Flipped(ValidIO(new Refill)) 84 val release = Flipped(ValidIO(new Release)) 85 val uncache = new UncacheWordIO 86 val exceptionAddr = new ExceptionAddrIO 87 val sqempty = Output(Bool()) 88 val issuePtrExt = Output(new SqPtr) 89 val sqFull = Output(Bool()) 90 val lqFull = Output(Bool()) 91 val lqCancelCnt = Output(UInt(log2Up(LoadQueueSize + 1).W)) 92 val sqCancelCnt = Output(UInt(log2Up(StoreQueueSize + 1).W)) 93 val sqDeq = Output(UInt(log2Ceil(EnsbufferWidth + 1).W)) 94 val trigger = Vec(LoadPipelineWidth, new LqTriggerIO) 95 }) 96 97 val loadQueue = Module(new LoadQueue) 98 val storeQueue = Module(new StoreQueue) 99 100 storeQueue.io.hartId := io.hartId 101 storeQueue.io.uncacheOutstanding := io.uncacheOutstanding 102 103 loadQueue.io.storeDataValidVec := storeQueue.io.storeDataValidVec 104 105 dontTouch(loadQueue.io.tlbReplayDelayCycleCtrl) 106 val tlbReplayDelayCycleCtrl = WireInit(VecInit(Seq(11.U(ReSelectLen.W), 50.U(ReSelectLen.W), 30.U(ReSelectLen.W), 10.U(ReSelectLen.W)))) 107 loadQueue.io.tlbReplayDelayCycleCtrl := tlbReplayDelayCycleCtrl 108 109 // io.enq logic 110 // LSQ: send out canAccept when both load queue and store queue are ready 111 // Dispatch: send instructions to LSQ only when they are ready 112 io.enq.canAccept := loadQueue.io.enq.canAccept && storeQueue.io.enq.canAccept 113 loadQueue.io.enq.sqCanAccept := storeQueue.io.enq.canAccept 114 storeQueue.io.enq.lqCanAccept := loadQueue.io.enq.canAccept 115 for (i <- io.enq.req.indices) { 116 loadQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i)(0) 117 loadQueue.io.enq.req(i).valid := io.enq.needAlloc(i)(0) && io.enq.req(i).valid 118 loadQueue.io.enq.req(i).bits := io.enq.req(i).bits 119 loadQueue.io.enq.req(i).bits.sqIdx := storeQueue.io.enq.resp(i) 120 121 storeQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i)(1) 122 storeQueue.io.enq.req(i).valid := io.enq.needAlloc(i)(1) && io.enq.req(i).valid 123 storeQueue.io.enq.req(i).bits := io.enq.req(i).bits 124 storeQueue.io.enq.req(i).bits := io.enq.req(i).bits 125 storeQueue.io.enq.req(i).bits.lqIdx := loadQueue.io.enq.resp(i) 126 127 io.enq.resp(i).lqIdx := loadQueue.io.enq.resp(i) 128 io.enq.resp(i).sqIdx := storeQueue.io.enq.resp(i) 129 } 130 131 // load queue wiring 132 loadQueue.io.brqRedirect <> io.brqRedirect 133 loadQueue.io.loadPaddrIn <> io.loadPaddrIn 134 loadQueue.io.loadOut <> io.loadOut 135 loadQueue.io.loadVaddrIn <> io.loadVaddrIn 136 loadQueue.io.replayFast <> io.replayFast 137 loadQueue.io.replaySlow <> io.replaySlow 138 loadQueue.io.loadIn <> io.loadIn 139 loadQueue.io.storeIn <> io.storeIn 140 loadQueue.io.s2_load_data_forwarded <> io.s2_load_data_forwarded 141 loadQueue.io.s3_delayed_load_error <> io.s3_delayed_load_error 142 loadQueue.io.s2_dcache_require_replay <> io.s2_dcache_require_replay 143 loadQueue.io.s3_replay_from_fetch <> io.s3_replay_from_fetch 144 loadQueue.io.ldout <> io.ldout 145 loadQueue.io.ldRawDataOut <> io.ldRawDataOut 146 loadQueue.io.rob <> io.rob 147 loadQueue.io.rollback <> io.rollback 148 loadQueue.io.refill <> io.refill 149 loadQueue.io.release <> io.release 150 loadQueue.io.trigger <> io.trigger 151 loadQueue.io.exceptionAddr.isStore := DontCare 152 loadQueue.io.lqCancelCnt <> io.lqCancelCnt 153 154 // store queue wiring 155 // storeQueue.io <> DontCare 156 storeQueue.io.brqRedirect <> io.brqRedirect 157 storeQueue.io.storeIn <> io.storeIn 158 storeQueue.io.storeInRe <> io.storeInRe 159 storeQueue.io.storeDataIn <> io.storeDataIn 160 storeQueue.io.storeMaskIn <> io.storeMaskIn 161 storeQueue.io.sbuffer <> io.sbuffer 162 storeQueue.io.mmioStout <> io.mmioStout 163 storeQueue.io.rob <> io.rob 164 storeQueue.io.exceptionAddr.isStore := DontCare 165 storeQueue.io.issuePtrExt <> io.issuePtrExt 166 storeQueue.io.sqCancelCnt <> io.sqCancelCnt 167 storeQueue.io.sqDeq <> io.sqDeq 168 169 loadQueue.io.load_s1 <> io.forward 170 storeQueue.io.forward <> io.forward // overlap forwardMask & forwardData, DO NOT CHANGE SEQUENCE 171 172 loadQueue.io.loadViolationQuery <> io.loadViolationQuery 173 174 storeQueue.io.sqempty <> io.sqempty 175 176 // rob commits for lsq is delayed for two cycles, which causes the delayed update for deqPtr in lq/sq 177 // s0: commit 178 // s1: exception find 179 // s2: exception triggered 180 // s3: ptr updated & new address 181 // address will be used at the next cycle after exception is triggered 182 io.exceptionAddr.vaddr := Mux(RegNext(io.exceptionAddr.isStore), storeQueue.io.exceptionAddr.vaddr, loadQueue.io.exceptionAddr.vaddr) 183 184 // naive uncache arbiter 185 val s_idle :: s_load :: s_store :: Nil = Enum(3) 186 val pendingstate = RegInit(s_idle) 187 188 switch(pendingstate){ 189 is(s_idle){ 190 when(io.uncache.req.fire() && !io.uncacheOutstanding){ 191 pendingstate := Mux(loadQueue.io.uncache.req.valid, s_load, 192 Mux(io.uncacheOutstanding, s_idle, s_store)) 193 } 194 } 195 is(s_load){ 196 when(io.uncache.resp.fire()){ 197 pendingstate := s_idle 198 } 199 } 200 is(s_store){ 201 when(io.uncache.resp.fire()){ 202 pendingstate := s_idle 203 } 204 } 205 } 206 207 loadQueue.io.uncache := DontCare 208 storeQueue.io.uncache := DontCare 209 loadQueue.io.uncache.resp.valid := false.B 210 storeQueue.io.uncache.resp.valid := false.B 211 when(loadQueue.io.uncache.req.valid){ 212 io.uncache.req <> loadQueue.io.uncache.req 213 }.otherwise{ 214 io.uncache.req <> storeQueue.io.uncache.req 215 } 216 when (io.uncacheOutstanding) { 217 io.uncache.resp <> loadQueue.io.uncache.resp 218 } .otherwise { 219 when(pendingstate === s_load){ 220 io.uncache.resp <> loadQueue.io.uncache.resp 221 }.otherwise{ 222 io.uncache.resp <> storeQueue.io.uncache.resp 223 } 224 } 225 226 227 assert(!(loadQueue.io.uncache.req.valid && storeQueue.io.uncache.req.valid)) 228 assert(!(loadQueue.io.uncache.resp.valid && storeQueue.io.uncache.resp.valid)) 229 when (!io.uncacheOutstanding) { 230 assert(!((loadQueue.io.uncache.resp.valid || storeQueue.io.uncache.resp.valid) && pendingstate === s_idle)) 231 } 232 233 io.lqFull := loadQueue.io.lqFull 234 io.sqFull := storeQueue.io.sqFull 235 236 val perfEvents = Seq(loadQueue, storeQueue).flatMap(_.getPerfEvents) 237 generatePerfEvent() 238} 239 240class LsqEnqCtrl(implicit p: Parameters) extends XSModule { 241 val io = IO(new Bundle { 242 val redirect = Flipped(ValidIO(new Redirect)) 243 // to dispatch 244 val enq = new LsqEnqIO 245 // from rob 246 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 247 // from `memBlock.io.sqDeq` 248 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 249 // from/tp lsq 250 val lqCancelCnt = Input(UInt(log2Up(LoadQueueSize + 1).W)) 251 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 252 val enqLsq = Flipped(new LsqEnqIO) 253 }) 254 255 val lqPtr = RegInit(0.U.asTypeOf(new LqPtr)) 256 val sqPtr = RegInit(0.U.asTypeOf(new SqPtr)) 257 val lqCounter = RegInit(LoadQueueSize.U(log2Up(LoadQueueSize + 1).W)) 258 val sqCounter = RegInit(StoreQueueSize.U(log2Up(StoreQueueSize + 1).W)) 259 val canAccept = RegInit(false.B) 260 261 val loadEnqNumber = PopCount(io.enq.req.zip(io.enq.needAlloc).map(x => x._1.valid && x._2(0))) 262 val storeEnqNumber = PopCount(io.enq.req.zip(io.enq.needAlloc).map(x => x._1.valid && x._2(1))) 263 264 // How to update ptr and counter: 265 // (1) by default, updated according to enq/commit 266 // (2) when redirect and dispatch queue is empty, update according to lsq 267 val t1_redirect = RegNext(io.redirect.valid) 268 val t2_redirect = RegNext(t1_redirect) 269 val t2_update = t2_redirect && !VecInit(io.enq.needAlloc.map(_.orR)).asUInt.orR 270 val t3_update = RegNext(t2_update) 271 val t3_lqCancelCnt = RegNext(io.lqCancelCnt) 272 val t3_sqCancelCnt = RegNext(io.sqCancelCnt) 273 when (t3_update) { 274 lqPtr := lqPtr - t3_lqCancelCnt 275 lqCounter := lqCounter + io.lcommit + t3_lqCancelCnt 276 sqPtr := sqPtr - t3_sqCancelCnt 277 sqCounter := sqCounter + io.scommit + t3_sqCancelCnt 278 }.elsewhen (!io.redirect.valid && io.enq.canAccept) { 279 lqPtr := lqPtr + loadEnqNumber 280 lqCounter := lqCounter + io.lcommit - loadEnqNumber 281 sqPtr := sqPtr + storeEnqNumber 282 sqCounter := sqCounter + io.scommit - storeEnqNumber 283 }.otherwise { 284 lqCounter := lqCounter + io.lcommit 285 sqCounter := sqCounter + io.scommit 286 } 287 288 289 val maxAllocate = Seq(backendParams.LduCnt, backendParams.StaCnt).max 290 val ldCanAccept = lqCounter >= loadEnqNumber +& maxAllocate.U 291 val sqCanAccept = sqCounter >= storeEnqNumber +& maxAllocate.U 292 // It is possible that t3_update and enq are true at the same clock cycle. 293 // For example, if redirect.valid lasts more than one clock cycle, 294 // after the last redirect, new instructions may enter but previously redirect 295 // has not been resolved (updated according to the cancel count from LSQ). 296 // To solve the issue easily, we block enqueue when t3_update, which is RegNext(t2_update). 297 io.enq.canAccept := RegNext(ldCanAccept && sqCanAccept && !t2_update) 298 val lqOffset = Wire(Vec(io.enq.resp.length, UInt(log2Up(maxAllocate + 1).W))) 299 val sqOffset = Wire(Vec(io.enq.resp.length, UInt(log2Up(maxAllocate + 1).W))) 300 for ((resp, i) <- io.enq.resp.zipWithIndex) { 301 lqOffset(i) := PopCount(io.enq.needAlloc.take(i).map(a => a(0))) 302 resp.lqIdx := lqPtr + lqOffset(i) 303 sqOffset(i) := PopCount(io.enq.needAlloc.take(i).map(a => a(1))) 304 resp.sqIdx := sqPtr + sqOffset(i) 305 } 306 307 io.enqLsq.needAlloc := RegNext(io.enq.needAlloc) 308 io.enqLsq.req.zip(io.enq.req).zip(io.enq.resp).foreach{ case ((toLsq, enq), resp) => 309 val do_enq = enq.valid && !io.redirect.valid && io.enq.canAccept 310 toLsq.valid := RegNext(do_enq) 311 toLsq.bits := RegEnable(enq.bits, do_enq) 312 toLsq.bits.lqIdx := RegEnable(resp.lqIdx, do_enq) 313 toLsq.bits.sqIdx := RegEnable(resp.sqIdx, do_enq) 314 } 315 316} 317