xref: /XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala (revision 3b739f49c5a26805be859c7231717ecc38aade30) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.backend.fu
18
19import chipsalliance.rocketchip.config.Parameters
20import chisel3._
21import chisel3.util._
22import utility._
23import utils._
24import xiangshan.ExceptionNO.illegalInstr
25import xiangshan._
26import xiangshan.v2backend.FuConfig
27import xiangshan.v2backend.fu.FuncUnit
28
29class FenceToSbuffer extends Bundle {
30  val flushSb = Output(Bool())
31  val sbIsEmpty = Input(Bool())
32}
33
34class Fence(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) {
35
36  val sfence = io.fenceio.get.sfence
37  val fencei = io.fenceio.get.fencei
38  val toSbuffer = io.fenceio.get.sbuffer
39  val disableSfence = io.fenceio.get.disableSfence
40
41  val (valid, src1) = (
42    io.in.valid,
43    io.in.bits.src(0)
44  )
45
46  val s_idle :: s_wait :: s_tlb :: s_icache :: s_fence :: s_nofence :: Nil = Enum(6)
47
48  val state = RegInit(s_idle)
49  /* fsm
50   * s_idle    : init state, send sbflush
51   * s_wait  : send sbflush, wait for sbEmpty
52   * s_tlb   : flush tlb, just hold one cycle
53   * s_icache: flush icache, just hold one cycle
54   * s_fence : do nothing, for timing optimiaztion
55   * s_nofence: do nothing , for Svinval extension
56   */
57
58  val sbuffer = toSbuffer.flushSb
59  val sbEmpty = toSbuffer.sbIsEmpty
60  val uop = RegEnable(io.in.bits, io.in.fire)
61  val func = uop.fuOpType
62
63  // NOTE: icache & tlb & sbuffer must receive flush signal at any time
64  sbuffer      := state === s_wait && !(func === FenceOpType.sfence && disableSfence)
65  fencei       := state === s_icache
66  sfence.valid := state === s_tlb && !disableSfence
67  sfence.bits.rs1  := uop.imm(4, 0) === 0.U
68  sfence.bits.rs2  := uop.imm(9, 5) === 0.U
69  sfence.bits.flushPipe := uop.flushPipe.get
70//  XSError(sfence.valid && uop.lsrc(0) =/= uop.imm(4, 0), "lsrc0 is passed by imm\n")
71//  XSError(sfence.valid && uop.lsrc(1) =/= uop.imm(9, 5), "lsrc1 is passed by imm\n")
72  sfence.bits.addr := RegEnable(io.in.bits.src(0), io.in.fire())
73  sfence.bits.asid := RegEnable(io.in.bits.src(1), io.in.fire())
74
75  when (state === s_idle && io.in.valid) { state := s_wait }
76  when (state === s_wait && func === FenceOpType.fencei && sbEmpty) { state := s_icache }
77  when (state === s_wait && func === FenceOpType.sfence && (sbEmpty || disableSfence)) { state := s_tlb }
78  when (state === s_wait && func === FenceOpType.fence  && sbEmpty) { state := s_fence }
79  when (state === s_wait && func === FenceOpType.nofence  && sbEmpty) { state := s_nofence }
80  when (state =/= s_idle && state =/= s_wait) { state := s_idle }
81
82  io.in.ready := state === s_idle
83  io.out.valid := state =/= s_idle && state =/= s_wait
84  io.out.bits.data := 0.U
85  io.out.bits.robIdx := uop.robIdx
86  io.out.bits.pc.get := uop.pc.get
87  io.out.bits.pdest := uop.pdest
88  io.out.bits.flushPipe.get := uop.flushPipe.get
89  io.out.bits.exceptionVec.get := 0.U.asTypeOf(io.out.bits.exceptionVec.get)
90  io.out.bits.exceptionVec.get(illegalInstr) := func === FenceOpType.sfence && disableSfence
91
92  XSDebug(io.in.valid, p"In(${io.in.valid} ${io.in.ready}) state:${state} Inpc:0x${Hexadecimal(io.in.bits.pc.get)} InrobIdx:${io.in.bits.robIdx}\n")
93  XSDebug(state =/= s_idle, p"state:${state} sbuffer(flush:${sbuffer} empty:${sbEmpty}) fencei:${fencei} sfence:${sfence}\n")
94  XSDebug(io.out.valid, p" Out(${io.out.valid} ${io.out.ready}) state:${state} Outpc:0x${Hexadecimal(io.out.bits.pc.get)} OutrobIdx:${io.out.bits.robIdx}\n")
95
96  // assert(!(io.out.valid && io.out.bits.uop.ctrl.rfWen))
97  assert(!io.out.valid || io.out.ready, "when fence is out valid, out ready should always be true")
98}
99