1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend.icache 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.tilelink.ClientStates 23import xiangshan._ 24import xiangshan.cache.mmu._ 25import utils._ 26import utility._ 27import xiangshan.backend.fu.{PMPReqBundle, PMPRespBundle} 28import xiangshan.frontend.{FtqICacheInfo, FtqToICacheRequestBundle} 29 30class ICacheMainPipeReq(implicit p: Parameters) extends ICacheBundle 31{ 32 val vaddr = UInt(VAddrBits.W) 33 def vsetIdx = get_idx(vaddr) 34} 35 36class ICacheMainPipeResp(implicit p: Parameters) extends ICacheBundle 37{ 38 val vaddr = UInt(VAddrBits.W) 39 val registerData = UInt(blockBits.W) 40 val sramData = UInt(blockBits.W) 41 val select = Bool() 42 val paddr = UInt(PAddrBits.W) 43 val tlbExcp = new Bundle{ 44 val pageFault = Bool() 45 val accessFault = Bool() 46 val mmio = Bool() 47 } 48} 49 50class ICacheMainPipeBundle(implicit p: Parameters) extends ICacheBundle 51{ 52 val req = Flipped(Decoupled(new FtqToICacheRequestBundle)) 53 val resp = Vec(PortNumber, ValidIO(new ICacheMainPipeResp)) 54} 55 56class ICacheMetaReqBundle(implicit p: Parameters) extends ICacheBundle{ 57 val toIMeta = DecoupledIO(new ICacheReadBundle) 58 val fromIMeta = Input(new ICacheMetaRespBundle) 59} 60 61class ICacheDataReqBundle(implicit p: Parameters) extends ICacheBundle{ 62 val toIData = DecoupledIO(Vec(partWayNum, new ICacheReadBundle)) 63 val fromIData = Input(new ICacheDataRespBundle) 64} 65 66class ICacheMSHRBundle(implicit p: Parameters) extends ICacheBundle{ 67 val toMSHR = Decoupled(new ICacheMissReq) 68 val fromMSHR = Flipped(ValidIO(new ICacheMissResp)) 69} 70 71class ICachePMPBundle(implicit p: Parameters) extends ICacheBundle{ 72 val req = Valid(new PMPReqBundle()) 73 val resp = Input(new PMPRespBundle()) 74} 75 76class ICachePerfInfo(implicit p: Parameters) extends ICacheBundle{ 77 val only_0_hit = Bool() 78 val only_0_miss = Bool() 79 val hit_0_hit_1 = Bool() 80 val hit_0_miss_1 = Bool() 81 val miss_0_hit_1 = Bool() 82 val miss_0_miss_1 = Bool() 83 val hit_0_except_1 = Bool() 84 val miss_0_except_1 = Bool() 85 val except_0 = Bool() 86 val bank_hit = Vec(2,Bool()) 87 val hit = Bool() 88} 89 90class ICacheMainPipeInterface(implicit p: Parameters) extends ICacheBundle { 91 /*** internal interface ***/ 92 val metaArray = new ICacheMetaReqBundle 93 val dataArray = new ICacheDataReqBundle 94 val mshr = Vec(PortNumber, new ICacheMSHRBundle) 95 val errors = Output(Vec(PortNumber, new L1CacheErrorInfo)) 96 /*** outside interface ***/ 97 //val fetch = Vec(PortNumber, new ICacheMainPipeBundle) 98 /* when ftq.valid is high in T + 1 cycle 99 * the ftq component must be valid in T cycle 100 */ 101 val fetch = new ICacheMainPipeBundle 102 val pmp = Vec(PortNumber, new ICachePMPBundle) 103 val itlb = Vec(PortNumber, new TlbRequestIO) 104 val respStall = Input(Bool()) 105 val perfInfo = Output(new ICachePerfInfo) 106 107 val prefetchEnable = Output(Bool()) 108 val prefetchDisable = Output(Bool()) 109 val csr_parity_enable = Input(Bool()) 110 111} 112 113class ICacheMainPipe(implicit p: Parameters) extends ICacheModule 114{ 115 val io = IO(new ICacheMainPipeInterface) 116 117 /** Input/Output port */ 118 val (fromFtq, toIFU) = (io.fetch.req, io.fetch.resp) 119 val (toMeta, metaResp) = (io.metaArray.toIMeta, io.metaArray.fromIMeta) 120 val (toData, dataResp) = (io.dataArray.toIData, io.dataArray.fromIData) 121 val (toMSHR, fromMSHR) = (io.mshr.map(_.toMSHR), io.mshr.map(_.fromMSHR)) 122 val (toITLB, fromITLB) = (io.itlb.map(_.req), io.itlb.map(_.resp)) 123 val (toPMP, fromPMP) = (io.pmp.map(_.req), io.pmp.map(_.resp)) 124 io.itlb.foreach(_.req_kill := false.B) 125 126 //Ftq RegNext Register 127 val fromFtqReq = fromFtq.bits.pcMemRead 128 129 /** pipeline control signal */ 130 val s1_ready, s2_ready = Wire(Bool()) 131 val s0_fire, s1_fire , s2_fire = Wire(Bool()) 132 133 val missSwitchBit = RegInit(false.B) 134 135 /** replacement status register */ 136 val touch_sets = Seq.fill(2)(Wire(Vec(2, UInt(log2Ceil(nSets/2).W)))) 137 val touch_ways = Seq.fill(2)(Wire(Vec(2, Valid(UInt(log2Ceil(nWays).W)))) ) 138 139 /** 140 ****************************************************************************** 141 * ICache Stage 0 142 * - send req to ITLB and wait for tlb miss fixing 143 * - send req to Meta/Data SRAM 144 ****************************************************************************** 145 */ 146 147 /** s0 control */ 148 val s0_valid = fromFtq.valid 149 val s0_req_vaddr = (0 until partWayNum + 1).map(i => VecInit(Seq(fromFtqReq(i).startAddr, fromFtqReq(i).nextlineStart))) 150 val s0_req_vsetIdx = (0 until partWayNum + 1).map(i => VecInit(s0_req_vaddr(i).map(get_idx(_)))) 151 val s0_only_first = (0 until partWayNum + 1).map(i => fromFtq.bits.readValid(i) && !fromFtqReq(i).crossCacheline) 152 val s0_double_line = (0 until partWayNum + 1).map(i => fromFtq.bits.readValid(i) && fromFtqReq(i).crossCacheline) 153 154 val s0_final_valid = s0_valid 155 val s0_final_vaddr = s0_req_vaddr.head 156 val s0_final_vsetIdx = s0_req_vsetIdx.head 157 val s0_final_only_first = s0_only_first.head 158 val s0_final_double_line = s0_double_line.head 159 160 /** SRAM request */ 161 //0 -> metaread, 1,2,3 -> data, 3 -> code 4 -> itlb 162 val ftq_req_to_data_doubleline = s0_double_line.init 163 val ftq_req_to_data_vset_idx = s0_req_vsetIdx.init 164 val ftq_req_to_data_valid = fromFtq.bits.readValid.init 165 166 val ftq_req_to_meta_doubleline = s0_double_line.head 167 val ftq_req_to_meta_vset_idx = s0_req_vsetIdx.head 168 169 val ftq_req_to_itlb_only_first = s0_only_first.last 170 val ftq_req_to_itlb_doubleline = s0_double_line.last 171 val ftq_req_to_itlb_vaddr = s0_req_vaddr.last 172 val ftq_req_to_itlb_vset_idx = s0_req_vsetIdx.last 173 174 175 for(i <- 0 until partWayNum) { 176 toData.valid := ftq_req_to_data_valid(i) && !missSwitchBit 177 toData.bits(i).isDoubleLine := ftq_req_to_data_doubleline(i) 178 toData.bits(i).vSetIdx := ftq_req_to_data_vset_idx(i) 179 } 180 181 toMeta.valid := s0_valid && !missSwitchBit 182 toMeta.bits.isDoubleLine := ftq_req_to_meta_doubleline 183 toMeta.bits.vSetIdx := ftq_req_to_meta_vset_idx 184 185 186 toITLB(0).valid := s0_valid 187 toITLB(0).bits.size := 3.U // TODO: fix the size 188 toITLB(0).bits.vaddr := ftq_req_to_itlb_vaddr(0) 189 toITLB(0).bits.debug.pc := ftq_req_to_itlb_vaddr(0) 190 191 toITLB(1).valid := s0_valid && ftq_req_to_itlb_doubleline 192 toITLB(1).bits.size := 3.U // TODO: fix the size 193 toITLB(1).bits.vaddr := ftq_req_to_itlb_vaddr(1) 194 toITLB(1).bits.debug.pc := ftq_req_to_itlb_vaddr(1) 195 196 toITLB.map{port => 197 port.bits.cmd := TlbCmd.exec 198 port.bits.debug.robIdx := DontCare 199 port.bits.no_translate := false.B 200 port.bits.debug.isFirstIssue := DontCare 201 } 202 203 /** ITLB & ICACHE sync case 204 * when icache is not ready, but itlb is ready 205 * because itlb is non-block, then the req will take the port 206 * then itlb will unset the ready?? itlb is wrongly blocked. 207 * Solution: maybe give itlb a signal to tell whether acquire the slot? 208 */ 209 210 val itlb_can_go = toITLB(0).ready && toITLB(1).ready 211 val icache_can_go = toData.ready && toMeta.ready 212 val pipe_can_go = !missSwitchBit && s1_ready 213 val s0_can_go = itlb_can_go && icache_can_go && pipe_can_go 214 val s0_fetch_fire = s0_valid && s0_can_go 215 s0_fire := s0_fetch_fire 216 toITLB.map{port => port.bits.kill := !icache_can_go || !pipe_can_go} 217 218 //TODO: fix GTimer() condition 219 fromFtq.ready := s0_can_go 220 221 /** 222 ****************************************************************************** 223 * ICache Stage 1 224 * - get tlb resp data (exceptiong info and physical addresses) 225 * - get Meta/Data SRAM read responses (latched for pipeline stop) 226 * - tag compare/hit check 227 ****************************************************************************** 228 */ 229 230 /** s1 control */ 231 232 val s1_valid = generatePipeControl(lastFire = s0_fire, thisFire = s1_fire, thisFlush = false.B, lastFlush = false.B) 233 234 val s1_req_vaddr = RegEnable(s0_final_vaddr, s0_fire) 235 val s1_req_vsetIdx = RegEnable(s0_final_vsetIdx, s0_fire) 236 val s1_only_first = RegEnable(s0_final_only_first, s0_fire) 237 val s1_double_line = RegEnable(s0_final_double_line, s0_fire) 238 239 /** tlb response latch for pipeline stop */ 240 val tlb_back = fromITLB.map(_.fire()) 241 val tlb_need_back = VecInit((0 until PortNumber).map(i => ValidHold(s0_fire && toITLB(i).fire(), s1_fire, false.B))) 242 val tlb_already_recv = RegInit(VecInit(Seq.fill(PortNumber)(false.B))) 243 val tlb_ready_recv = VecInit((0 until PortNumber).map(i => RegNext(s0_fire, false.B) || (s1_valid && !tlb_already_recv(i)))) 244 val tlb_resp_valid = Wire(Vec(2, Bool())) 245 for (i <- 0 until PortNumber) { 246 tlb_resp_valid(i) := tlb_already_recv(i) || (tlb_ready_recv(i) && tlb_back(i)) 247 when (tlb_already_recv(i) && s1_fire) { 248 tlb_already_recv(i) := false.B 249 } 250 when (tlb_back(i) && tlb_ready_recv(i) && !s1_fire) { 251 tlb_already_recv(i) := true.B 252 } 253 fromITLB(i).ready := tlb_ready_recv(i) 254 } 255 assert(RegNext(Cat((0 until PortNumber).map(i => tlb_need_back(i) || !tlb_resp_valid(i))).andR(), true.B), 256 "when tlb should not back, tlb should not resp valid") 257 assert(RegNext(!s1_valid || Cat(tlb_need_back).orR, true.B), "when s1_valid, need at least one tlb_need_back") 258 assert(RegNext(s1_valid || !Cat(tlb_need_back).orR, true.B), "when !s1_valid, all the tlb_need_back should be false") 259 assert(RegNext(s1_valid || !Cat(tlb_already_recv).orR, true.B), "when !s1_valid, should not tlb_already_recv") 260 assert(RegNext(s1_valid || !Cat(tlb_resp_valid).orR, true.B), "when !s1_valid, should not tlb_resp_valid") 261 262 val tlbRespPAddr = VecInit((0 until PortNumber).map(i => ResultHoldBypass(valid = tlb_back(i), data = fromITLB(i).bits.paddr(0)))) 263 val tlbExcpPF = VecInit((0 until PortNumber).map(i => ResultHoldBypass(valid = tlb_back(i), data = fromITLB(i).bits.excp(0).pf.instr) && tlb_need_back(i))) 264 val tlbExcpAF = VecInit((0 until PortNumber).map(i => ResultHoldBypass(valid = tlb_back(i), data = fromITLB(i).bits.excp(0).af.instr) && tlb_need_back(i))) 265 val tlbExcp = VecInit((0 until PortNumber).map(i => tlbExcpPF(i) || tlbExcpPF(i))) 266 267 val tlbRespAllValid = Cat((0 until PortNumber).map(i => !tlb_need_back(i) || tlb_resp_valid(i))).andR 268 s1_ready := s2_ready && tlbRespAllValid || !s1_valid 269 s1_fire := s1_valid && tlbRespAllValid && s2_ready 270 271 /** s1 hit check/tag compare */ 272 val s1_req_paddr = tlbRespPAddr 273 val s1_req_ptags = VecInit(s1_req_paddr.map(get_phy_tag(_))) 274 275 val s1_meta_ptags = ResultHoldBypass(data = metaResp.tags, valid = RegNext(s0_fire)) 276 val s1_meta_cohs = ResultHoldBypass(data = metaResp.cohs, valid = RegNext(s0_fire)) 277 val s1_meta_errors = ResultHoldBypass(data = metaResp.errors, valid = RegNext(s0_fire)) 278 279 val s1_data_cacheline = ResultHoldBypass(data = dataResp.datas, valid = RegNext(s0_fire)) 280 val s1_data_errorBits = ResultHoldBypass(data = dataResp.codes, valid = RegNext(s0_fire)) 281 282 val s1_tag_eq_vec = VecInit((0 until PortNumber).map( p => VecInit((0 until nWays).map( w => s1_meta_ptags(p)(w) === s1_req_ptags(p) )))) 283 val s1_tag_match_vec = VecInit((0 until PortNumber).map( k => VecInit(s1_tag_eq_vec(k).zipWithIndex.map{ case(way_tag_eq, w) => way_tag_eq && s1_meta_cohs(k)(w).isValid()}))) 284 val s1_tag_match = VecInit(s1_tag_match_vec.map(vector => ParallelOR(vector))) 285 286 val s1_port_hit = VecInit(Seq(s1_tag_match(0) && s1_valid && !tlbExcp(0), s1_tag_match(1) && s1_valid && s1_double_line && !tlbExcp(1) )) 287 val s1_bank_miss = VecInit(Seq(!s1_tag_match(0) && s1_valid && !tlbExcp(0), !s1_tag_match(1) && s1_valid && s1_double_line && !tlbExcp(1) )) 288 val s1_hit = (s1_port_hit(0) && s1_port_hit(1)) || (!s1_double_line && s1_port_hit(0)) 289 290 /** choose victim cacheline */ 291 val replacers = Seq.fill(PortNumber)(ReplacementPolicy.fromString(cacheParams.replacer,nWays,nSets/PortNumber)) 292 val s1_victim_oh = ResultHoldBypass(data = VecInit(replacers.zipWithIndex.map{case (replacer, i) => UIntToOH(replacer.way(s1_req_vsetIdx(i)))}), valid = RegNext(s0_fire)) 293 294 val s1_victim_coh = VecInit(s1_victim_oh.zipWithIndex.map {case(oh, port) => Mux1H(oh, s1_meta_cohs(port))}) 295 296 when(s1_valid){ 297 assert(PopCount(s1_tag_match_vec(0)) <= 1.U && PopCount(s1_tag_match_vec(1)) <= 1.U, "Multiple hit in main pipe") 298 } 299 300 ((replacers zip touch_sets) zip touch_ways).map{case ((r, s),w) => r.access(s,w)} 301 302 303 /** <PERF> replace victim way number */ 304 305 (0 until nWays).map{ w => 306 XSPerfAccumulate("line_0_hit_way_" + Integer.toString(w, 10), s1_fire && s1_port_hit(0) && OHToUInt(s1_tag_match_vec(0)) === w.U) 307 } 308 309 (0 until nWays).map{ w => 310 XSPerfAccumulate("line_0_victim_way_" + Integer.toString(w, 10), s1_fire && !s1_port_hit(0) && OHToUInt(s1_victim_oh(0)) === w.U) 311 } 312 313 (0 until nWays).map{ w => 314 XSPerfAccumulate("line_1_hit_way_" + Integer.toString(w, 10), s1_fire && s1_double_line && s1_port_hit(1) && OHToUInt(s1_tag_match_vec(1)) === w.U) 315 } 316 317 (0 until nWays).map{ w => 318 XSPerfAccumulate("line_1_victim_way_" + Integer.toString(w, 10), s1_fire && s1_double_line && !s1_port_hit(1) && OHToUInt(s1_victim_oh(1)) === w.U) 319 } 320 321 /** 322 ****************************************************************************** 323 * ICache Stage 2 324 * - send request to MSHR if ICache miss 325 * - generate secondary miss status/data registers 326 * - response to IFU 327 ****************************************************************************** 328 */ 329 330 /** s2 control */ 331 val s2_fetch_finish = Wire(Bool()) 332 333 val s2_valid = generatePipeControl(lastFire = s1_fire, thisFire = s2_fire, thisFlush = false.B, lastFlush = false.B) 334 val s2_miss_available = Wire(Bool()) 335 336 s2_ready := (s2_valid && s2_fetch_finish && !io.respStall) || (!s2_valid && s2_miss_available) 337 s2_fire := s2_valid && s2_fetch_finish && !io.respStall 338 339 /** s2 data */ 340 val mmio = fromPMP.map(port => port.mmio) // TODO: handle it 341 342 val (s2_req_paddr , s2_req_vaddr) = (RegEnable(s1_req_paddr, s1_fire), RegEnable(s1_req_vaddr, s1_fire)) 343 val s2_req_vsetIdx = RegEnable(s1_req_vsetIdx, s1_fire) 344 val s2_req_ptags = RegEnable(s1_req_ptags, s1_fire) 345 val s2_only_first = RegEnable(s1_only_first, s1_fire) 346 val s2_double_line = RegEnable(s1_double_line, s1_fire) 347 val s2_hit = RegEnable(s1_hit , s1_fire) 348 val s2_port_hit = RegEnable(s1_port_hit, s1_fire) 349 val s2_bank_miss = RegEnable(s1_bank_miss, s1_fire) 350 val s2_waymask = RegEnable(s1_victim_oh, s1_fire) 351 val s2_victim_coh = RegEnable(s1_victim_coh, s1_fire) 352 val s2_tag_match_vec = RegEnable(s1_tag_match_vec, s1_fire) 353 354 assert(RegNext(!s2_valid || s2_req_paddr(0)(11,0) === s2_req_vaddr(0)(11,0), true.B)) 355 356 /** status imply that s2 is a secondary miss (no need to resend miss request) */ 357 val sec_meet_vec = Wire(Vec(2, Bool())) 358 val s2_fixed_hit_vec = VecInit((0 until 2).map(i => s2_port_hit(i) || sec_meet_vec(i))) 359 val s2_fixed_hit = (s2_valid && s2_fixed_hit_vec(0) && s2_fixed_hit_vec(1) && s2_double_line) || (s2_valid && s2_fixed_hit_vec(0) && !s2_double_line) 360 361 val s2_meta_errors = RegEnable(s1_meta_errors, s1_fire) 362 val s2_data_errorBits = RegEnable(s1_data_errorBits, s1_fire) 363 val s2_data_cacheline = RegEnable(s1_data_cacheline, s1_fire) 364 365 val s2_data_errors = Wire(Vec(PortNumber,Vec(nWays, Bool()))) 366 367 (0 until PortNumber).map{ i => 368 val read_datas = s2_data_cacheline(i).asTypeOf(Vec(nWays,Vec(dataCodeUnitNum, UInt(dataCodeUnit.W)))) 369 val read_codes = s2_data_errorBits(i).asTypeOf(Vec(nWays,Vec(dataCodeUnitNum, UInt(dataCodeBits.W)))) 370 val data_full_wayBits = VecInit((0 until nWays).map( w => 371 VecInit((0 until dataCodeUnitNum).map(u => 372 Cat(read_codes(w)(u), read_datas(w)(u)))))) 373 val data_error_wayBits = VecInit((0 until nWays).map( w => 374 VecInit((0 until dataCodeUnitNum).map(u => 375 cacheParams.dataCode.decode(data_full_wayBits(w)(u)).error )))) 376 if(i == 0){ 377 (0 until nWays).map{ w => 378 s2_data_errors(i)(w) := RegNext(RegNext(s1_fire)) && RegNext(data_error_wayBits(w)).reduce(_||_) 379 } 380 } else { 381 (0 until nWays).map{ w => 382 s2_data_errors(i)(w) := RegNext(RegNext(s1_fire)) && RegNext(RegNext(s1_double_line)) && RegNext(data_error_wayBits(w)).reduce(_||_) 383 } 384 } 385 } 386 387 val s2_parity_meta_error = VecInit((0 until PortNumber).map(i => s2_meta_errors(i).reduce(_||_) && io.csr_parity_enable)) 388 val s2_parity_data_error = VecInit((0 until PortNumber).map(i => s2_data_errors(i).reduce(_||_) && io.csr_parity_enable)) 389 val s2_parity_error = VecInit((0 until PortNumber).map(i => RegNext(s2_parity_meta_error(i)) || s2_parity_data_error(i))) 390 391 for(i <- 0 until PortNumber){ 392 io.errors(i).valid := RegNext(s2_parity_error(i) && RegNext(RegNext(s1_fire))) 393 io.errors(i).report_to_beu := RegNext(s2_parity_error(i) && RegNext(RegNext(s1_fire))) 394 io.errors(i).paddr := RegNext(RegNext(s2_req_paddr(i))) 395 io.errors(i).source := DontCare 396 io.errors(i).source.tag := RegNext(RegNext(s2_parity_meta_error(i))) 397 io.errors(i).source.data := RegNext(s2_parity_data_error(i)) 398 io.errors(i).source.l2 := false.B 399 io.errors(i).opType := DontCare 400 io.errors(i).opType.fetch := true.B 401 } 402 XSError(s2_parity_error.reduce(_||_) && RegNext(RegNext(s1_fire)), "ICache has parity error in MainPaipe!") 403 404 405 /** exception and pmp logic **/ 406 //PMP Result 407 val s2_tlb_need_back = VecInit((0 until PortNumber).map(i => ValidHold(tlb_need_back(i) && s1_fire, s2_fire, false.B))) 408 val pmpExcpAF = Wire(Vec(PortNumber, Bool())) 409 pmpExcpAF(0) := fromPMP(0).instr && s2_tlb_need_back(0) 410 pmpExcpAF(1) := fromPMP(1).instr && s2_double_line && s2_tlb_need_back(1) 411 //exception information 412 //short delay exception signal 413 val s2_except_pf = RegEnable(tlbExcpPF, s1_fire) 414 val s2_except_tlb_af = RegEnable(tlbExcpAF, s1_fire) 415 //long delay exception signal 416 val s2_except_pmp_af = DataHoldBypass(pmpExcpAF, RegNext(s1_fire)) 417 // val s2_except_parity_af = VecInit(s2_parity_error(i) && RegNext(RegNext(s1_fire)) ) 418 419 val s2_except = VecInit((0 until 2).map{i => s2_except_pf(i) || s2_except_tlb_af(i)}) 420 val s2_has_except = s2_valid && (s2_except_tlb_af.reduce(_||_) || s2_except_pf.reduce(_||_)) 421 //MMIO 422 val s2_mmio = DataHoldBypass(io.pmp(0).resp.mmio && !s2_except_tlb_af(0) && !s2_except_pmp_af(0) && !s2_except_pf(0), RegNext(s1_fire)).asBool() && s2_valid 423 424 //send physical address to PMP 425 io.pmp.zipWithIndex.map { case (p, i) => 426 p.req.valid := s2_valid && !missSwitchBit 427 p.req.bits.addr := s2_req_paddr(i) 428 p.req.bits.size := 3.U // TODO 429 p.req.bits.cmd := TlbCmd.exec 430 } 431 432 /*** cacheline miss logic ***/ 433 val wait_idle :: wait_queue_ready :: wait_send_req :: wait_two_resp :: wait_0_resp :: wait_1_resp :: wait_one_resp ::wait_finish :: wait_pmp_except :: Nil = Enum(9) 434 val wait_state = RegInit(wait_idle) 435 436 val port_miss_fix = VecInit(Seq(fromMSHR(0).fire() && !s2_port_hit(0), fromMSHR(1).fire() && s2_double_line && !s2_port_hit(1) )) 437 438 // secondary miss record registers 439 class MissSlot(implicit p: Parameters) extends ICacheBundle { 440 val m_vSetIdx = UInt(idxBits.W) 441 val m_pTag = UInt(tagBits.W) 442 val m_data = UInt(blockBits.W) 443 val m_corrupt = Bool() 444 } 445 446 val missSlot = Seq.fill(2)(RegInit(0.U.asTypeOf(new MissSlot))) 447 val m_invalid :: m_valid :: m_refilled :: m_flushed :: m_wait_sec_miss :: m_check_final ::Nil = Enum(6) 448 val missStateQueue = RegInit(VecInit(Seq.fill(2)(m_invalid)) ) 449 val reservedRefillData = Wire(Vec(2, UInt(blockBits.W))) 450 451 s2_miss_available := VecInit(missStateQueue.map(entry => entry === m_invalid || entry === m_wait_sec_miss)).reduce(_&&_) 452 453 val fix_sec_miss = Wire(Vec(4, Bool())) 454 val sec_meet_0_miss = fix_sec_miss(0) || fix_sec_miss(2) 455 val sec_meet_1_miss = fix_sec_miss(1) || fix_sec_miss(3) 456 sec_meet_vec := VecInit(Seq(sec_meet_0_miss,sec_meet_1_miss )) 457 458 /*** miss/hit pattern: <Control Signal> only raise at the first cycle of s2_valid ***/ 459 val cacheline_0_hit = (s2_port_hit(0) || sec_meet_0_miss) 460 val cacheline_0_miss = !s2_port_hit(0) && !sec_meet_0_miss 461 462 val cacheline_1_hit = (s2_port_hit(1) || sec_meet_1_miss) 463 val cacheline_1_miss = !s2_port_hit(1) && !sec_meet_1_miss 464 465 val only_0_miss = RegNext(s1_fire) && cacheline_0_miss && !s2_double_line && !s2_has_except && !s2_mmio 466 val only_0_hit = RegNext(s1_fire) && cacheline_0_hit && !s2_double_line && !s2_mmio 467 val hit_0_hit_1 = RegNext(s1_fire) && cacheline_0_hit && cacheline_1_hit && s2_double_line && !s2_mmio 468 val hit_0_miss_1 = RegNext(s1_fire) && cacheline_0_hit && cacheline_1_miss && s2_double_line && !s2_has_except && !s2_mmio 469 val miss_0_hit_1 = RegNext(s1_fire) && cacheline_0_miss && cacheline_1_hit && s2_double_line && !s2_has_except && !s2_mmio 470 val miss_0_miss_1 = RegNext(s1_fire) && cacheline_0_miss && cacheline_1_miss && s2_double_line && !s2_has_except && !s2_mmio 471 472 val hit_0_except_1 = RegNext(s1_fire) && s2_double_line && !s2_except(0) && s2_except(1) && cacheline_0_hit 473 val miss_0_except_1 = RegNext(s1_fire) && s2_double_line && !s2_except(0) && s2_except(1) && cacheline_0_miss 474 val except_0 = RegNext(s1_fire) && s2_except(0) 475 476 def holdReleaseLatch(valid: Bool, release: Bool, flush: Bool): Bool ={ 477 val bit = RegInit(false.B) 478 when(flush) { bit := false.B } 479 .elsewhen(valid && !release) { bit := true.B } 480 .elsewhen(release) { bit := false.B } 481 bit || valid 482 } 483 484 /*** miss/hit pattern latch: <Control Signal> latch the miss/hit patter if pipeline stop ***/ 485 val miss_0_hit_1_latch = holdReleaseLatch(valid = miss_0_hit_1, release = s2_fire, flush = false.B) 486 val miss_0_miss_1_latch = holdReleaseLatch(valid = miss_0_miss_1, release = s2_fire, flush = false.B) 487 val only_0_miss_latch = holdReleaseLatch(valid = only_0_miss, release = s2_fire, flush = false.B) 488 val hit_0_miss_1_latch = holdReleaseLatch(valid = hit_0_miss_1, release = s2_fire, flush = false.B) 489 490 val miss_0_except_1_latch = holdReleaseLatch(valid = miss_0_except_1, release = s2_fire, flush = false.B) 491 val except_0_latch = holdReleaseLatch(valid = except_0, release = s2_fire, flush = false.B) 492 val hit_0_except_1_latch = holdReleaseLatch(valid = hit_0_except_1, release = s2_fire, flush = false.B) 493 494 val only_0_hit_latch = holdReleaseLatch(valid = only_0_hit, release = s2_fire, flush = false.B) 495 val hit_0_hit_1_latch = holdReleaseLatch(valid = hit_0_hit_1, release = s2_fire, flush = false.B) 496 497 498 /*** secondary miss judgment ***/ 499 500 def waitSecondComeIn(missState: UInt): Bool = (missState === m_wait_sec_miss) 501 502 def getMissSituat(slotNum : Int, missNum : Int ) :Bool = { 503 RegNext(s1_fire) && 504 RegNext(missSlot(slotNum).m_vSetIdx === s1_req_vsetIdx(missNum)) && 505 RegNext(missSlot(slotNum).m_pTag === s1_req_ptags(missNum)) && 506 !s2_port_hit(missNum) && 507 waitSecondComeIn(missStateQueue(slotNum)) 508 } 509 510 val miss_0_s2_0 = getMissSituat(slotNum = 0, missNum = 0) 511 val miss_0_s2_1 = getMissSituat(slotNum = 0, missNum = 1) 512 val miss_1_s2_0 = getMissSituat(slotNum = 1, missNum = 0) 513 val miss_1_s2_1 = getMissSituat(slotNum = 1, missNum = 1) 514 515 val miss_0_s2_0_latch = holdReleaseLatch(valid = miss_0_s2_0, release = s2_fire, flush = false.B) 516 val miss_0_s2_1_latch = holdReleaseLatch(valid = miss_0_s2_1, release = s2_fire, flush = false.B) 517 val miss_1_s2_0_latch = holdReleaseLatch(valid = miss_1_s2_0, release = s2_fire, flush = false.B) 518 val miss_1_s2_1_latch = holdReleaseLatch(valid = miss_1_s2_1, release = s2_fire, flush = false.B) 519 520 521 val slot_0_solve = fix_sec_miss(0) || fix_sec_miss(1) 522 val slot_1_solve = fix_sec_miss(2) || fix_sec_miss(3) 523 val slot_slove = VecInit(Seq(slot_0_solve, slot_1_solve)) 524 525 fix_sec_miss := VecInit(Seq(miss_0_s2_0_latch, miss_0_s2_1_latch, miss_1_s2_0_latch, miss_1_s2_1_latch)) 526 527 /*** reserved data for secondary miss ***/ 528 529 reservedRefillData(0) := DataHoldBypass(data = missSlot(0).m_data, valid = miss_0_s2_0 || miss_0_s2_1) 530 reservedRefillData(1) := DataHoldBypass(data = missSlot(1).m_data, valid = miss_1_s2_0 || miss_1_s2_1) 531 532 /*** miss state machine ***/ 533 534 //deal with not-cache-hit pmp af 535 val only_pmp_af = Wire(Vec(2, Bool())) 536 only_pmp_af(0) := s2_except_pmp_af(0) && cacheline_0_miss && !s2_except(0) && s2_valid 537 only_pmp_af(1) := s2_except_pmp_af(1) && cacheline_1_miss && !s2_except(1) && s2_valid && s2_double_line 538 539 switch(wait_state){ 540 is(wait_idle){ 541 when(only_pmp_af(0) || only_pmp_af(1) || s2_mmio){ 542 //should not send req to MissUnit when there is an access exception in PMP 543 //But to avoid using pmp exception in control signal (like s2_fire), should delay 1 cycle. 544 //NOTE: pmp exception cache line also could hit in ICache, but the result is meaningless. Just give the exception signals. 545 wait_state := wait_finish 546 }.elsewhen(miss_0_except_1_latch){ 547 wait_state := Mux(toMSHR(0).ready, wait_queue_ready ,wait_idle ) 548 }.elsewhen( only_0_miss_latch || miss_0_hit_1_latch){ 549 wait_state := Mux(toMSHR(0).ready, wait_queue_ready ,wait_idle ) 550 }.elsewhen(hit_0_miss_1_latch){ 551 wait_state := Mux(toMSHR(1).ready, wait_queue_ready ,wait_idle ) 552 }.elsewhen( miss_0_miss_1_latch ){ 553 wait_state := Mux(toMSHR(0).ready && toMSHR(1).ready, wait_queue_ready ,wait_idle) 554 } 555 } 556 557 is(wait_queue_ready){ 558 wait_state := wait_send_req 559 } 560 561 is(wait_send_req) { 562 when(miss_0_except_1_latch || only_0_miss_latch || hit_0_miss_1_latch || miss_0_hit_1_latch){ 563 wait_state := wait_one_resp 564 }.elsewhen( miss_0_miss_1_latch ){ 565 wait_state := wait_two_resp 566 } 567 } 568 569 is(wait_one_resp) { 570 when( (miss_0_except_1_latch ||only_0_miss_latch || miss_0_hit_1_latch) && fromMSHR(0).fire()){ 571 wait_state := wait_finish 572 }.elsewhen( hit_0_miss_1_latch && fromMSHR(1).fire()){ 573 wait_state := wait_finish 574 } 575 } 576 577 is(wait_two_resp) { 578 when(fromMSHR(0).fire() && fromMSHR(1).fire()){ 579 wait_state := wait_finish 580 }.elsewhen( !fromMSHR(0).fire() && fromMSHR(1).fire() ){ 581 wait_state := wait_0_resp 582 }.elsewhen(fromMSHR(0).fire() && !fromMSHR(1).fire()){ 583 wait_state := wait_1_resp 584 } 585 } 586 587 is(wait_0_resp) { 588 when(fromMSHR(0).fire()){ 589 wait_state := wait_finish 590 } 591 } 592 593 is(wait_1_resp) { 594 when(fromMSHR(1).fire()){ 595 wait_state := wait_finish 596 } 597 } 598 599 is(wait_finish) {when(s2_fire) {wait_state := wait_idle } 600 } 601 } 602 603 604 /*** send request to MissUnit ***/ 605 606 (0 until 2).map { i => 607 if(i == 1) toMSHR(i).valid := (hit_0_miss_1_latch || miss_0_miss_1_latch) && wait_state === wait_queue_ready && !s2_mmio 608 else toMSHR(i).valid := (only_0_miss_latch || miss_0_hit_1_latch || miss_0_miss_1_latch || miss_0_except_1_latch) && wait_state === wait_queue_ready && !s2_mmio 609 toMSHR(i).bits.paddr := s2_req_paddr(i) 610 toMSHR(i).bits.vaddr := s2_req_vaddr(i) 611 toMSHR(i).bits.waymask := s2_waymask(i) 612 toMSHR(i).bits.coh := s2_victim_coh(i) 613 614 615 when(toMSHR(i).fire() && missStateQueue(i) === m_invalid){ 616 missStateQueue(i) := m_valid 617 missSlot(i).m_vSetIdx := s2_req_vsetIdx(i) 618 missSlot(i).m_pTag := get_phy_tag(s2_req_paddr(i)) 619 } 620 621 when(fromMSHR(i).fire() && missStateQueue(i) === m_valid ){ 622 missStateQueue(i) := m_refilled 623 missSlot(i).m_data := fromMSHR(i).bits.data 624 missSlot(i).m_corrupt := fromMSHR(i).bits.corrupt 625 } 626 627 628 when(s2_fire && missStateQueue(i) === m_refilled){ 629 missStateQueue(i) := m_wait_sec_miss 630 } 631 632 /*** Only the first cycle to check whether meet the secondary miss ***/ 633 when(missStateQueue(i) === m_wait_sec_miss){ 634 /*** The seondary req has been fix by this slot and another also hit || the secondary req for other cacheline and hit ***/ 635 when((slot_slove(i) && s2_fire) || (!slot_slove(i) && s2_fire) ) { 636 missStateQueue(i) := m_invalid 637 } 638 /*** The seondary req has been fix by this slot but another miss/f3 not ready || the seondary req for other cacheline and miss ***/ 639 .elsewhen((slot_slove(i) && !s2_fire && s2_valid) || (s2_valid && !slot_slove(i) && !s2_fire) ){ 640 missStateQueue(i) := m_check_final 641 } 642 } 643 644 when(missStateQueue(i) === m_check_final && toMSHR(i).fire()){ 645 missStateQueue(i) := m_valid 646 missSlot(i).m_vSetIdx := s2_req_vsetIdx(i) 647 missSlot(i).m_pTag := get_phy_tag(s2_req_paddr(i)) 648 }.elsewhen(missStateQueue(i) === m_check_final) { 649 missStateQueue(i) := m_invalid 650 } 651 } 652 653 io.prefetchEnable := false.B 654 io.prefetchDisable := false.B 655 when(toMSHR.map(_.valid).reduce(_||_)){ 656 missSwitchBit := true.B 657 io.prefetchEnable := true.B 658 }.elsewhen(missSwitchBit && s2_fetch_finish){ 659 missSwitchBit := false.B 660 io.prefetchDisable := true.B 661 } 662 663 664 val miss_all_fix = wait_state === wait_finish 665 666 s2_fetch_finish := ((s2_valid && s2_fixed_hit) || miss_all_fix || hit_0_except_1_latch || except_0_latch) 667 668 /** update replacement status register: 0 is hit access/ 1 is miss access */ 669 (touch_ways zip touch_sets).zipWithIndex.map{ case((t_w,t_s), i) => 670 t_s(0) := s2_req_vsetIdx(i) 671 t_w(0).valid := s2_valid && s2_port_hit(i) 672 t_w(0).bits := OHToUInt(s2_tag_match_vec(i)) 673 674 t_s(1) := s2_req_vsetIdx(i) 675 t_w(1).valid := s2_valid && !s2_port_hit(i) 676 t_w(1).bits := OHToUInt(s2_waymask(i)) 677 } 678 679 //** use hit one-hot select data 680 val s2_hit_datas = VecInit(s2_data_cacheline.zipWithIndex.map { case(bank, i) => 681 val port_hit_data = Mux1H(s2_tag_match_vec(i).asUInt, bank) 682 port_hit_data 683 }) 684 685 val s2_register_datas = Wire(Vec(2, UInt(blockBits.W))) 686 687 s2_register_datas.zipWithIndex.map{case(bank,i) => 688 // if(i == 0) bank := Mux(s2_port_hit(i), s2_hit_datas(i), Mux(miss_0_s2_0_latch,reservedRefillData(0), Mux(miss_1_s2_0_latch,reservedRefillData(1), missSlot(0).m_data))) 689 // else bank := Mux(s2_port_hit(i), s2_hit_datas(i), Mux(miss_0_s2_1_latch,reservedRefillData(0), Mux(miss_1_s2_1_latch,reservedRefillData(1), missSlot(1).m_data))) 690 if(i == 0) bank := Mux(miss_0_s2_0_latch,reservedRefillData(0), Mux(miss_1_s2_0_latch,reservedRefillData(1), missSlot(0).m_data)) 691 else bank := Mux(miss_0_s2_1_latch,reservedRefillData(0), Mux(miss_1_s2_1_latch,reservedRefillData(1), missSlot(1).m_data)) 692 } 693 694 /** response to IFU */ 695 696 (0 until PortNumber).map{ i => 697 if(i ==0) toIFU(i).valid := s2_fire 698 else toIFU(i).valid := s2_fire && s2_double_line 699 //when select is high, use sramData. Otherwise, use registerData. 700 toIFU(i).bits.registerData := s2_register_datas(i) 701 toIFU(i).bits.sramData := s2_hit_datas(i) 702 toIFU(i).bits.select := s2_port_hit(i) 703 toIFU(i).bits.paddr := s2_req_paddr(i) 704 toIFU(i).bits.vaddr := s2_req_vaddr(i) 705 toIFU(i).bits.tlbExcp.pageFault := s2_except_pf(i) 706 toIFU(i).bits.tlbExcp.accessFault := s2_except_tlb_af(i) || missSlot(i).m_corrupt || s2_except_pmp_af(i) 707 toIFU(i).bits.tlbExcp.mmio := s2_mmio 708 709 when(RegNext(s2_fire && missSlot(i).m_corrupt)){ 710 io.errors(i).valid := true.B 711 io.errors(i).report_to_beu := false.B // l2 should have report that to bus error unit, no need to do it again 712 io.errors(i).paddr := RegNext(s2_req_paddr(i)) 713 io.errors(i).source.tag := false.B 714 io.errors(i).source.data := false.B 715 io.errors(i).source.l2 := true.B 716 } 717 } 718 719 io.perfInfo.only_0_hit := only_0_hit_latch 720 io.perfInfo.only_0_miss := only_0_miss_latch 721 io.perfInfo.hit_0_hit_1 := hit_0_hit_1_latch 722 io.perfInfo.hit_0_miss_1 := hit_0_miss_1_latch 723 io.perfInfo.miss_0_hit_1 := miss_0_hit_1_latch 724 io.perfInfo.miss_0_miss_1 := miss_0_miss_1_latch 725 io.perfInfo.hit_0_except_1 := hit_0_except_1_latch 726 io.perfInfo.miss_0_except_1 := miss_0_except_1_latch 727 io.perfInfo.except_0 := except_0_latch 728 io.perfInfo.bank_hit(0) := only_0_miss_latch || hit_0_hit_1_latch || hit_0_miss_1_latch || hit_0_except_1_latch 729 io.perfInfo.bank_hit(1) := miss_0_hit_1_latch || hit_0_hit_1_latch 730 io.perfInfo.hit := hit_0_hit_1_latch || only_0_hit_latch || hit_0_except_1_latch || except_0_latch 731 732 /** <PERF> fetch bubble generated by icache miss*/ 733 734 XSPerfAccumulate("icache_bubble_s2_miss", s2_valid && !s2_fetch_finish ) 735 736 val tlb_miss_vec = VecInit((0 until PortNumber).map(i => toITLB(i).valid && s0_can_go && fromITLB(i).bits.miss)) 737 val tlb_has_miss = tlb_miss_vec.reduce(_ || _) 738 XSPerfAccumulate("icache_bubble_s0_tlb_miss", s0_valid && tlb_has_miss ) 739} 740