1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 34import xiangshan.frontend._ 35import xiangshan.frontend.icache.ICacheParameters 36 37import scala.math.min 38 39case object XSTileKey extends Field[Seq[XSCoreParameters]] 40 41case object XSCoreParamsKey extends Field[XSCoreParameters] 42 43case class XSCoreParameters 44( 45 HasPrefetch: Boolean = false, 46 HartId: Int = 0, 47 XLEN: Int = 64, 48 VLEN: Int = 128, 49 HasMExtension: Boolean = true, 50 HasCExtension: Boolean = true, 51 HasDiv: Boolean = true, 52 HasICache: Boolean = true, 53 HasDCache: Boolean = true, 54 AddrBits: Int = 64, 55 VAddrBits: Int = 39, 56 HasFPU: Boolean = true, 57 HasVPU: Boolean = true, 58 HasCustomCSRCacheOp: Boolean = true, 59 FetchWidth: Int = 8, 60 AsidLength: Int = 16, 61 EnableBPU: Boolean = true, 62 EnableBPD: Boolean = true, 63 EnableRAS: Boolean = true, 64 EnableLB: Boolean = false, 65 EnableLoop: Boolean = true, 66 EnableSC: Boolean = true, 67 EnbaleTlbDebug: Boolean = false, 68 EnableJal: Boolean = false, 69 EnableFauFTB: Boolean = true, 70 UbtbGHRLength: Int = 4, 71 // HistoryLength: Int = 512, 72 EnableGHistDiff: Boolean = true, 73 UbtbSize: Int = 256, 74 FtbSize: Int = 2048, 75 RasSize: Int = 32, 76 CacheLineSize: Int = 512, 77 FtbWays: Int = 4, 78 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 79 // Sets Hist Tag 80 // Seq(( 2048, 2, 8), 81 // ( 2048, 9, 8), 82 // ( 2048, 13, 8), 83 // ( 2048, 20, 8), 84 // ( 2048, 26, 8), 85 // ( 2048, 44, 8), 86 // ( 2048, 73, 8), 87 // ( 2048, 256, 8)), 88 Seq(( 4096, 8, 8), 89 ( 4096, 13, 8), 90 ( 4096, 32, 8), 91 ( 4096, 119, 8)), 92 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 93 // Sets Hist Tag 94 Seq(( 256, 4, 9), 95 ( 256, 8, 9), 96 ( 512, 13, 9), 97 ( 512, 16, 9), 98 ( 512, 32, 9)), 99 SCNRows: Int = 512, 100 SCNTables: Int = 4, 101 SCCtrBits: Int = 6, 102 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 103 numBr: Int = 2, 104 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 105 ((resp_in: BranchPredictionResp, p: Parameters) => { 106 val ftb = Module(new FTB()(p)) 107 val ubtb =Module(new FauFTB()(p)) 108 // val bim = Module(new BIM()(p)) 109 val tage = Module(new Tage_SC()(p)) 110 val ras = Module(new RAS()(p)) 111 val ittage = Module(new ITTage()(p)) 112 val preds = Seq(ubtb, tage, ftb, ittage, ras) 113 preds.map(_.io := DontCare) 114 115 // ubtb.io.resp_in(0) := resp_in 116 // bim.io.resp_in(0) := ubtb.io.resp 117 // btb.io.resp_in(0) := bim.io.resp 118 // tage.io.resp_in(0) := btb.io.resp 119 // loop.io.resp_in(0) := tage.io.resp 120 ubtb.io.in.bits.resp_in(0) := resp_in 121 tage.io.in.bits.resp_in(0) := ubtb.io.out 122 ftb.io.in.bits.resp_in(0) := tage.io.out 123 ittage.io.in.bits.resp_in(0) := ftb.io.out 124 ras.io.in.bits.resp_in(0) := ittage.io.out 125 126 (preds, ras.io.out) 127 }), 128 IBufSize: Int = 48, 129 DecodeWidth: Int = 6, 130 RenameWidth: Int = 6, 131 CommitWidth: Int = 6, 132 FtqSize: Int = 64, 133 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 134 NRPhyRegs: Int = 192, 135 IntPhyRegs: Int = 192, 136 VfPhyRegs: Int = 192, 137 LoadQueueSize: Int = 80, 138 LoadQueueNWriteBanks: Int = 8, 139 StoreQueueSize: Int = 64, 140 StoreQueueNWriteBanks: Int = 8, 141 VlsQueueSize: Int = 8, 142 RobSize: Int = 256, 143 dpParams: DispatchParameters = DispatchParameters( 144 IntDqSize = 16, 145 FpDqSize = 16, 146 LsDqSize = 16, 147 IntDqDeqWidth = 6, 148 FpDqDeqWidth = 6, 149 LsDqDeqWidth = 6, 150 ), 151 intPreg: PregParams = IntPregParams( 152 numEntries = 64, 153 numRead = 14, 154 numWrite = 8, 155 ), 156 vfPreg: VfPregParams = VfPregParams( 157 numEntries = 64, 158 numRead = 14, 159 numWrite = 8, 160 ), 161 LoadPipelineWidth: Int = 2, 162 StorePipelineWidth: Int = 2, 163 VecMemSrcInWidth: Int = 2, 164 VecMemInstWbWidth: Int = 1, 165 VecMemDispatchWidth: Int = 1, 166 StoreBufferSize: Int = 16, 167 StoreBufferThreshold: Int = 7, 168 EnsbufferWidth: Int = 2, 169 UncacheBufferSize: Int = 4, 170 EnableLoadToLoadForward: Boolean = true, 171 EnableFastForward: Boolean = false, 172 EnableLdVioCheckAfterReset: Boolean = true, 173 EnableSoftPrefetchAfterReset: Boolean = true, 174 EnableCacheErrorAfterReset: Boolean = true, 175 EnableDCacheWPU: Boolean = false, 176 EnableAccurateLoadError: Boolean = true, 177 EnableUncacheWriteOutstanding: Boolean = true, 178 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 179 ReSelectLen: Int = 6, // load replay queue replay select counter len 180 itlbParameters: TLBParameters = TLBParameters( 181 name = "itlb", 182 fetchi = true, 183 useDmode = false, 184 normalNWays = 32, 185 normalReplacer = Some("plru"), 186 superNWays = 4, 187 superReplacer = Some("plru") 188 ), 189 ldtlbParameters: TLBParameters = TLBParameters( 190 name = "ldtlb", 191 normalNSets = 64, 192 normalNWays = 1, 193 normalAssociative = "sa", 194 normalReplacer = Some("setplru"), 195 superNWays = 16, 196 normalAsVictim = true, 197 outReplace = false, 198 partialStaticPMP = true, 199 outsideRecvFlush = true, 200 saveLevel = true 201 ), 202 sttlbParameters: TLBParameters = TLBParameters( 203 name = "sttlb", 204 normalNSets = 64, 205 normalNWays = 1, 206 normalAssociative = "sa", 207 normalReplacer = Some("setplru"), 208 superNWays = 16, 209 normalAsVictim = true, 210 outReplace = false, 211 partialStaticPMP = true, 212 outsideRecvFlush = true, 213 saveLevel = true 214 ), 215 refillBothTlb: Boolean = false, 216 btlbParameters: TLBParameters = TLBParameters( 217 name = "btlb", 218 normalNSets = 1, 219 normalNWays = 64, 220 superNWays = 4, 221 ), 222 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 223 NumPerfCounters: Int = 16, 224 icacheParameters: ICacheParameters = ICacheParameters( 225 tagECC = Some("parity"), 226 dataECC = Some("parity"), 227 replacer = Some("setplru"), 228 nMissEntries = 2, 229 nProbeEntries = 2, 230 nPrefetchEntries = 2, 231 hasPrefetch = true, 232 ), 233 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 234 tagECC = Some("secded"), 235 dataECC = Some("secded"), 236 replacer = Some("setplru"), 237 nMissEntries = 16, 238 nProbeEntries = 8, 239 nReleaseEntries = 18 240 )), 241 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 242 name = "l2", 243 level = 2, 244 ways = 8, 245 sets = 1024, // default 512KB L2 246 prefetch = Some(huancun.prefetch.BOPParameters()) 247 )), 248 L2NBanks: Int = 1, 249 usePTWRepeater: Boolean = false, 250 softPTW: Boolean = false, // dpi-c debug only 251 softPTWDelay: Int = 1 252){ 253 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 254 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 255 256 def intSchdParams = { 257 implicit val schdType: SchedulerType = IntScheduler() 258 val pregBits = intPreg.addrWidth 259 val numRfRead = intPreg.numRead 260 val numRfWrite = intPreg.numWrite 261 SchdBlockParams(Seq( 262 IssueBlockParams(Seq( 263 ExeUnitParams(Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 2)), Seq(IntRD(1, 2)))), 264 ExeUnitParams(Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(0, 1)), Seq(IntRD(1, 1)))), 265 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 266 IssueBlockParams(Seq( 267 ExeUnitParams(Seq(DivCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0)))), 268 ExeUnitParams(Seq(DivCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 269 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 270 IssueBlockParams(Seq( 271 ExeUnitParams(Seq(BrhCfg, JmpCfg, CsrCfg, FenceCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(4, 1)), Seq(IntRD(5, 1)))), 272 ExeUnitParams(Seq(BrhCfg), Seq(), Seq(Seq(IntRD(6, 1)), Seq(IntRD(7, 1)))), 273 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 274 IssueBlockParams(Seq( 275 ExeUnitParams(Seq(I2fCfg), Seq(VecWB(port = 6, Int.MaxValue)), Seq(Seq(IntRD(0, 0)))), 276 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2) 277 ), 278 numPregs = intPreg.numEntries, 279 numRfReadWrite = Some((numRfRead, numRfWrite)), 280 numDeqOutside = 0, 281 schdType = schdType, 282 rfDataWidth = intPreg.dataCfg.dataWidth, 283 numUopIn = dpParams.IntDqDeqWidth, 284 ) 285 } 286 def vfSchdParams = { 287 implicit val schdType: SchedulerType = VfScheduler() 288 val pregBits = vfPreg.addrWidth 289 val numRfRead = vfPreg.numRead 290 val numRfWrite = vfPreg.numWrite 291 SchdBlockParams(Seq( 292 IssueBlockParams(Seq( 293 ExeUnitParams(Seq(FmacCfg), Seq(VecWB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)))), 294 ExeUnitParams(Seq(FmacCfg), Seq(VecWB(port = 1, 0)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 295 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 4), 296 IssueBlockParams(Seq( 297 ExeUnitParams(Seq(F2fCfg, F2iCfg, FDivSqrtCfg), Seq(VecWB(port = 2, 0), IntWB(port = 7, 0)), Seq(Seq(VfRD(6, 0)), Seq(VfRD(7, 0)))), 298 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 4), 299 ), 300 numPregs = vfPreg.numEntries, 301 numRfReadWrite = Some((numRfRead, numRfWrite)), 302 numDeqOutside = 0, 303 schdType = schdType, 304 rfDataWidth = vfPreg.dataCfg.dataWidth, 305 numUopIn = dpParams.FpDqDeqWidth, 306 ) 307 } 308 def memSchdParams = { 309 implicit val schdType: SchedulerType = MemScheduler() 310 val pregBits = vfPreg.addrWidth max intPreg.addrWidth 311 val rfDataWidth = 64 312 313 SchdBlockParams(Seq( 314 IssueBlockParams(Seq( 315 ExeUnitParams(Seq(LduCfg), Seq(IntWB(5, 0), VecWB(4, 0)), Seq(Seq(IntRD(8, 0)))), 316 ExeUnitParams(Seq(LduCfg), Seq(IntWB(6, 0), VecWB(5, 0)), Seq(Seq(IntRD(9, 0)))), 317 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 318 IssueBlockParams(Seq( 319 ExeUnitParams(Seq(StaCfg), Seq(), Seq(Seq(IntRD(10, 0)))), 320 ExeUnitParams(Seq(StaCfg), Seq(), Seq(Seq(IntRD(11, 0)))), 321 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 322 IssueBlockParams(Seq( 323 ExeUnitParams(Seq(StdCfg), Seq(), Seq(Seq(IntRD(12, 0), VfRD(12, 0)))), 324 ExeUnitParams(Seq(StdCfg), Seq(), Seq(Seq(IntRD(13, 0), VfRD(13, 0)))), 325 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 326 ), 327 numPregs = intPreg.numEntries max vfPreg.numEntries, 328 numRfReadWrite = None, 329 numDeqOutside = 0, 330 schdType = schdType, 331 rfDataWidth = rfDataWidth, 332 numUopIn = dpParams.LsDqDeqWidth, 333 ) 334 } 335 336 def backendParams: BackendParams = backend.BackendParams(Map( 337 IntScheduler() -> intSchdParams, 338 VfScheduler() -> vfSchdParams, 339 MemScheduler() -> memSchdParams, 340 ), Seq( 341 intPreg, 342 vfPreg, 343 )) 344} 345 346case object DebugOptionsKey extends Field[DebugOptions] 347 348case class DebugOptions 349( 350 FPGAPlatform: Boolean = false, 351 EnableDifftest: Boolean = false, 352 AlwaysBasicDiff: Boolean = true, 353 EnableDebug: Boolean = false, 354 EnablePerfDebug: Boolean = true, 355 UseDRAMSim: Boolean = false, 356 EnableTopDown: Boolean = false 357) 358 359trait HasXSParameter { 360 361 implicit val p: Parameters 362 363 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 364 365 val coreParams = p(XSCoreParamsKey) 366 val env = p(DebugOptionsKey) 367 368 val XLEN = coreParams.XLEN 369 val VLEN = coreParams.VLEN 370 val minFLen = 32 371 val fLen = 64 372 def xLen = XLEN 373 374 val HasMExtension = coreParams.HasMExtension 375 val HasCExtension = coreParams.HasCExtension 376 val HasDiv = coreParams.HasDiv 377 val HasIcache = coreParams.HasICache 378 val HasDcache = coreParams.HasDCache 379 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 380 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 381 val AsidLength = coreParams.AsidLength 382 val ReSelectLen = coreParams.ReSelectLen 383 val AddrBytes = AddrBits / 8 // unused 384 val DataBits = XLEN 385 val DataBytes = DataBits / 8 386 val HasFPU = coreParams.HasFPU 387 val HasVPU = coreParams.HasVPU 388 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 389 val FetchWidth = coreParams.FetchWidth 390 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 391 val EnableBPU = coreParams.EnableBPU 392 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 393 val EnableRAS = coreParams.EnableRAS 394 val EnableLB = coreParams.EnableLB 395 val EnableLoop = coreParams.EnableLoop 396 val EnableSC = coreParams.EnableSC 397 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 398 val HistoryLength = coreParams.HistoryLength 399 val EnableGHistDiff = coreParams.EnableGHistDiff 400 val UbtbGHRLength = coreParams.UbtbGHRLength 401 val UbtbSize = coreParams.UbtbSize 402 val EnableFauFTB = coreParams.EnableFauFTB 403 val FtbSize = coreParams.FtbSize 404 val FtbWays = coreParams.FtbWays 405 val RasSize = coreParams.RasSize 406 407 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 408 coreParams.branchPredictor(resp_in, p) 409 } 410 val numBr = coreParams.numBr 411 val TageTableInfos = coreParams.TageTableInfos 412 val TageBanks = coreParams.numBr 413 val SCNRows = coreParams.SCNRows 414 val SCCtrBits = coreParams.SCCtrBits 415 val SCHistLens = coreParams.SCHistLens 416 val SCNTables = coreParams.SCNTables 417 418 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 419 case ((n, cb), h) => (n, cb, h) 420 } 421 val ITTageTableInfos = coreParams.ITTageTableInfos 422 type FoldedHistoryInfo = Tuple2[Int, Int] 423 val foldedGHistInfos = 424 (TageTableInfos.map{ case (nRows, h, t) => 425 if (h > 0) 426 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 427 else 428 Set[FoldedHistoryInfo]() 429 }.reduce(_++_).toSet ++ 430 SCTableInfos.map{ case (nRows, _, h) => 431 if (h > 0) 432 Set((h, min(log2Ceil(nRows/TageBanks), h))) 433 else 434 Set[FoldedHistoryInfo]() 435 }.reduce(_++_).toSet ++ 436 ITTageTableInfos.map{ case (nRows, h, t) => 437 if (h > 0) 438 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 439 else 440 Set[FoldedHistoryInfo]() 441 }.reduce(_++_) ++ 442 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 443 ).toList 444 445 446 447 val CacheLineSize = coreParams.CacheLineSize 448 val CacheLineHalfWord = CacheLineSize / 16 449 val ExtHistoryLength = HistoryLength + 64 450 val IBufSize = coreParams.IBufSize 451 val DecodeWidth = coreParams.DecodeWidth 452 val RenameWidth = coreParams.RenameWidth 453 val CommitWidth = coreParams.CommitWidth 454 val FtqSize = coreParams.FtqSize 455 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 456 val NRPhyRegs = coreParams.NRPhyRegs 457 val PhyRegIdxWidth = log2Up(NRPhyRegs) 458 val IntPhyRegs = coreParams.IntPhyRegs 459 val VfPhyRegs = coreParams.VfPhyRegs 460 val IntPregIdxWidth = log2Up(IntPhyRegs) 461 val VfPregIdxWidth = log2Up(VfPhyRegs) 462 val RobSize = coreParams.RobSize 463 val IntRefCounterWidth = log2Ceil(RobSize) 464 val LoadQueueSize = coreParams.LoadQueueSize 465 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 466 val StoreQueueSize = coreParams.StoreQueueSize 467 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 468 val VlsQueueSize = coreParams.VlsQueueSize 469 val dpParams = coreParams.dpParams 470 471 def backendParams: BackendParams = coreParams.backendParams 472 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 473 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 474 val LoadPipelineWidth = coreParams.LoadPipelineWidth 475 val StorePipelineWidth = coreParams.StorePipelineWidth 476 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 477 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 478 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 479 val StoreBufferSize = coreParams.StoreBufferSize 480 val StoreBufferThreshold = coreParams.StoreBufferThreshold 481 val EnsbufferWidth = coreParams.EnsbufferWidth 482 val UncacheBufferSize = coreParams.UncacheBufferSize 483 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 484 val EnableFastForward = coreParams.EnableFastForward 485 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 486 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 487 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 488 val EnableDCacheWPU = coreParams.EnableDCacheWPU 489 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 490 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 491 val asidLen = coreParams.MMUAsidLen 492 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 493 val refillBothTlb = coreParams.refillBothTlb 494 val itlbParams = coreParams.itlbParameters 495 val ldtlbParams = coreParams.ldtlbParameters 496 val sttlbParams = coreParams.sttlbParameters 497 val btlbParams = coreParams.btlbParameters 498 val l2tlbParams = coreParams.l2tlbParameters 499 val NumPerfCounters = coreParams.NumPerfCounters 500 501 val instBytes = if (HasCExtension) 2 else 4 502 val instOffsetBits = log2Ceil(instBytes) 503 504 val icacheParameters = coreParams.icacheParameters 505 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 506 507 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 508 // for constrained LR/SC loop 509 val LRSCCycles = 64 510 // for lr storm 511 val LRSCBackOff = 8 512 513 // cache hierarchy configurations 514 val l1BusDataWidth = 256 515 516 // load violation predict 517 val ResetTimeMax2Pow = 20 //1078576 518 val ResetTimeMin2Pow = 10 //1024 519 // wait table parameters 520 val WaitTableSize = 1024 521 val MemPredPCWidth = log2Up(WaitTableSize) 522 val LWTUse2BitCounter = true 523 // store set parameters 524 val SSITSize = WaitTableSize 525 val LFSTSize = 32 526 val SSIDWidth = log2Up(LFSTSize) 527 val LFSTWidth = 4 528 val StoreSetEnable = true // LWT will be disabled if SS is enabled 529 530 val PCntIncrStep: Int = 6 531 val numPCntHc: Int = 25 532 val numPCntPtw: Int = 19 533 534 val numCSRPCntFrontend = 8 535 val numCSRPCntCtrl = 8 536 val numCSRPCntLsu = 8 537 val numCSRPCntHc = 5 538} 539