Backend: implement speculative busytable supporting fastWakeUp and cancel

ibuffer: fix unhandled instr page fault caused by move elimination (#2279)

Backend, Fusion: enable fused_lui_load

Backend, Fusion: another implementation for instruction fusion case 'lui + addi(w)' without widening imm bits

Rob: support ROB compression (#2192)

For consecutive instructions that do not raise exceptions,
they can share a same rob entry and reduce rob consumption.

Only scalar instructions are supported no

Rob: support ROB compression (#2192)

For consecutive instructions that do not raise exceptions,
they can share a same rob entry and reduce rob consumption.

Only scalar instructions are supported now.

---------

Co-authored-by: fdy <[email protected]>

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vector: fix rename for vector instructions
* add old_pdest connection from vecRat to rename

fix errors in merge master into new-backend

merge master into new-backend

Todo: fix error

params,backend: refactor RegFile parameters

CtrlBlock: implement rename snapshot (#2191)

* CtrlBlock: new ME method for better timing and area

* ctrlblock: implement snapshot recovery

* rename: enlarge distance between snapshots

* sn

CtrlBlock: implement rename snapshot (#2191)

* CtrlBlock: new ME method for better timing and area

* ctrlblock: implement snapshot recovery

* rename: enlarge distance between snapshots

* snapshot: add rename snapshot switch

* CtrlBlock: add snapshotGen API

* snapshot: optimize timing

* snapshot: put snapshot logic in a module

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CtrlBlock: new ME method for better timing and area (#2161)

new move elimination method:

1. get old_pdest from arch-rat when commit;
2. get ready-for-free from comparing old-pdest with arch-rat

CtrlBlock: new ME method for better timing and area (#2161)

new move elimination method:

1. get old_pdest from arch-rat when commit;
2. get ready-for-free from comparing old-pdest with arch-rat after commit;

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difftest: Remove diff_rat and its related ports, when both env.EnableDifftest and env.AlwaysBasicDiff are false.

Decode: merge DecodeUnitComplex to DecodeUnitComp

top-down: align top-down with Gem5 (#2085)

* topdown: add defines of topdown counters enum

* redirect: add redirect type for perf

* top-down: add stallReason IOs

frontend -> ctrlBlock -> de

top-down: align top-down with Gem5 (#2085)

* topdown: add defines of topdown counters enum

* redirect: add redirect type for perf

* top-down: add stallReason IOs

frontend -> ctrlBlock -> decode -> rename -> dispatch

* top-down: add dummy connections

* top-down: update TopdownCounters

* top-down: imp backend analysis and counter dump

* top-down: add HartId in `addSource`

* top-down: broadcast lqIdx of ROB head

* top-down: frontend signal done

* top-down: add memblock topdown interface

* Bump HuanCun: add TopDownMonitor

* top-down: receive and handle reasons in dispatch

* top-down: remove previous top-down code

* TopDown: add MemReqSource enum

* TopDown: extend mshr_latency range

* TopDown: add basic Req Source

TODO: distinguish prefetch

* dcache: distinguish L1DataPrefetch and CPUData

* top-down: comment out debugging perf counters in ibuffer

* TopDown: add path to pass MemReqSource to HuanCun

* TopDown: use simpler logic to count reqSource and update Probe count

* frontend: update topdown counters

* Update HuanCun Topdown for MemReqSource

* top-down: fix load stalls

* top-down: Change the priority of different stall reasons

* top-down: breakdown OtherCoreStall

* sbuffer: fix eviction

* when valid count reaches StoreBufferSize, do eviction

* sbuffer: fix replaceIdx

* If the way selected by the replacement algorithm cannot be written into dcache, its result is not used.

* dcache, ldu: fix vaddr in missqueue

This commit prevents the high bits of the virtual address from being truncated

* fix-ldst_pri-230506

* mainpipe: fix loadsAreComing

* top-down: disable dedup

* top-down: remove old top-down config

* top-down: split lq addr from ls_debug

* top-down: purge previous top-down code

* top-down: add debug_vaddr in LoadQueueReplay

* add source rob_head_other_repay

* remove load_l1_cache_stall_with/wihtou_bank_conflict

* dcache: split CPUData & refill latency

* split CPUData to CPUStoreData & CPULoadData & CPUAtomicData
* monitor refill latency for all type of req

* dcache: fix perfcounter in mq

* io.req.bits.cancel should be applied when counting req.fire

* TopDown: add TopDown for CPL2 in XiangShan

* top-down: add hartid params to L2Cache

* top-down: fix dispatch queue bound

* top-down: no DqStall when robFull

* topdown: buspmu support latency statistic (#2106)

* perf: add buspmu between L2 and L3, support name argument

* bump difftest

* perf: busmonitor supports latency stat

* config: fix cpl2 compatible problem

* bump utility

* bump coupledL2

* bump huancun

* misc: adapt to utility key&field

* config: fix key&field source, remove deprecated argument

* buspmu: remove debug print

* bump coupledl2&huancun

* top-down: fix sq full condition

* top-down: classify "lq full" load bound

* top-down: bump submodules

* bump coupledL2: fix reqSource in data path

* bump coupledL2

---------

Co-authored-by: tastynoob <[email protected]>
Co-authored-by: Guokai Chen <[email protected]>
Co-authored-by: lixin <[email protected]>
Co-authored-by: XiChen <[email protected]>
Co-authored-by: Zhou Yaoyang <[email protected]>
Co-authored-by: Lyn <[email protected]>
Co-authored-by: wakafa <[email protected]>

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rat: add separated ldest read port for vector insts

backend: fix error in uop counter

* Set uopNum at rob's enq instead of using enqCnt to avoid committing before all uop enq.
* There are many uops mapped to the same robIdx. When some of the uops ent

backend: fix error in uop counter

* Set uopNum at rob's enq instead of using enqCnt to avoid committing before all uop enq.
* There are many uops mapped to the same robIdx. When some of the uops enter rob, while others blocked at rename stage for the lack of free regfiles, committing before all uop enq would happen.
* Distinguish std wb status as before

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backend: fix vector rename

vector: fix vector src type

backend: refactor src configs

* calculate number of source reg instead of using immediate number

Merge branch 'dev-vector' into new-backend

backend: refactor vset and add rab support

add vset support

Co-authored-by: zhanglyGit <[email protected]>
Co-authored-by: Xuan Hu <[email protected]>

Merge remote-tracking branch 'upstream/master' into new-backend-merge-master

perf: add some slot util perf counters of id/rn/dp (#2046)

backend: merge v2backend into backend