xref: /XiangShan/Makefile (revision 39c59369af6e7d78fa72e13aae3735f1a6e98f5c) 
1#***************************************************************************************
2# Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3# Copyright (c) 2020-2021 Peng Cheng Laboratory
4#
5# XiangShan is licensed under Mulan PSL v2.
6# You can use this software according to the terms and conditions of the Mulan PSL v2.
7# You may obtain a copy of Mulan PSL v2 at:
8#          http://license.coscl.org.cn/MulanPSL2
9#
10# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13#
14# See the Mulan PSL v2 for more details.
15#***************************************************************************************
16
17TOP = XSTop
18FPGATOP = top.TopMain
19BUILD_DIR = ./build
20TOP_V = $(BUILD_DIR)/$(TOP).v
21SCALA_FILE = $(shell find ./src/main/scala -name '*.scala')
22TEST_FILE = $(shell find ./src/test/scala -name '*.scala')
23MEM_GEN = ./scripts/vlsi_mem_gen
24MEM_GEN_SEP = ./scripts/gen_sep_mem.sh
25
26SIMTOP  = top.SimTop
27IMAGE  ?= temp
28CONFIG ?= DefaultConfig
29NUM_CORES ?= 1
30MFC ?= 0
31
32FPGA_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full
33SIM_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full
34
35# select firrtl compiler
36ifeq ($(MFC),1)
37override FC_ARGS = --mfc
38override FPGA_MEM_ARGS = --infer-rw --firtool-opt -split-verilog --firtool-opt -o --firtool-opt build --firtool-opt -repl-seq-mem --firtool-opt -repl-seq-mem-circuit=$(FPGATOP) --firtool-opt -repl-seq-mem-file=XSTop.v.conf
39override SIM_MEM_ARGS = --infer-rw --firtool-opt -split-verilog --firtool-opt -o --firtool-opt build --firtool-opt -repl-seq-mem --firtool-opt -repl-seq-mem-circuit=$(SIMTOP) --firtool-opt -repl-seq-mem-file=SimTop.v.conf
40endif
41
42
43# co-simulation with DRAMsim3
44ifeq ($(WITH_DRAMSIM3),1)
45ifndef DRAMSIM3_HOME
46$(error DRAMSIM3_HOME is not set)
47endif
48override SIM_ARGS += --with-dramsim3
49endif
50
51# dynamic switch CONSTANTIN
52ifeq ($(WITH_CONSTANTIN),0)
53$(info disable WITH_CONSTANTIN)
54else
55override SIM_ARGS += --with-constantin
56endif
57
58# top-down
59ifeq ($(CONFIG),DefaultConfig)
60ENABLE_TOPDOWN ?= 0
61endif
62ifneq ($(NUM_CORES),1)
63ENABLE_TOPDOWN = 0
64endif
65ifeq ($(ENABLE_TOPDOWN),1)
66override SIM_ARGS += --enable-topdown
67endif
68
69# emu for the release version
70RELEASE_ARGS = --disable-all --remove-assert --fpga-platform
71DEBUG_ARGS   = --enable-difftest
72ifeq ($(RELEASE),1)
73override SIM_ARGS += $(RELEASE_ARGS)
74else
75override SIM_ARGS += $(DEBUG_ARGS)
76endif
77
78TIMELOG = $(BUILD_DIR)/time.log
79TIME_CMD = time -a -o $(TIMELOG)
80
81SED_CMD = sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g'
82
83.DEFAULT_GOAL = verilog
84
85help:
86	mill -i XiangShan.runMain $(FPGATOP) --help
87
88$(TOP_V): $(SCALA_FILE)
89	mkdir -p $(@D)
90	$(TIME_CMD) mill -i XiangShan.runMain $(FPGATOP) -td $(@D)  \
91		--config $(CONFIG)                                        \
92		$(FPGA_MEM_ARGS)                                          \
93		--num-cores $(NUM_CORES)                                  \
94		$(RELEASE_ARGS) $(FC_ARGS)
95ifeq ($(MFC),1)
96	for file in $(BUILD_DIR)/*.sv; do $(SED_CMD) "$${file}"; mv "$${file}" "$${file%.sv}.v"; done
97	mv $(BUILD_DIR)/$(BUILD_DIR)/* $(BUILD_DIR)
98	$(MEM_GEN_SEP) "$(MEM_GEN)" "$(TOP_V).conf" "$(BUILD_DIR)"
99endif
100	$(SED_CMD) $@
101	@git log -n 1 >> .__head__
102	@git diff >> .__diff__
103	@sed -i 's/^/\/\// ' .__head__
104	@sed -i 's/^/\/\//' .__diff__
105	@cat .__head__ .__diff__ $@ > .__out__
106	@mv .__out__ $@
107	@rm .__head__ .__diff__
108
109verilog: $(TOP_V)
110
111SIM_TOP   = SimTop
112SIM_TOP_V = $(BUILD_DIR)/$(SIM_TOP).v
113$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE)
114	mkdir -p $(@D)
115	@echo "\n[mill] Generating Verilog files..." > $(TIMELOG)
116	@date -R | tee -a $(TIMELOG)
117	$(TIME_CMD) mill -i XiangShan.test.runMain $(SIMTOP) -td $(@D)  \
118		--config $(CONFIG)                                            \
119		$(SIM_MEM_ARGS)                                               \
120		--num-cores $(NUM_CORES)                                      \
121		$(SIM_ARGS) $(FC_ARGS) --full-stacktrace
122ifeq ($(MFC),1)
123	for file in $(BUILD_DIR)/*.sv; do $(SED_CMD) "$${file}"; mv "$${file}" "$${file%.sv}.v"; done
124	mv $(BUILD_DIR)/$(BUILD_DIR)/* $(BUILD_DIR)
125	$(MEM_GEN_SEP) "$(MEM_GEN)" "$(SIM_TOP_V).conf" "$(BUILD_DIR)"
126endif
127	$(SED_CMD) $@
128	@git log -n 1 >> .__head__
129	@git diff >> .__diff__
130	@sed -i 's/^/\/\// ' .__head__
131	@sed -i 's/^/\/\//' .__diff__
132	@cat .__head__ .__diff__ $@ > .__out__
133	@mv .__out__ $@
134	@rm .__head__ .__diff__
135	sed -i -e 's/$$fatal/xs_assert(`__LINE__)/g' $(SIM_TOP_V)
136
137sim-verilog: $(SIM_TOP_V)
138
139clean:
140	$(MAKE) -C ./difftest clean
141	rm -rf ./build
142
143init:
144	git submodule update --init
145	cd rocket-chip && git submodule update --init api-config-chipsalliance hardfloat
146
147bump:
148	git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master"
149
150bsp:
151	mill -i mill.bsp.BSP/install
152
153idea:
154	mill -i mill.scalalib.GenIdea/idea
155
156# verilator simulation
157emu:
158	$(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES)
159
160emu-run:
161	$(MAKE) -C ./difftest emu-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES)
162
163# vcs simulation
164simv:
165	$(MAKE) -C ./difftest simv SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES)
166
167include Makefile.test
168
169.PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO)
170