1#*************************************************************************************** 2# Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3# Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4# Copyright (c) 2020-2021 Peng Cheng Laboratory 5# 6# XiangShan is licensed under Mulan PSL v2. 7# You can use this software according to the terms and conditions of the Mulan PSL v2. 8# You may obtain a copy of Mulan PSL v2 at: 9# http://license.coscl.org.cn/MulanPSL2 10# 11# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14# 15# See the Mulan PSL v2 for more details. 16#*************************************************************************************** 17 18BUILD_DIR = ./build 19RTL_DIR = $(BUILD_DIR)/rtl 20 21# if XSTopPrefix is specified in yaml, use it. 22ifneq ($(YAML_CONFIG),) 23HAS_PREFIX_FROM_YAML = $(shell grep 'XSTopPrefix *:' $(YAML_CONFIG)) 24ifneq ($(HAS_PREFIX_FROM_YAML),) 25XSTOP_PREFIX_YAML = $(shell grep 'XSTopPrefix *:' $(YAML_CONFIG) | sed 's/XSTopPrefix *: *//' | tr -d \"\') 26override XSTOP_PREFIX = $(XSTOP_PREFIX_YAML) 27endif 28endif 29 30TOP = $(XSTOP_PREFIX)XSTop 31SIM_TOP = SimTop 32 33FPGATOP = top.TopMain 34SIMTOP = top.SimTop 35 36RTL_SUFFIX ?= sv 37TOP_V = $(RTL_DIR)/$(TOP).$(RTL_SUFFIX) 38SIM_TOP_V = $(RTL_DIR)/$(SIM_TOP).$(RTL_SUFFIX) 39 40SCALA_FILE = $(shell find ./src/main/scala -name '*.scala') 41TEST_FILE = $(shell find ./src/test/scala -name '*.scala') 42 43MEM_GEN = ./scripts/vlsi_mem_gen 44MEM_GEN_SEP = ./scripts/gen_sep_mem.sh 45 46CONFIG ?= DefaultConfig 47NUM_CORES ?= 1 48ISSUE ?= E.b 49CHISEL_TARGET ?= systemverilog 50 51SUPPORT_CHI_ISSUE = B C E.b 52ifeq ($(findstring $(ISSUE), $(SUPPORT_CHI_ISSUE)),) 53$(error "Unsupported CHI issue: $(ISSUE)") 54endif 55 56ifneq ($(shell echo "$(MAKECMDGOALS)" | grep ' '),) 57$(error At most one target can be specified) 58endif 59 60ifeq ($(MAKECMDGOALS),) 61GOALS = verilog 62else 63GOALS = $(MAKECMDGOALS) 64endif 65 66# JVM memory configurations 67JVM_XMX ?= 40G 68JVM_XSS ?= 256m 69 70# mill arguments for build.sc 71MILL_BUILD_ARGS = -Djvm-xmx=$(JVM_XMX) -Djvm-xss=$(JVM_XSS) 72 73# common chisel args 74FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).$(RTL_SUFFIX).conf" 75SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).$(RTL_SUFFIX).conf" 76MFC_ARGS = --dump-fir --target $(CHISEL_TARGET) --split-verilog \ 77 --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing,locationInfoStyle=none" 78 79# prefix of XSTop or XSNoCTop 80ifneq ($(XSTOP_PREFIX),) 81COMMON_EXTRA_ARGS += --xstop-prefix $(XSTOP_PREFIX) 82endif 83 84# IMSIC bus type (AXI, TL or NONE) 85ifneq ($(IMSIC_BUS_TYPE),) 86COMMON_EXTRA_ARGS += --imsic-bus-type $(IMSIC_BUS_TYPE) 87endif 88 89# enable or disable dfx manually 90ifeq ($(DFX),1) 91COMMON_EXTRA_ARGS += --dfx true 92else 93ifeq ($(DFX),0) 94COMMON_EXTRA_ARGS += --dfx false 95endif 96endif 97 98# enable or disable sram ctl maunally 99ifeq ($(SRAM_WITH_CTL),1) 100COMMON_EXTRA_ARGS += --sram-with-ctl 101endif 102 103# enable non-secure access or not 104# CHI requests are secure as default by now 105ifeq ($(ENABLE_NS),1) 106COMMON_EXTRA_ARGS += --enable-ns 107endif 108 109# L2 cache size in KB 110ifneq ($(L2_CACHE_SIZE),) 111COMMON_EXTRA_ARGS += --l2-cache-size $(L2_CACHE_SIZE) 112endif 113 114# L3 cache size in KB 115ifneq ($(L3_CACHE_SIZE),) 116COMMON_EXTRA_ARGS += --l3-cache-size $(L3_CACHE_SIZE) 117endif 118 119# hart id bits 120ifneq ($(HART_ID_BITS),) 121COMMON_EXTRA_ARGS += --hartidbits $(HART_ID_BITS) 122endif 123 124# configuration from yaml file 125ifneq ($(YAML_CONFIG),) 126COMMON_EXTRA_ARGS += --yaml-config $(YAML_CONFIG) 127endif 128 129# public args sumup 130RELEASE_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) 131DEBUG_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) 132override PLDM_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS) 133 134# co-simulation with DRAMsim3 135ifeq ($(WITH_DRAMSIM3),1) 136ifndef DRAMSIM3_HOME 137$(error DRAMSIM3_HOME is not set) 138endif 139override SIM_ARGS += --with-dramsim3 140endif 141 142# run emu with chisel-db 143ifeq ($(WITH_CHISELDB),1) 144override SIM_ARGS += --with-chiseldb 145endif 146 147# run emu with chisel-db 148ifeq ($(WITH_ROLLINGDB),1) 149override SIM_ARGS += --with-rollingdb 150endif 151 152# enable ResetGen 153ifeq ($(WITH_RESETGEN),1) 154override SIM_ARGS += --reset-gen 155endif 156 157# run with disable all perf 158ifeq ($(DISABLE_PERF),1) 159override SIM_ARGS += --disable-perf 160endif 161 162# run with disable all db 163ifeq ($(DISABLE_ALWAYSDB),1) 164override SIM_ARGS += --disable-alwaysdb 165endif 166 167# dynamic switch CONSTANTIN 168ifeq ($(WITH_CONSTANTIN),1) 169override SIM_ARGS += --with-constantin 170endif 171 172# emu for the release version 173RELEASE_ARGS += --fpga-platform --disable-all --remove-assert --reset-gen --firtool-opt --ignore-read-enable-mem 174DEBUG_ARGS += --enable-difftest 175override PLDM_ARGS += --enable-difftest 176ifeq ($(RELEASE),1) 177override SIM_ARGS += $(RELEASE_ARGS) 178else ifeq ($(PLDM),1) 179override SIM_ARGS += $(PLDM_ARGS) 180else 181override SIM_ARGS += $(DEBUG_ARGS) 182endif 183 184# use RELEASE_ARGS for TopMain by default 185ifeq ($(PLDM), 1) 186TOPMAIN_ARGS += $(PLDM_ARGS) 187else 188TOPMAIN_ARGS += $(RELEASE_ARGS) 189endif 190 191TIMELOG = $(BUILD_DIR)/time.log 192TIME_CMD = time -avp -o $(TIMELOG) 193 194ifeq ($(PLDM),1) 195SED_IFNDEF = `ifndef SYNTHESIS // src/main/scala/device/RocketDebugWrapper.scala 196SED_ENDIF = `endif // not def SYNTHESIS 197endif 198 199.DEFAULT_GOAL = verilog 200 201help: 202 mill -i xiangshan.runMain $(FPGATOP) --help 203 204version: 205 mill -i xiangshan.runMain $(FPGATOP) --version 206 207jar: 208 mill -i xiangshan.assembly 209 210test-jar: 211 mill -i xiangshan.test.assembly 212 213comp: 214 mill -i xiangshan.compile 215 mill -i xiangshan.test.compile 216 217$(TOP_V): $(SCALA_FILE) 218 mkdir -p $(@D) 219 $(TIME_CMD) mill -i $(MILL_BUILD_ARGS) xiangshan.runMain $(FPGATOP) \ 220 --target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(FPGA_MEM_ARGS) \ 221 --num-cores $(NUM_CORES) $(TOPMAIN_ARGS) 222ifeq ($(CHISEL_TARGET),systemverilog) 223 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)" 224 @git log -n 1 >> .__head__ 225 @git diff >> .__diff__ 226 @sed -i 's/^/\/\// ' .__head__ 227 @sed -i 's/^/\/\//' .__diff__ 228 @cat .__head__ .__diff__ $@ > .__out__ 229 @mv .__out__ $@ 230 @rm .__head__ .__diff__ 231endif 232 233verilog: $(TOP_V) 234 235$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE) 236 mkdir -p $(@D) 237 @echo -e "\n[mill] Generating Verilog files..." > $(TIMELOG) 238 @date -R | tee -a $(TIMELOG) 239 $(TIME_CMD) mill -i $(MILL_BUILD_ARGS) xiangshan.test.runMain $(SIMTOP) \ 240 --target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(SIM_MEM_ARGS) \ 241 --num-cores $(NUM_CORES) $(SIM_ARGS) --full-stacktrace 242ifeq ($(CHISEL_TARGET),systemverilog) 243 $(MEM_GEN_SEP) "$(MEM_GEN)" "[email protected]" "$(@D)" 244 @git log -n 1 >> .__head__ 245 @git diff >> .__diff__ 246 @sed -i 's/^/\/\// ' .__head__ 247 @sed -i 's/^/\/\//' .__diff__ 248 @cat .__head__ .__diff__ $@ > .__out__ 249 @mv .__out__ $@ 250 @rm .__head__ .__diff__ 251ifeq ($(PLDM),1) 252 sed -i -e 's/$$fatal/$$finish/g' $(RTL_DIR)/*.$(RTL_SUFFIX) 253 sed -i -e '/sed/! { \|$(SED_IFNDEF)|, \|$(SED_ENDIF)| { \|$(SED_IFNDEF)|d; \|$(SED_ENDIF)|d; } }' $(RTL_DIR)/*.$(RTL_SUFFIX) 254else 255ifeq ($(ENABLE_XPROP),1) 256 sed -i -e "s/\$$fatal/assert(1\'b0)/g" $(RTL_DIR)/*.$(RTL_SUFFIX) 257else 258 sed -i -e 's/$$fatal/xs_assert_v2(`__FILE__, `__LINE__)/g' $(RTL_DIR)/*.$(RTL_SUFFIX) 259endif 260endif 261 sed -i -e "s/\$$error(/\$$fwrite(32\'h80000002, /g" $(RTL_DIR)/*.$(RTL_SUFFIX) 262endif 263 264sim-verilog: $(SIM_TOP_V) 265 266clean: 267 $(MAKE) -C ./difftest clean 268 rm -rf $(BUILD_DIR) 269 270init: 271 git submodule update --init 272 cd rocket-chip && git submodule update --init cde hardfloat 273 cd openLLC && git submodule update --init openNCB 274 275bump: 276 git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master" 277 278bsp: 279 mill -i mill.bsp.BSP/install 280 281idea: 282 mill -i mill.idea.GenIdea/idea 283 284check-format: 285 mill xiangshan.checkFormat 286 287reformat: 288 mill xiangshan.reformat 289 290# verilator simulation 291emu: sim-verilog 292 $(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 293 294emu-run: emu 295 $(MAKE) -C ./difftest emu-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 296 297# vcs simulation 298simv: sim-verilog 299 $(MAKE) -C ./difftest simv SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 300 301simv-run: 302 $(MAKE) -C ./difftest simv-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 303 304# palladium simulation 305pldm-build: sim-verilog 306 $(MAKE) -C ./difftest pldm-build SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 307 308pldm-run: 309 $(MAKE) -C ./difftest pldm-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 310 311pldm-debug: 312 $(MAKE) -C ./difftest pldm-debug SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX) 313 314include Makefile.test 315 316include src/main/scala/device/standalone/standalone_device.mk 317 318.PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO) 319