1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.rename 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utility._ 23import utils._ 24import xiangshan._ 25import xiangshan.backend.Bundles.{DecodedInst, DynInst} 26import xiangshan.backend.decode.{FusionDecodeInfo, ImmUnion, Imm_I, Imm_LUI_LOAD, Imm_U} 27import xiangshan.backend.fu.FuType 28import xiangshan.backend.rename.freelist._ 29import xiangshan.backend.rob.RobPtr 30import xiangshan.mem.mdp._ 31 32class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper with HasPerfEvents { 33 34 // params alias 35 private val numRegSrc = backendParams.numRegSrc 36 private val numVecRegSrc = backendParams.numVecRegSrc 37 private val numVecRatPorts = numVecRegSrc + 1 // +1 dst 38 39 println(s"[Rename] numRegSrc: $numRegSrc") 40 41 val io = IO(new Bundle() { 42 val redirect = Flipped(ValidIO(new Redirect)) 43 val robCommits = Input(new RobCommitIO) 44 // from decode 45 val in = Vec(RenameWidth, Flipped(DecoupledIO(new DecodedInst))) 46 val fusionInfo = Vec(DecodeWidth - 1, Flipped(new FusionDecodeInfo)) 47 // ssit read result 48 val ssit = Flipped(Vec(RenameWidth, Output(new SSITEntry))) 49 // waittable read result 50 val waittable = Flipped(Vec(RenameWidth, Output(Bool()))) 51 // to rename table 52 val intReadPorts = Vec(RenameWidth, Vec(3, Input(UInt(PhyRegIdxWidth.W)))) 53 val fpReadPorts = Vec(RenameWidth, Vec(4, Input(UInt(PhyRegIdxWidth.W)))) 54 val vecReadPorts = Vec(RenameWidth, Vec(numVecRatPorts, Input(UInt(PhyRegIdxWidth.W)))) 55 val intRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 56 val fpRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 57 val vecRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 58 // from rename table 59 val int_old_pdest = Vec(CommitWidth, Input(UInt(PhyRegIdxWidth.W))) 60 val fp_old_pdest = Vec(CommitWidth, Input(UInt(PhyRegIdxWidth.W))) 61 val vec_old_pdest = Vec(CommitWidth, Input(UInt(PhyRegIdxWidth.W))) 62 val int_need_free = Vec(CommitWidth, Input(Bool())) 63 // to dispatch1 64 val out = Vec(RenameWidth, DecoupledIO(new DynInst)) 65 // for snapshots 66 val snpt = Input(new SnapshotPort) 67 // debug arch ports 68 val debug_int_rat = Vec(32, Input(UInt(PhyRegIdxWidth.W))) 69 val debug_vconfig_rat = Input(UInt(PhyRegIdxWidth.W)) 70 val debug_fp_rat = Vec(32, Input(UInt(PhyRegIdxWidth.W))) 71 val debug_vec_rat = Vec(32, Input(UInt(PhyRegIdxWidth.W))) 72 // perf only 73 val stallReason = new Bundle { 74 val in = Flipped(new StallReasonIO(RenameWidth)) 75 val out = new StallReasonIO(RenameWidth) 76 } 77 }) 78 79 val compressUnit = Module(new CompressUnit()) 80 // create free list and rat 81 val intFreeList = Module(new MEFreeList(IntPhyRegs)) 82 val fpFreeList = Module(new StdFreeList(VfPhyRegs - FpLogicRegs - VecLogicRegs)) 83 84 intFreeList.io.commit <> io.robCommits 85 intFreeList.io.debug_rat <> io.debug_int_rat 86 fpFreeList.io.commit <> io.robCommits 87 fpFreeList.io.debug_rat <> io.debug_fp_rat 88 89 // decide if given instruction needs allocating a new physical register (CfCtrl: from decode; RobCommitInfo: from rob) 90 // fp and vec share `fpFreeList` 91 def needDestReg[T <: DecodedInst](reg_t: RegType, x: T): Bool = reg_t match { 92 case Reg_I => x.rfWen && x.ldest =/= 0.U 93 case Reg_F => x.fpWen 94 case Reg_V => x.vecWen 95 } 96 def needDestRegCommit[T <: RobCommitInfo](reg_t: RegType, x: T): Bool = { 97 reg_t match { 98 case Reg_I => x.rfWen 99 case Reg_F => x.fpWen 100 case Reg_V => x.vecWen 101 } 102 } 103 def needDestRegWalk[T <: RobCommitInfo](reg_t: RegType, x: T): Bool = { 104 reg_t match { 105 case Reg_I => x.rfWen && x.ldest =/= 0.U 106 case Reg_F => x.fpWen 107 case Reg_V => x.vecWen 108 } 109 } 110 111 // connect [redirect + walk] ports for __float point__ & __integer__ free list 112 Seq(fpFreeList, intFreeList).foreach { case fl => 113 fl.io.redirect := io.redirect.valid 114 fl.io.walk := io.robCommits.isWalk 115 } 116 // only when both fp and int free list and dispatch1 has enough space can we do allocation 117 // when isWalk, freelist can definitely allocate 118 intFreeList.io.doAllocate := fpFreeList.io.canAllocate && io.out(0).ready || io.robCommits.isWalk 119 fpFreeList.io.doAllocate := intFreeList.io.canAllocate && io.out(0).ready || io.robCommits.isWalk 120 121 // dispatch1 ready ++ float point free list ready ++ int free list ready ++ not walk 122 val canOut = io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk 123 124 compressUnit.io.in.zip(io.in).foreach{ case(sink, source) => 125 sink.valid := source.valid 126 sink.bits := source.bits 127 } 128 val needRobFlags = compressUnit.io.out.needRobFlags 129 val instrSizesVec = compressUnit.io.out.instrSizes 130 val compressMasksVec = compressUnit.io.out.masks 131 132 // speculatively assign the instruction with an robIdx 133 val validCount = PopCount(io.in.zip(needRobFlags).map{ case(in, needRobFlag) => in.valid && in.bits.lastUop && needRobFlag}) // number of instructions waiting to enter rob (from decode) 134 val robIdxHead = RegInit(0.U.asTypeOf(new RobPtr)) 135 val lastCycleMisprediction = RegNext(io.redirect.valid && !io.redirect.bits.flushItself()) 136 val robIdxHeadNext = Mux(io.redirect.valid, io.redirect.bits.robIdx, // redirect: move ptr to given rob index 137 Mux(lastCycleMisprediction, robIdxHead + 1.U, // mis-predict: not flush robIdx itself 138 Mux(canOut, robIdxHead + validCount, // instructions successfully entered next stage: increase robIdx 139 /* default */ robIdxHead))) // no instructions passed by this cycle: stick to old value 140 robIdxHead := robIdxHeadNext 141 142 /** 143 * Rename: allocate free physical register and update rename table 144 */ 145 val uops = Wire(Vec(RenameWidth, new DynInst)) 146 uops.foreach( uop => { 147 uop.srcState := DontCare 148 uop.debugInfo := DontCare 149 uop.lqIdx := DontCare 150 uop.sqIdx := DontCare 151 uop.waitForRobIdx := DontCare 152 uop.singleStep := DontCare 153 uop.snapshot := DontCare 154 }) 155 156 require(RenameWidth >= CommitWidth) 157 val needVecDest = Wire(Vec(RenameWidth, Bool())) 158 val needFpDest = Wire(Vec(RenameWidth, Bool())) 159 val needIntDest = Wire(Vec(RenameWidth, Bool())) 160 val hasValid = Cat(io.in.map(_.valid)).orR 161 162 val isMove = io.in.map(_.bits.isMove) 163 164 val walkNeedIntDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 165 val walkNeedFpDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 166 val walkNeedVecDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 167 val walkIsMove = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 168 169 val intSpecWen = Wire(Vec(RenameWidth, Bool())) 170 val fpSpecWen = Wire(Vec(RenameWidth, Bool())) 171 val vecSpecWen = Wire(Vec(RenameWidth, Bool())) 172 173 val walkIntSpecWen = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 174 175 val walkPdest = Wire(Vec(RenameWidth, UInt(PhyRegIdxWidth.W))) 176 177 // uop calculation 178 for (i <- 0 until RenameWidth) { 179 for ((name, data) <- uops(i).elements) { 180 if (io.in(i).bits.elements.contains(name)) { 181 data := io.in(i).bits.elements(name) 182 } 183 } 184 185 // update cf according to ssit result 186 uops(i).storeSetHit := io.ssit(i).valid 187 uops(i).loadWaitStrict := io.ssit(i).strict && io.ssit(i).valid 188 uops(i).ssid := io.ssit(i).ssid 189 190 // update cf according to waittable result 191 uops(i).loadWaitBit := io.waittable(i) 192 193 uops(i).replayInst := false.B // set by IQ or MemQ 194 // alloc a new phy reg, fp and vec share the `fpFreeList` 195 needVecDest (i) := io.in(i).valid && needDestReg(Reg_V, io.in(i).bits) 196 needFpDest (i) := io.in(i).valid && needDestReg(Reg_F, io.in(i).bits) 197 needIntDest (i) := io.in(i).valid && needDestReg(Reg_I, io.in(i).bits) 198 if (i < CommitWidth) { 199 walkNeedIntDest(i) := io.robCommits.walkValid(i) && needDestRegWalk(Reg_I, io.robCommits.info(i)) 200 walkNeedFpDest(i) := io.robCommits.walkValid(i) && needDestRegWalk(Reg_F, io.robCommits.info(i)) 201 walkNeedVecDest(i) := io.robCommits.walkValid(i) && needDestRegWalk(Reg_V, io.robCommits.info(i)) 202 walkIsMove(i) := io.robCommits.info(i).isMove 203 } 204 fpFreeList.io.allocateReq(i) := needFpDest(i) || needVecDest(i) 205 fpFreeList.io.walkReq(i) := walkNeedFpDest(i) || walkNeedVecDest(i) 206 intFreeList.io.allocateReq(i) := needIntDest(i) && !isMove(i) 207 intFreeList.io.walkReq(i) := walkNeedIntDest(i) && !walkIsMove(i) 208 209 // no valid instruction from decode stage || all resources (dispatch1 + both free lists) ready 210 io.in(i).ready := !hasValid || canOut 211 212 uops(i).robIdx := robIdxHead + PopCount(io.in.zip(needRobFlags).take(i).map{ case(in, needRobFlag) => in.valid && in.bits.lastUop && needRobFlag}) 213 uops(i).instrSize := instrSizesVec(i) 214 when(isMove(i)) { 215 uops(i).numUops := 0.U 216 } 217 if (i > 0) { 218 when(!needRobFlags(i - 1)) { 219 uops(i).firstUop := false.B 220 uops(i).ftqPtr := uops(i - 1).ftqPtr 221 uops(i).ftqOffset := uops(i - 1).ftqOffset 222 uops(i).numUops := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 223 } 224 } 225 when(!needRobFlags(i)) { 226 uops(i).lastUop := false.B 227 uops(i).numUops := instrSizesVec(i) - PopCount(compressMasksVec(i) & Cat(isMove.reverse)) 228 } 229 230 uops(i).psrc(0) := Mux1H(uops(i).srcType(0), Seq(io.intReadPorts(i)(0), io.fpReadPorts(i)(0), io.vecReadPorts(i)(0))) 231 uops(i).psrc(1) := Mux1H(uops(i).srcType(1), Seq(io.intReadPorts(i)(1), io.fpReadPorts(i)(1), io.vecReadPorts(i)(1))) 232 uops(i).psrc(2) := Mux1H(uops(i).srcType(2)(2, 1), Seq(io.fpReadPorts(i)(2), io.vecReadPorts(i)(2))) 233 uops(i).psrc(3) := io.vecReadPorts(i)(3) 234 uops(i).psrc(4) := io.vecReadPorts(i)(4) // Todo: vl read port 235 236 // int psrc2 should be bypassed from next instruction if it is fused 237 if (i < RenameWidth - 1) { 238 when (io.fusionInfo(i).rs2FromRs2 || io.fusionInfo(i).rs2FromRs1) { 239 uops(i).psrc(1) := Mux(io.fusionInfo(i).rs2FromRs2, io.intReadPorts(i + 1)(1), io.intReadPorts(i + 1)(0)) 240 }.elsewhen(io.fusionInfo(i).rs2FromZero) { 241 uops(i).psrc(1) := 0.U 242 } 243 } 244 uops(i).psrc(2) := io.fpReadPorts(i)(2) 245 // Todo 246 // uops(i).old_pdest := Mux(uops(i).ctrl.rfWen, io.intReadPorts(i).last, io.fpReadPorts(i).last) 247 uops(i).eliminatedMove := isMove(i) 248 249 // update pdest 250 uops(i).pdest := MuxCase(0.U, Seq( 251 needIntDest(i) -> intFreeList.io.allocatePhyReg(i), 252 (needFpDest(i) || needVecDest(i)) -> fpFreeList.io.allocatePhyReg(i), 253 )) 254 255 // Assign performance counters 256 uops(i).debugInfo.renameTime := GTimer() 257 258 io.out(i).valid := io.in(i).valid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && !io.robCommits.isWalk 259 io.out(i).bits := uops(i) 260 // Todo: move these shit in decode stage 261 // dirty code for fence. The lsrc is passed by imm. 262 when (io.out(i).bits.fuType === FuType.fence.U) { 263 io.out(i).bits.imm := Cat(io.in(i).bits.lsrc(1), io.in(i).bits.lsrc(0)) 264 } 265 266 // dirty code for SoftPrefetch (prefetch.r/prefetch.w) 267// when (io.in(i).bits.isSoftPrefetch) { 268// io.out(i).bits.fuType := FuType.ldu.U 269// io.out(i).bits.fuOpType := Mux(io.in(i).bits.lsrc(1) === 1.U, LSUOpType.prefetch_r, LSUOpType.prefetch_w) 270// io.out(i).bits.selImm := SelImm.IMM_S 271// io.out(i).bits.imm := Cat(io.in(i).bits.imm(io.in(i).bits.imm.getWidth - 1, 5), 0.U(5.W)) 272// } 273 274 // dirty code for lui+addi(w) fusion 275 if (i < RenameWidth - 1) { 276 val fused_lui32 = io.in(i).bits.selImm === SelImm.IMM_LUI32 && io.in(i).bits.fuType === FuType.alu.U 277 when (fused_lui32) { 278 val lui_imm = io.in(i).bits.imm(19, 0) 279 val add_imm = io.in(i + 1).bits.imm(11, 0) 280 io.out(i).bits.imm := Imm_LUI_LOAD().immFromLuiLoad(lui_imm, add_imm) 281 val lsrcWidth = uops(i).lsrc.head.getWidth 282 val lui_imm_in_imm = ImmUnion.maxLen - Imm_I().len 283 val left_lui_imm = Imm_U().len - lui_imm_in_imm 284 require(2 * lsrcWidth >= left_lui_imm, "cannot fused lui and addi(w) with lsrc") 285 io.out(i).bits.lsrc(0) := lui_imm(lui_imm_in_imm + lsrcWidth - 1, lui_imm_in_imm) 286 io.out(i).bits.lsrc(1) := lui_imm(lui_imm.getWidth - 1, lui_imm_in_imm + lsrcWidth) 287 } 288 } 289 290 // write speculative rename table 291 // we update rat later inside commit code 292 intSpecWen(i) := needIntDest(i) && intFreeList.io.canAllocate && intFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 293 fpSpecWen(i) := needFpDest(i) && fpFreeList.io.canAllocate && fpFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 294 vecSpecWen(i) := needVecDest(i) && fpFreeList.io.canAllocate && fpFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 295 296 if (i < CommitWidth) { 297 walkIntSpecWen(i) := walkNeedIntDest(i) && !io.redirect.valid 298 walkPdest(i) := io.robCommits.info(i).pdest 299 } else { 300 walkPdest(i) := io.out(i).bits.pdest 301 } 302 } 303 304 /** 305 * How to set psrc: 306 * - bypass the pdest to psrc if previous instructions write to the same ldest as lsrc 307 * - default: psrc from RAT 308 * How to set pdest: 309 * - Mux(isMove, psrc, pdest_from_freelist). 310 * 311 * The critical path of rename lies here: 312 * When move elimination is enabled, we need to update the rat with psrc. 313 * However, psrc maybe comes from previous instructions' pdest, which comes from freelist. 314 * 315 * If we expand these logic for pdest(N): 316 * pdest(N) = Mux(isMove(N), psrc(N), freelist_out(N)) 317 * = Mux(isMove(N), Mux(bypass(N, N - 1), pdest(N - 1), 318 * Mux(bypass(N, N - 2), pdest(N - 2), 319 * ... 320 * Mux(bypass(N, 0), pdest(0), 321 * rat_out(N))...)), 322 * freelist_out(N)) 323 */ 324 // a simple functional model for now 325 io.out(0).bits.pdest := Mux(isMove(0), uops(0).psrc.head, uops(0).pdest) 326 327 // psrc(n) + pdest(1) 328 val bypassCond: Vec[MixedVec[UInt]] = Wire(Vec(numRegSrc + 1, MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))))) 329 require(io.in(0).bits.srcType.size == io.in(0).bits.numSrc) 330 private val pdestLoc = io.in.head.bits.srcType.size // 2 vector src: v0, vl&vtype 331 println(s"[Rename] idx of pdest in bypassCond $pdestLoc") 332 for (i <- 1 until RenameWidth) { 333 val vecCond = io.in(i).bits.srcType.map(_ === SrcType.vp) :+ needVecDest(i) 334 val fpCond = io.in(i).bits.srcType.map(_ === SrcType.fp) :+ needFpDest(i) 335 val intCond = io.in(i).bits.srcType.map(_ === SrcType.xp) :+ needIntDest(i) 336 val target = io.in(i).bits.lsrc :+ io.in(i).bits.ldest 337 for (((((cond1, cond2), cond3), t), j) <- vecCond.zip(fpCond).zip(intCond).zip(target).zipWithIndex) { 338 val destToSrc = io.in.take(i).zipWithIndex.map { case (in, j) => 339 val indexMatch = in.bits.ldest === t 340 val writeMatch = cond3 && needIntDest(j) || cond2 && needFpDest(j) || cond1 && needVecDest(j) 341 indexMatch && writeMatch 342 } 343 bypassCond(j)(i - 1) := VecInit(destToSrc).asUInt 344 } 345 io.out(i).bits.psrc(0) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(0)(i-1).asBools).foldLeft(uops(i).psrc(0)) { 346 (z, next) => Mux(next._2, next._1, z) 347 } 348 io.out(i).bits.psrc(1) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(1)(i-1).asBools).foldLeft(uops(i).psrc(1)) { 349 (z, next) => Mux(next._2, next._1, z) 350 } 351 io.out(i).bits.psrc(2) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(2)(i-1).asBools).foldLeft(uops(i).psrc(2)) { 352 (z, next) => Mux(next._2, next._1, z) 353 } 354 io.out(i).bits.psrc(3) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(3)(i-1).asBools).foldLeft(uops(i).psrc(3)) { 355 (z, next) => Mux(next._2, next._1, z) 356 } 357 io.out(i).bits.psrc(4) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(4)(i-1).asBools).foldLeft(uops(i).psrc(4)) { 358 (z, next) => Mux(next._2, next._1, z) 359 } 360 io.out(i).bits.pdest := Mux(isMove(i), io.out(i).bits.psrc(0), uops(i).pdest) 361 362 // Todo: better implementation for fields reuse 363 // For fused-lui-load, load.src(0) is replaced by the imm. 364 val last_is_lui = io.in(i - 1).bits.selImm === SelImm.IMM_U && io.in(i - 1).bits.srcType(0) =/= SrcType.pc 365 val this_is_load = io.in(i).bits.fuType === FuType.ldu.U 366 val lui_to_load = io.in(i - 1).valid && io.in(i - 1).bits.ldest === io.in(i).bits.lsrc(0) 367 val fused_lui_load = last_is_lui && this_is_load && lui_to_load && false.B // Todo: enable it 368 when (fused_lui_load) { 369 // The first LOAD operand (base address) is replaced by LUI-imm and stored in {psrc, imm} 370 val lui_imm = io.in(i - 1).bits.imm(19, 0) 371 val ld_imm = io.in(i).bits.imm 372 io.out(i).bits.srcType(0) := SrcType.imm 373 io.out(i).bits.imm := Imm_LUI_LOAD().immFromLuiLoad(lui_imm, ld_imm) 374 val psrcWidth = uops(i).psrc.head.getWidth 375 val lui_imm_in_imm = 20/*Todo: uops(i).imm.getWidth*/ - Imm_I().len 376 val left_lui_imm = Imm_U().len - lui_imm_in_imm 377 require(2 * psrcWidth >= left_lui_imm, "cannot fused lui and load with psrc") 378 io.out(i).bits.psrc(0) := lui_imm(lui_imm_in_imm + psrcWidth - 1, lui_imm_in_imm) 379 io.out(i).bits.psrc(1) := lui_imm(lui_imm.getWidth - 1, lui_imm_in_imm + psrcWidth) 380 } 381 382 } 383 384 val hasCFI = VecInit(io.in.map(in => (!in.bits.preDecodeInfo.notCFI || FuType.isJump(in.bits.fuType)) && in.fire)).asUInt.orR 385 val snapshotCtr = RegInit((4 * CommitWidth).U) 386 val allowSnpt = if (EnableRenameSnapshot) !snapshotCtr.orR else false.B 387 io.out.head.bits.snapshot := hasCFI && allowSnpt 388 when(io.out.head.fire && io.out.head.bits.snapshot) { 389 snapshotCtr := (4 * CommitWidth).U - PopCount(io.out.map(_.fire)) 390 }.elsewhen(io.out.head.fire) { 391 snapshotCtr := Mux(snapshotCtr < PopCount(io.out.map(_.fire)), 0.U, snapshotCtr - PopCount(io.out.map(_.fire))) 392 } 393 394 intFreeList.io.snpt := io.snpt 395 fpFreeList.io.snpt := io.snpt 396 intFreeList.io.snpt.snptEnq := io.out.head.fire && io.out.head.bits.snapshot 397 fpFreeList.io.snpt.snptEnq := io.out.head.fire && io.out.head.bits.snapshot 398 399 /** 400 * Instructions commit: update freelist and rename table 401 */ 402 for (i <- 0 until CommitWidth) { 403 val commitValid = io.robCommits.isCommit && io.robCommits.commitValid(i) 404 val walkValid = io.robCommits.isWalk && io.robCommits.walkValid(i) 405 406 // I. RAT Update 407 // When redirect happens (mis-prediction), don't update the rename table 408 io.intRenamePorts(i).wen := intSpecWen(i) 409 io.intRenamePorts(i).addr := uops(i).ldest 410 io.intRenamePorts(i).data := io.out(i).bits.pdest 411 412 io.fpRenamePorts(i).wen := fpSpecWen(i) 413 io.fpRenamePorts(i).addr := uops(i).ldest 414 io.fpRenamePorts(i).data := fpFreeList.io.allocatePhyReg(i) 415 416 io.vecRenamePorts(i).wen := vecSpecWen(i) 417 io.vecRenamePorts(i).addr := uops(i).ldest 418 io.vecRenamePorts(i).data := fpFreeList.io.allocatePhyReg(i) 419 420 // II. Free List Update 421 intFreeList.io.freeReq(i) := io.int_need_free(i) 422 intFreeList.io.freePhyReg(i) := RegNext(io.int_old_pdest(i)) 423 fpFreeList.io.freeReq(i) := RegNext(commitValid && (needDestRegCommit(Reg_F, io.robCommits.info(i)) || needDestRegCommit(Reg_V, io.robCommits.info(i)))) 424 fpFreeList.io.freePhyReg(i) := Mux(RegNext(needDestRegCommit(Reg_F, io.robCommits.info(i))), io.fp_old_pdest(i), io.vec_old_pdest(i)) 425 } 426 427 /* 428 Debug and performance counters 429 */ 430 def printRenameInfo(in: DecoupledIO[DecodedInst], out: DecoupledIO[DynInst]) = { 431 XSInfo(out.fire, p"pc:${Hexadecimal(in.bits.pc)} in(${in.valid},${in.ready}) " + 432 p"lsrc(0):${in.bits.lsrc(0)} -> psrc(0):${out.bits.psrc(0)} " + 433 p"lsrc(1):${in.bits.lsrc(1)} -> psrc(1):${out.bits.psrc(1)} " + 434 p"lsrc(2):${in.bits.lsrc(2)} -> psrc(2):${out.bits.psrc(2)} " + 435 p"ldest:${in.bits.ldest} -> pdest:${out.bits.pdest}\n" 436 ) 437 } 438 439 for ((x,y) <- io.in.zip(io.out)) { 440 printRenameInfo(x, y) 441 } 442 443 val debugRedirect = RegEnable(io.redirect.bits, io.redirect.valid) 444 // bad speculation 445 val recStall = io.redirect.valid || io.robCommits.isWalk 446 val ctrlRecStall = Mux(io.redirect.valid, io.redirect.bits.debugIsCtrl, io.robCommits.isWalk && debugRedirect.debugIsCtrl) 447 val mvioRecStall = Mux(io.redirect.valid, io.redirect.bits.debugIsMemVio, io.robCommits.isWalk && debugRedirect.debugIsMemVio) 448 val otherRecStall = recStall && !(ctrlRecStall || mvioRecStall) 449 XSPerfAccumulate("recovery_stall", recStall) 450 XSPerfAccumulate("control_recovery_stall", ctrlRecStall) 451 XSPerfAccumulate("mem_violation_recovery_stall", mvioRecStall) 452 XSPerfAccumulate("other_recovery_stall", otherRecStall) 453 // freelist stall 454 val notRecStall = !io.out.head.valid && !recStall 455 val intFlStall = notRecStall && hasValid && !intFreeList.io.canAllocate 456 val fpFlStall = notRecStall && hasValid && !fpFreeList.io.canAllocate 457 // other stall 458 val otherStall = notRecStall && !intFlStall && !fpFlStall 459 460 io.stallReason.in.backReason.valid := io.stallReason.out.backReason.valid || !io.in.head.ready 461 io.stallReason.in.backReason.bits := Mux(io.stallReason.out.backReason.valid, io.stallReason.out.backReason.bits, 462 MuxCase(TopDownCounters.OtherCoreStall.id.U, Seq( 463 ctrlRecStall -> TopDownCounters.ControlRecoveryStall.id.U, 464 mvioRecStall -> TopDownCounters.MemVioRecoveryStall.id.U, 465 otherRecStall -> TopDownCounters.OtherRecoveryStall.id.U, 466 intFlStall -> TopDownCounters.IntFlStall.id.U, 467 fpFlStall -> TopDownCounters.FpFlStall.id.U 468 ) 469 )) 470 io.stallReason.out.reason.zip(io.stallReason.in.reason).zip(io.in.map(_.valid)).foreach { case ((out, in), valid) => 471 out := Mux(io.stallReason.in.backReason.valid, 472 io.stallReason.in.backReason.bits, 473 Mux(valid, TopDownCounters.NoStall.id.U, in)) 474 } 475 476 XSDebug(io.robCommits.isWalk, p"Walk Recovery Enabled\n") 477 XSDebug(io.robCommits.isWalk, p"validVec:${Binary(io.robCommits.walkValid.asUInt)}\n") 478 for (i <- 0 until CommitWidth) { 479 val info = io.robCommits.info(i) 480 XSDebug(io.robCommits.isWalk && io.robCommits.walkValid(i), p"[#$i walk info] pc:${Hexadecimal(info.pc)} " + 481 p"ldest:${info.ldest} rfWen:${info.rfWen} fpWen:${info.fpWen} vecWen:${info.vecWen}") 482 } 483 484 XSDebug(p"inValidVec: ${Binary(Cat(io.in.map(_.valid)))}\n") 485 486 XSPerfAccumulate("in", Mux(RegNext(io.in(0).ready), PopCount(io.in.map(_.valid)), 0.U)) 487 XSPerfAccumulate("utilization", PopCount(io.in.map(_.valid))) 488 XSPerfAccumulate("waitInstr", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready))) 489 XSPerfAccumulate("stall_cycle_dispatch", hasValid && !io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk) 490 XSPerfAccumulate("stall_cycle_fp", hasValid && io.out(0).ready && !fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk) 491 XSPerfAccumulate("stall_cycle_int", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && !intFreeList.io.canAllocate && !io.robCommits.isWalk) 492 XSPerfAccumulate("stall_cycle_walk", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && io.robCommits.isWalk) 493 494 XSPerfHistogram("slots_fire", PopCount(io.out.map(_.fire)), true.B, 0, RenameWidth+1, 1) 495 // Explaination: when out(0) not fire, PopCount(valid) is not meaningfull 496 XSPerfHistogram("slots_valid_pure", PopCount(io.in.map(_.valid)), io.out(0).fire, 0, RenameWidth+1, 1) 497 XSPerfHistogram("slots_valid_rough", PopCount(io.in.map(_.valid)), true.B, 0, RenameWidth+1, 1) 498 499 XSPerfAccumulate("move_instr_count", PopCount(io.out.map(out => out.fire && out.bits.isMove))) 500 val is_fused_lui_load = io.out.map(o => o.fire && o.bits.fuType === FuType.ldu.U && o.bits.srcType(0) === SrcType.imm) 501 XSPerfAccumulate("fused_lui_load_instr_count", PopCount(is_fused_lui_load)) 502 503 504 val renamePerf = Seq( 505 ("rename_in ", PopCount(io.in.map(_.valid & io.in(0).ready )) ), 506 ("rename_waitinstr ", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready)) ), 507 ("rename_stall_cycle_dispatch", hasValid && !io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk), 508 ("rename_stall_cycle_fp ", hasValid && io.out(0).ready && !fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk), 509 ("rename_stall_cycle_int ", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && !intFreeList.io.canAllocate && !io.robCommits.isWalk), 510 ("rename_stall_cycle_walk ", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && io.robCommits.isWalk) 511 ) 512 val intFlPerf = intFreeList.getPerfEvents 513 val fpFlPerf = fpFreeList.getPerfEvents 514 val perfEvents = renamePerf ++ intFlPerf ++ fpFlPerf 515 generatePerfEvent() 516} 517