History log of /XiangShan/src/main/scala/xiangshan/backend/rename/ (Results 1 – 25 of 313)
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51ad03b021-Apr-2025 Zhaoyang You <[email protected]>

fix(rename): fix Csrr format (#4605)


/XiangShan/.github/ISSUE_TEMPLATE/1-bug_report.yml
/XiangShan/.github/ISSUE_TEMPLATE/3-problem.yaml
/XiangShan/.github/workflows/perf.yml
/XiangShan/.gitmodules
/XiangShan/ChiselAIA
/XiangShan/Makefile
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/huancun
/XiangShan/ready-to-run
/XiangShan/scalastyle-config.xml
/XiangShan/scalastyle-test-config.xml
/XiangShan/src/main/resources/config/Default.yml
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/top/YamlParser.scala
/XiangShan/src/main/scala/utils/LowPowerState.scala
/XiangShan/src/main/scala/utils/PowerSwitchBuffer.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/XSTileWrap.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPMP.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/PMAEntryModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/PMPEntryModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapHandleModule.scala
Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/ExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TlbPrefetch.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/WrBypass.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/mem/Bundles.scala
/XiangShan/src/main/scala/xiangshan/mem/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
/XiangShan/utility
1592abd108-Apr-2025 Yan Xu <[email protected]>

feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument

feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument
2. Run with "--dump-db --dump-select-db lifetime", then get the database
3. Instruction lifetime visualize run "python3 scripts/perfcct.py
"the-db-file-path" -p 1 -v | less"
4. Analysis script now is in XS-GEM5 repo, see
https://github.com/OpenXiangShan/GEM5/blob/xs-dev/util/ClockAnalysis.py

How it works:
1. Allocate one unique tag "seqNum" like GEM5 for each instruction at
fetch stage
2. Passing the "seqNum" in each pipeline
3. Recording perf data through the DPIC interface

show more ...


/XiangShan/.github/CODEOWNERS
/XiangShan/.github/workflows/emu.yml
/XiangShan/.github/workflows/nightly.yml
/XiangShan/.github/workflows/perf.yml
/XiangShan/ChiselAIA
/XiangShan/Makefile
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/ready-to-run
/XiangShan/scalastyle-config.xml
/XiangShan/scripts/constantHelper.py
/XiangShan/scripts/perfcct.py
/XiangShan/scripts/requirements.txt
/XiangShan/scripts/rolling/.gitignore
/XiangShan/scripts/rolling/rollingplot.py
/XiangShan/scripts/top-down/configs.py
/XiangShan/scripts/top-down/draw.py
/XiangShan/scripts/top-down/top_down.py
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/resources/config/Default.yml
/XiangShan/src/main/scala/device/AXI4Memory.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDebugModule.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/ArgParser.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/top/YamlParser.scala
/XiangShan/src/main/scala/utils/LowPowerState.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/XSTileWrap.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Fence.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/mem/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/utility
8893eb2c12-Mar-2025 Zhaoyang You <[email protected]>

fix(csr): CSRR instruction read xireg inOrder (#4393)

* AIA registers are designed to be access asynchronously, so newCSR will
wait for response. Therefore, CSRR instruction read mireg/sireg/vsireg

fix(csr): CSRR instruction read xireg inOrder (#4393)

* AIA registers are designed to be access asynchronously, so newCSR will
wait for response. Therefore, CSRR instruction read mireg/sireg/vsireg
inOrder.

show more ...


/XiangShan/.github/workflows/emu.yml
/XiangShan/.gitmodules
/XiangShan/ChiselAIA
/XiangShan/Makefile
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/ready-to-run
/XiangShan/scalastyle-config.xml
/XiangShan/scalastyle-test-config.xml
/XiangShan/src/main/scala/device/IMSICAsync.scala
/XiangShan/src/main/scala/device/MemEncrypt.scala
/XiangShan/src/main/scala/device/imsic_axi_top.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/ArgParser.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/XSTileWrap.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSROoORead.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/Trigger.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/LegacyMetaArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/InstrUncache.scala
/XiangShan/src/main/scala/xiangshan/mem/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/test/scala/xiangshan/frontend/FrontTrigger.scala
a2ecedc906-Mar-2025 Ziyue Zhang <[email protected]>

fix(vlbusytable): fix vlbusytable update (#4364)


/XiangShan/.github/workflows/emu.yml
/XiangShan/.github/workflows/perf.yml
/XiangShan/Makefile
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/scripts/top-down/configs.py
/XiangShan/src/main/scala/device/MemEncrypt.scala
/XiangShan/src/main/scala/device/MemEncryptUtil.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/ArgParser.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/PMParameters.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/XSTileWrap.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRDefines.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/SretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/PFEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/VirtualSupervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
BusyTable.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/BitmapCheck.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/Bundles.scala
/XiangShan/src/main/scala/xiangshan/mem/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueUncache.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StreamPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StridePrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/PrefetcherMonitor.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/utility
075d493730-Dec-2024 junxiong-ji <[email protected]>

feat(CSR): allow most CSRR can be out-of-order issued and executed

* Add some comment on rdata in NewCSR.
* Allow CSRR not to block backward instruction.
* Here is **Inorder** CSRR list,
* fflags,

feat(CSR): allow most CSRR can be out-of-order issued and executed

* Add some comment on rdata in NewCSR.
* Allow CSRR not to block backward instruction.
* Here is **Inorder** CSRR list,
* fflags, fcsr,
* vxsat, vcsr, vstart,
* mstatus, sstatus, hstatus, vsstatus, mnstatus,
* dcsr.
* The reason for Inorder CSRR executed is that these CSR will be changed
by Use-Level instruction without any fence, and executing OoO would
get wrong result.
* Since there must be FENCE before reading any PMC CSRs, there is no
need to let reading PMC CSRs inorder.

show more ...


/XiangShan/.github/workflows/artifacts.yml
/XiangShan/.github/workflows/emu.yml
/XiangShan/Makefile
/XiangShan/README.md
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/huancun
/XiangShan/openLLC
/XiangShan/readme.zh-cn.md
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/resources/config/Default.yml
/XiangShan/src/main/scala/device/AXI4Memory.scala
/XiangShan/src/main/scala/device/RocketDebugWrapper.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDebugModule.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/ArgParser.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/top/YamlParser.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/PMParameters.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/XSTileWrap.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRCustom.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/DretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MNretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSROoORead.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/DebugLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/SstcInterruptGen.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/VirtualSupervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMP.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/cache/CacheConstants.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/Bundles.scala
/XiangShan/src/main/scala/xiangshan/mem/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueUncache.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchInterface.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StreamPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StridePrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/PrefetcherMonitor.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/FakeSbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/src/test/scala/top/SimTop.scala
/XiangShan/utility
/XiangShan/yunsuan
398aeef606-Jan-2025 Tang Haojin <[email protected]>

fix(Rename): fuse lui-load only if `rfWen` of lui is true (#4131)


/XiangShan/.github/CODEOWNERS
/XiangShan/.github/workflows/perf.yml
/XiangShan/Makefile
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/openLLC
/XiangShan/ready-to-run
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/top/ArgParser.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/ctrlblock/RedirectGenerator.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FusionDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRCustom.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/PMPEntryModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapHandleModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/util/CSRConst.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala
Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheCtrlUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/InstrUncache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueUncache.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/transforms/PrintModuleName.scala
/XiangShan/src/test/scala/top/SimTop.scala
/XiangShan/utility
8b33cd3013-Dec-2024 klin02 <[email protected]>

feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
Wh

feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
WhenContext. For example, when(cond1){XSDebug(cond2, pable)} to
XSDebug(cond1 && cond2, pable)

show more ...


/XiangShan/src/main/scala/device/AXI4SlaveModule.scala
/XiangShan/src/main/scala/device/TLTimer.scala
/XiangShan/src/main/scala/utils/DebugIdentityNode.scala
/XiangShan/src/main/scala/utils/TLDump.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapHandleModule.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/DataArray.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
Snapshot.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobDeqPtrWrapper.scala
/XiangShan/src/main/scala/xiangshan/backend/trace/Interface.scala
/XiangShan/src/main/scala/xiangshan/backend/trace/Trace.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/AbstractDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/DuplicatedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/AtomicsReplayUnit.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/LegacyMetaArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueUncache.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala
/XiangShan/src/main/scala/xiangshan/mem/mdp/WaitTable.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
41eedc8d16-Dec-2024 linzhida <[email protected]>

timing(zacas): move isDropAmocasSta logic gen from Scheduler to NewDispatch


/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/ctrlblock/RedirectGenerator.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Jump.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/FpPipedFuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/BranchUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FDivSqrt.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/FMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/JumpUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/regfile/Regfile.scala
Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
3019c60128-Nov-2024 xiaofeibao <[email protected]>

timing(backend): pipe robCommits for better timing and area

0a7d1d5c22-Nov-2024 xiaofeibao <[email protected]>

feat(backend): NewDispatch


/XiangShan/.github/filters.yaml
/XiangShan/.github/workflows/format.yml
/XiangShan/coupledL2
/XiangShan/ready-to-run
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/device/AXI4IntrGenerator.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/BypassNetwork.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch2IqFpImp.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
/XiangShan/src/main/scala/xiangshan/backend/regcache/RegCacheTagTable.scala
BusyTable.scala
Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/trace/Interface.scala
/XiangShan/src/main/scala/xiangshan/backend/trace/Trace.scala
/XiangShan/src/main/scala/xiangshan/backend/trace/TraceBuffer.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/CtrlUnit.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/package.scala
c308d93621-Nov-2024 chengguanghui <[email protected]>

fix(trace): remove traceTrap & tracePriv from trace pipeline

b720b0cd30-Oct-2024 chengguanghui <[email protected]>

fix(trace): fix `tracePipe` in pipeline

* fix itype for branch after writeback
* update itype to DeqGroup when branch instruction commit at next cycle after writeback.
* fix ftqoffset in commitIn

fix(trace): fix `tracePipe` in pipeline

* fix itype for branch after writeback
* update itype to DeqGroup when branch instruction commit at next cycle after writeback.
* fix ftqoffset in commitInfo for fuse instruction
* fix `iretire` in rename

show more ...


/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/ready-to-run
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/XSTileWrap.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
CompressUnit.scala
Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/trace/Interface.scala
/XiangShan/src/main/scala/xiangshan/backend/trace/Trace.scala
/XiangShan/src/main/scala/xiangshan/backend/trace/TraceBuffer.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueData.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAW.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/test/scala/top/SimTop.scala
/XiangShan/utility
38c2959426-Nov-2024 zhanglinjuan <[email protected]>

feat(MemBlock): add support for Zacas extension

fix(AtomicsUnit, MemBlock): fix loss of multiple stds

In the previous design, AtomicsUnit receives stds from StdExeUnit and
arbitrate at most one std

feat(MemBlock): add support for Zacas extension

fix(AtomicsUnit, MemBlock): fix loss of multiple stds

In the previous design, AtomicsUnit receives stds from StdExeUnit and
arbitrate at most one std uop for one cycle. This works fine on most of
the AMOs and LR/SC because they require only one std uop. However AMOCAS
requires at least two std uops, which may be issued from two separate
issue queues at the same time, leading to the loss of std uops.

This commit fixes this by taking all the outputs of the StdExeUnits into
account with arbitration logics.

fix(AtomicsUnit): DCache req can only be sent at `s_cache_req`

fix(AtomicsUnit, difftest): fix difftest io for atomic events

fix(MainPipe): fix precedence of `&` and `=/=` operator

fix(MainPipe): AMOCAS should not wait for AMOALU

fix(MemBlock): remove unnecessary assertion

fix(MainPipe): only CAS instruction can assert `s3_cas_fail`

fix(AtomicsUnit): fix bug in data select logic

submodule(difftest): bump difftest

show more ...

12861ac721-Nov-2024 linzhida <[email protected]>

feat(Backend): add support for Zacas extension

misc: remove assert temporarily


/XiangShan/.github/workflows/emu.yml
/XiangShan/Makefile
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/openLLC
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRDefines.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/Uncache.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueRAR.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueUncache.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/utility
547d96ac01-Dec-2024 Tang Haojin <[email protected]>

fix(vector): do not set vs.dirty for some type of vecInsts (#3965)


/XiangShan/.github/workflows/emu.yml
/XiangShan/.mill-version
/XiangShan/build.sc
/XiangShan/difftest
/XiangShan/ready-to-run
/XiangShan/src/main/scala/device/IMSIC.scala
/XiangShan/src/main/scala/top/XiangShanStage.scala
/XiangShan/src/main/scala/utils/SeqUtils.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSDts.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/PMPEntryModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/SchdBlockParams.scala
Rename.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/FIFO.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/InstrUncache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/yunsuan
3dfb64bd25-Nov-2024 Zehao Liu <[email protected]>

fix(HPM): fix PTW perfevent print error, organize the code format of some perfevents (#3890)

`getperfevent` retrieves both the `name` and `value` fields, whereas
`getperf` only retrieves the `value

fix(HPM): fix PTW perfevent print error, organize the code format of some perfevents (#3890)

`getperfevent` retrieves both the `name` and `value` fields, whereas
`getperf` only retrieves the `value` port. The original implementation
caused all perf event information for PTW to be printed as
`perfEventsPTW`, making them indistinguishable.

show more ...

09910ab022-Nov-2024 Ziyue Zhang <[email protected]>

fix(vlbusytable): fix int vl writeback wrong use vf vl writeback (#3909)


/XiangShan/README.md
/XiangShan/difftest
/XiangShan/images/xs-arch-kunminghu.svg
/XiangShan/readme.zh-cn.md
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/src/main/scala/device/standalone/StandAloneDebugModule.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDevice.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/backend/GPAMem.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/DretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapHandleModule.scala
BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/FauFTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/utility
c49ebec818-Nov-2024 Haoyuan Feng <[email protected]>

docs: add acknowledgements (#3861)


/XiangShan/.github/workflows/emu.yml
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/Multiplier.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryDEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/DebugLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/SRT16Divider.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
CompressUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MissQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/mdp/StoreSet.scala
/XiangShan/src/main/scala/xiangshan/mem/mdp/WaitTable.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/FDP.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1StridePrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/sbuffer/Sbuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
4376b52508-Nov-2024 Ziyue Zhang <[email protected]>

busytable: support eliminate old vd when read vl's state


/XiangShan/.github/workflows/emu.yml
/XiangShan/.github/workflows/format.yml
/XiangShan/.github/workflows/perf.yml
/XiangShan/.scalafmt.conf
/XiangShan/Makefile
/XiangShan/README.md
/XiangShan/build.sc
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSDts.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/XSTileWrap.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/GPAMem.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/FPDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnitParams.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MNretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/SretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CommitIDModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/SupervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapHandleModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/VirtualSupervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/IntToFP.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFDivSqrt.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFMA.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/data/BankedDataArray.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/meta/TagArray.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/Bim.scala
/XiangShan/src/main/scala/xiangshan/frontend/Composer.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/FauFTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/PreDecode.scala
/XiangShan/src/main/scala/xiangshan/frontend/RAS.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/WrBypass.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/FIFO.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMissUnit.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/InstrUncache.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/UncacheBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/utility
/XiangShan/yunsuan
b9dc808d25-Oct-2024 JinHong Zeng <[email protected]>

fix(Rename): remove the handling of dest being src in bypassCond (#3752)

67af58f715-Oct-2024 sinsanction <[email protected]>

timing(BusyTable, RegCacheTagModule): loadDependency do not need clear by cancel

e311c27815-Oct-2024 sinsanction <[email protected]>

fix(IssueQueue, BusyTable): refactor wakeup and cancel, and remove redundant logic


/XiangShan/.github/workflows/emu.yml
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/device/imsic_axi_top.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/Configs.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/utils/AXI4Lite.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSDts.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/XSTileWrap.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/VecExcpDataMergeModule.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/VldMergeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/WbArbiter.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/isa/bitfield/RiscvInst.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/DebugLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/vector/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VIAluFix.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EnqEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/OthersEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
BusyTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/ExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VfofBuffer.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/src/test/scala/top/SimMMIO.scala
/XiangShan/src/test/scala/top/SimTop.scala
df3b4b9220-Sep-2024 Anzooooo <[email protected]>

feat(rv64v): support first only fault instruction


/XiangShan/.github/workflows/emu.yml
/XiangShan/.github/workflows/perf.yml
/XiangShan/Makefile
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/ready-to-run
/XiangShan/scripts/parser.py
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/resources/aia
/XiangShan/src/main/scala/device/IMSICAsync.scala
/XiangShan/src/main/scala/device/imsic_axi_top.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDebugModule.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDevice.scala
/XiangShan/src/main/scala/system/SoC.scala
/XiangShan/src/main/scala/top/Top.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/xiangshan/L2Top.scala
/XiangShan/src/main/scala/xiangshan/PMParameters.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSDts.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/XSTileWrap.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/GPAMem.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeStage.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnitComp.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/UopInfoGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VTypeGen.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecDecoder.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRDefines.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/DretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MNretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/SretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryDEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMNEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRFields.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Debug.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/ExceptionBundle.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/InterruptFilter.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapInstMod.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/Unprivileged.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/SRT16Divider.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VCVT.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VFALU.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/VSet.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Dispatch2Iq.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Entries.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/EntryBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/Scheduler.scala
Rename.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/ExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/VTypeBuffer.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/DCacheWrapper.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/loadpipe/LoadPipe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/Probe.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/mainpipe/WritebackQueue.scala
/XiangShan/src/main/scala/xiangshan/cache/dcache/storepipe/StorePipe.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/Repeater.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala
/XiangShan/src/main/scala/xiangshan/frontend/BPU.scala
/XiangShan/src/main/scala/xiangshan/frontend/FTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/FauFTB.scala
/XiangShan/src/main/scala/xiangshan/frontend/Frontend.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/SC.scala
/XiangShan/src/main/scala/xiangshan/frontend/Tage.scala
/XiangShan/src/main/scala/xiangshan/frontend/WrBypass.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/WayLookup.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/mem/MemCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LSQWrapper.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueueReplay.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/VirtualLoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchComponent.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/L1PrefetchInterface.scala
/XiangShan/src/main/scala/xiangshan/mem/prefetch/SMSPrefetcher.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSplit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VfofBuffer.scala
/XiangShan/src/main/scala/xiangshan/package.scala
/XiangShan/src/test/scala/xiangshan/backend/dispatch/Dispatch2IqMain.scala
/XiangShan/utility
63d67ef314-Sep-2024 Tang Haojin <[email protected]>

build: enable always-basic-diff for make verilog (#3574)

This commit turns on basic difftest features again, no matter it's for
simulation or physical design. This commit aims at allowing designs f

build: enable always-basic-diff for make verilog (#3574)

This commit turns on basic difftest features again, no matter it's for
simulation or physical design. This commit aims at allowing designs for
physical design to be verified.

show more ...


/XiangShan/.github/filters.yaml
/XiangShan/.github/workflows/perf.yml
/XiangShan/Makefile
/XiangShan/coupledL2
/XiangShan/difftest
/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/src/main/scala/device/RocketDebugWrapper.scala
/XiangShan/src/main/scala/device/imsic_axi_top.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDebugModule.scala
/XiangShan/src/main/scala/device/standalone/StandAloneDevice.scala
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/Parameters.scala
/XiangShan/src/main/scala/xiangshan/XSCore.scala
/XiangShan/src/main/scala/xiangshan/XSTile.scala
/XiangShan/src/main/scala/xiangshan/XSTileWrap.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/BackendParams.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/datapath/DataPath.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/DecodeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/decode/VecExceptionGen.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRBundles.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRDefines.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSRPermitModule.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/HypervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/PMA.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/BranchUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/issue/IssueQueue.scala
Rename.scala
RenameTable.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUConst.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableCache.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLBStorage.scala
/XiangShan/src/main/scala/xiangshan/frontend/ITTAGE.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadExceptionBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreMisalignBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecBundle.scala
/XiangShan/src/main/scala/xiangshan/mem/vector/VecCommon.scala
/XiangShan/src/test/scala/top/SimMMIO.scala
6112d99409-Sep-2024 xiaofeibao <[email protected]>

timing(Backend): remove useless ldest=/=0.U logic because rfWen will be false


/XiangShan/ready-to-run
/XiangShan/rocket-chip
/XiangShan/scripts/xiangshan.py
/XiangShan/src/main/scala/top/XSNoCTop.scala
/XiangShan/src/main/scala/xiangshan/Bundle.scala
/XiangShan/src/main/scala/xiangshan/DbEntry.scala
/XiangShan/src/main/scala/xiangshan/backend/Backend.scala
/XiangShan/src/main/scala/xiangshan/backend/Bundles.scala
/XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/MemBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/dispatch/Dispatch.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/exu/ExuBlock.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/FuncUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/CSREvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/DretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MNretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/MretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/SretEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryDEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryHSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryMNEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/CSREvents/TrapEntryVSEvent.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/TrapTvalMod.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/NewCSR/VirtualSupervisorLevel.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/BranchUnit.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/CSR.scala
/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/JumpUnit.scala
Rename.scala
freelist/MEFreeList.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rab.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/Rob.scala
/XiangShan/src/main/scala/xiangshan/backend/rob/RobBundles.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/L2TLB.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/MMUBundle.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
/XiangShan/src/main/scala/xiangshan/cache/mmu/TLB.scala
/XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala
/XiangShan/src/main/scala/xiangshan/frontend/IBuffer.scala
/XiangShan/src/main/scala/xiangshan/frontend/IFU.scala
/XiangShan/src/main/scala/xiangshan/frontend/NewFtq.scala
/XiangShan/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
/XiangShan/src/main/scala/xiangshan/frontend/newRAS.scala
/XiangShan/src/main/scala/xiangshan/package.scala

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