1package xiangshan.backend.issue 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import xiangshan._ 8import xiangshan.backend.Bundles 9import xiangshan.backend.datapath.DataConfig.VAddrData 10import xiangshan.backend.regfile.RfWritePortWithConfig 11import xiangshan.backend.rename.BusyTable 12import xiangshan.mem.{LsqEnqCtrl, LsqEnqIO, MemWaitUpdateReq, SqPtr} 13import xiangshan.backend.Bundles.{DynInst, IssueQueueWakeUpBundle} 14 15sealed trait SchedulerType 16 17case class IntScheduler() extends SchedulerType 18case class MemScheduler() extends SchedulerType 19case class VfScheduler() extends SchedulerType 20case class NoScheduler() extends SchedulerType 21 22class Scheduler(val params: SchdBlockParams)(implicit p: Parameters) extends LazyModule with HasXSParameter { 23 val numIntStateWrite = backendParams.numIntWb 24 val numVfStateWrite = backendParams.numVfWb 25 26 val dispatch2Iq = LazyModule(new Dispatch2Iq(params)) 27 val issueQueue = params.issueBlockParams.map(x => LazyModule(new IssueQueue(x).suggestName(x.getIQName))) 28 29 lazy val module = params.schdType match { 30 case IntScheduler() => new SchedulerArithImp(this)(params, p) 31 case MemScheduler() => new SchedulerMemImp(this)(params, p) 32 case VfScheduler() => new SchedulerArithImp(this)(params, p) 33 case _ => null 34 } 35} 36 37class SchedulerIO()(implicit params: SchdBlockParams, p: Parameters) extends XSBundle { 38 val fromTop = new Bundle { 39 val hartId = Input(UInt(8.W)) 40 } 41 val fromCtrlBlock = new Bundle { 42 val pcVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 43 val targetVec = Input(Vec(params.numPcReadPort, UInt(VAddrData().dataWidth.W))) 44 val flush = Flipped(ValidIO(new Redirect)) 45 } 46 val fromDispatch = new Bundle { 47 val allocPregs = Vec(RenameWidth, Input(new ResetPregStateReq)) 48 val uops = Vec(params.numUopIn, Flipped(DecoupledIO(new DynInst))) 49 } 50 val intWriteBack = MixedVec(Vec(backendParams.intPregParams.numWrite, 51 new RfWritePortWithConfig(backendParams.intPregParams.dataCfg, backendParams.intPregParams.addrWidth))) 52 val vfWriteBack = MixedVec(Vec(backendParams.vfPregParams.numWrite, 53 new RfWritePortWithConfig(backendParams.vfPregParams.dataCfg, backendParams.vfPregParams.addrWidth))) 54 val toDataPath: MixedVec[MixedVec[DecoupledIO[Bundles.IssueQueueIssueBundle]]] = MixedVec(params.issueBlockParams.map(_.genIssueDecoupledBundle)) 55 val fromDataPath: MixedVec[MixedVec[Bundles.OGRespBundle]] = MixedVec(params.issueBlockParams.map(x => Flipped(x.genOGRespBundle))) 56 57 val memIO = if (params.isMemSchd) Some(new Bundle { 58 val feedbackIO = Flipped(Vec(params.StaCnt, new MemRSFeedbackIO)) 59 val lsqEnqIO = Flipped(new LsqEnqIO) 60 }) else None 61 val fromMem = if (params.isMemSchd) Some(new Bundle { 62 val stIssuePtr = Input(new SqPtr()) 63 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 64 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) // connected to `memBlock.io.sqDeq` instead of ROB 65 // from lsq 66 val lqCancelCnt = Input(UInt(log2Up(LoadQueueSize + 1).W)) 67 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 68 val memWaitUpdateReq = Flipped(new MemWaitUpdateReq) 69 }) else None 70 val toMem = if (params.isMemSchd) Some(new Bundle { 71 val loadFastMatch = Output(Vec(params.LduCnt, new IssueQueueLoadBundle)) 72 }) else None 73} 74 75abstract class SchedulerImpBase(wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 76 extends LazyModuleImp(wrapper) 77 with HasXSParameter 78{ 79 val io = IO(new SchedulerIO()) 80 81 // alias 82 private val schdType = params.schdType 83 private val (numRfRead, numRfWrite) = params.numRfReadWrite.getOrElse((0, 0)) 84 private val numPregs = params.numPregs 85 86 // Modules 87 val dispatch2Iq: Dispatch2IqImp = wrapper.dispatch2Iq.module 88 val issueQueues: Seq[IssueQueueImp] = wrapper.issueQueue.map(_.module) 89 90 // BusyTable Modules 91 val intBusyTable = schdType match { 92 case IntScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numIntStateRead, wrapper.numIntStateWrite))) 93 case _ => None 94 } 95 96 val vfBusyTable = schdType match { 97 case VfScheduler() | MemScheduler() => Some(Module(new BusyTable(dispatch2Iq.numVfStateRead, wrapper.numVfStateWrite))) 98 case _ => None 99 } 100 101 dispatch2Iq.io match { case dp2iq => 102 dp2iq.redirect <> io.fromCtrlBlock.flush 103 dp2iq.in <> io.fromDispatch.uops 104 dp2iq.readIntState.foreach(_ <> intBusyTable.get.io.read) 105 dp2iq.readVfState.foreach(_ <> vfBusyTable.get.io.read) 106 } 107 108 intBusyTable match { 109 case Some(bt) => 110 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 111 btAllocPregs.valid := dpAllocPregs.isInt 112 btAllocPregs.bits := dpAllocPregs.preg 113 } 114 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 115 wb.valid := io.intWriteBack(i).wen && io.intWriteBack(i).intWen 116 wb.bits := io.intWriteBack(i).addr 117 } 118 case None => 119 } 120 121 vfBusyTable match { 122 case Some(bt) => 123 bt.io.allocPregs.zip(io.fromDispatch.allocPregs).foreach { case (btAllocPregs, dpAllocPregs) => 124 btAllocPregs.valid := dpAllocPregs.isFp 125 btAllocPregs.bits := dpAllocPregs.preg 126 } 127 bt.io.wbPregs.zipWithIndex.foreach { case (wb, i) => 128 wb.valid := io.vfWriteBack(i).wen && (io.vfWriteBack(i).fpWen || io.vfWriteBack(i).vecWen) 129 wb.bits := io.vfWriteBack(i).addr 130 } 131 case None => 132 } 133 134 val wakeupFromWBVec = Wire(Vec(params.numWakeupFromWB, ValidIO(new IssueQueueWakeUpBundle(params.pregIdxWidth)))) 135 val writeback = params.schdType match { 136 case IntScheduler() => io.intWriteBack 137 case MemScheduler() => io.intWriteBack ++ io.vfWriteBack 138 case VfScheduler() => io.vfWriteBack 139 case _ => Seq() 140 } 141 wakeupFromWBVec.zip(writeback).foreach { case (sink, source) => 142 sink.valid := source.wen 143 sink.bits.rfWen := source.intWen 144 sink.bits.fpWen := source.fpWen 145 sink.bits.vecWen := source.vecWen 146 sink.bits.pdest := source.addr 147 } 148 149 io.toDataPath.zipWithIndex.foreach { case (toDp, i) => 150 toDp <> issueQueues(i).io.deq 151 } 152} 153 154class SchedulerArithImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 155 extends SchedulerImpBase(wrapper) 156 with HasXSParameter 157{ 158 println(s"[SchedulerArithImp] " + 159 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 160 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 161 162 issueQueues.zipWithIndex.foreach { case (iq, i) => 163 iq.io.flush <> io.fromCtrlBlock.flush 164 iq.io.enq <> dispatch2Iq.io.out(i) 165 iq.io.wakeup := wakeupFromWBVec 166 iq.io.deqResp.zipWithIndex.foreach { case (deqResp, j) => 167 deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready 168 deqResp.bits.success := false.B 169 deqResp.bits.respType := RSFeedbackType.issueSuccess 170 deqResp.bits.addrOH := iq.io.deq(j).bits.addrOH 171 } 172 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 173 og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid 174 og0Resp.bits.success := false.B // Todo: remove it 175 og0Resp.bits.respType := io.fromDataPath(i)(j).og0resp.bits.respType 176 og0Resp.bits.addrOH := io.fromDataPath(i)(j).og0resp.bits.addrOH 177 } 178 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 179 og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid 180 og1Resp.bits.success := false.B 181 og1Resp.bits.respType := io.fromDataPath(i)(j).og1resp.bits.respType 182 og1Resp.bits.addrOH := io.fromDataPath(i)(j).og1resp.bits.addrOH 183 } 184 } 185 186 val iqJumpBundleVec: Seq[IssueQueueJumpBundle] = issueQueues.map { 187 case imp: IssueQueueIntImp => imp.io.enqJmp 188 case _ => None 189 }.filter(_.nonEmpty).flatMap(_.get) 190 println(s"[Scheduler] iqJumpBundleVec: ${iqJumpBundleVec}") 191 192 iqJumpBundleVec.zip(io.fromCtrlBlock.pcVec zip io.fromCtrlBlock.targetVec).foreach { case (iqJmp, (pc, target)) => 193 iqJmp.pc := pc 194 iqJmp.target := target 195 } 196} 197 198class SchedulerMemImp(override val wrapper: Scheduler)(implicit params: SchdBlockParams, p: Parameters) 199 extends SchedulerImpBase(wrapper) 200 with HasXSParameter 201{ 202 println(s"[SchedulerMemImp] " + 203 s"has intBusyTable: ${intBusyTable.nonEmpty}, " + 204 s"has vfBusyTable: ${vfBusyTable.nonEmpty}") 205 206 val memAddrIQs = issueQueues.filter(iq => iq.params.StdCnt == 0) 207 val stAddrIQs = issueQueues.filter(iq => iq.params.StaCnt > 0) // included in memAddrIQs 208 val stDataIQs = issueQueues.filter(iq => iq.params.StdCnt > 0) 209 require(memAddrIQs.nonEmpty && stDataIQs.nonEmpty) 210 211 issueQueues.zipWithIndex.foreach { case (iq, i) => 212 iq.io.deqResp.zipWithIndex.foreach { case (deqResp, j) => 213 deqResp.valid := iq.io.deq(j).valid && io.toDataPath(i)(j).ready 214 deqResp.bits.success := false.B 215 deqResp.bits.respType := RSFeedbackType.issueSuccess 216 deqResp.bits.addrOH := iq.io.deq(j).bits.addrOH 217 } 218 iq.io.og0Resp.zipWithIndex.foreach { case (og0Resp, j) => 219 og0Resp.valid := io.fromDataPath(i)(j).og0resp.valid 220 og0Resp.bits.success := false.B // Todo: remove it 221 og0Resp.bits.respType := io.fromDataPath(i)(j).og0resp.bits.respType 222 og0Resp.bits.addrOH := io.fromDataPath(i)(j).og0resp.bits.addrOH 223 } 224 iq.io.og1Resp.zipWithIndex.foreach { case (og1Resp, j) => 225 og1Resp.valid := io.fromDataPath(i)(j).og1resp.valid 226 og1Resp.bits.success := false.B 227 og1Resp.bits.respType := io.fromDataPath(i)(j).og1resp.bits.respType 228 og1Resp.bits.addrOH := io.fromDataPath(i)(j).og1resp.bits.addrOH 229 } 230 } 231 232 memAddrIQs.zipWithIndex.foreach { case (iq, i) => 233 iq.io.flush <> io.fromCtrlBlock.flush 234 iq.io.enq <> dispatch2Iq.io.out(i) 235 iq.io.wakeup := wakeupFromWBVec 236 } 237 238 239 dispatch2Iq.io.out(1).zip(stAddrIQs(0).io.enq).zip(stDataIQs(0).io.enq).foreach{ case((di, staIQ), stdIQ) => 240 val isAllReady = staIQ.ready && stdIQ.ready 241 di.ready := isAllReady 242 staIQ.valid := di.valid && isAllReady 243 stdIQ.valid := di.valid && isAllReady 244 } 245 246 require(stAddrIQs.size == stDataIQs.size, s"number of store address IQs(${stAddrIQs.size}) " + 247 s"should be equal to number of data IQs(${stDataIQs})") 248 stDataIQs.zip(stAddrIQs).zipWithIndex.foreach { case ((stdIQ, staIQ), i) => 249 stdIQ.io.flush <> io.fromCtrlBlock.flush 250 251 stdIQ.io.enq.zip(staIQ.io.enq).foreach { case (stdIQEnq, staIQEnq) => 252 stdIQEnq.bits := staIQEnq.bits 253 // Store data reuses store addr src(1) in dispatch2iq 254 // [dispatch2iq] --src*------src*(0)--> [staIQ] 255 // \ 256 // ---src*(1)--> [stdIQ] 257 // Since the src(1) of sta is easier to get, stdIQEnq.bits.src*(0) is assigned to staIQEnq.bits.src*(1) 258 // instead of dispatch2Iq.io.out(x).bits.src*(1) 259 stdIQEnq.bits.srcState(0) := staIQEnq.bits.srcState(1) 260 stdIQEnq.bits.srcType(0) := staIQEnq.bits.srcType(1) 261 stdIQEnq.bits.psrc(0) := staIQEnq.bits.psrc(1) 262 stdIQEnq.bits.sqIdx := staIQEnq.bits.sqIdx 263 } 264 stdIQ.io.wakeup := wakeupFromWBVec 265 } 266 267 val iqMemBundleVec = stAddrIQs.map { 268 case imp: IssueQueueMemAddrImp => imp.io.memIO 269 case _ => None 270 }.filter(_.nonEmpty).map(_.get) 271 println(s"[Scheduler] iqMemBundleVec: ${iqMemBundleVec}") 272 273 val lsqEnqCtrl = Module(new LsqEnqCtrl) 274 275 lsqEnqCtrl.io.redirect <> io.fromCtrlBlock.flush 276 lsqEnqCtrl.io.enq <> dispatch2Iq.io.enqLsqIO.get 277 lsqEnqCtrl.io.lcommit := io.fromMem.get.lcommit 278 lsqEnqCtrl.io.scommit := io.fromMem.get.scommit 279 lsqEnqCtrl.io.lqCancelCnt := io.fromMem.get.lqCancelCnt 280 lsqEnqCtrl.io.sqCancelCnt := io.fromMem.get.sqCancelCnt 281 io.memIO.get.lsqEnqIO <> lsqEnqCtrl.io.enqLsq 282 require(io.memIO.get.feedbackIO.size == iqMemBundleVec.map(_.feedbackIO.size).sum, 283 s"[SchedulerMemImp] io.memIO.feedbackIO.size(${io.memIO.get.feedbackIO.size}) " + 284 s"should be equal to sum of memIQ.io.feedbackIO.size(${iqMemBundleVec.map(_.feedbackIO.size).sum})") 285 286 val memIQFeedbackIO: Seq[MemRSFeedbackIO] = iqMemBundleVec.flatMap(_.feedbackIO) 287 io.memIO.get.feedbackIO <> memIQFeedbackIO 288} 289