1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import xiangshan.backend.fu.FuType 30import freechips.rocketchip.rocket.Instructions._ 31import xiangshan.backend.Bundles.{DecodedInst, StaticInst} 32import xiangshan.backend.decode.isa.bitfield.XSInstBitFields 33import xiangshan.backend.fu.vector.Bundles.VType 34import yunsuan.VpermType 35 36import scala.collection.Seq 37 38trait VectorConstants { 39 val MAX_VLMUL = 8 40 val FP_TMP_REG_MV = 32 41 val VECTOR_TMP_REG_LMUL = 33 // 33~47 -> 15 42} 43 44class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 45 val enq = new Bundle { val staticInst = Input(new StaticInst) } 46 val vtype = Input(new VType) 47 val isComplex = Input(Vec(DecodeWidth - 1, Bool())) 48 val validFromIBuf = Input(Vec(DecodeWidth, Bool())) 49 val readyFromRename = Input(Vec(RenameWidth, Bool())) 50 val deq = new Bundle { 51 val decodedInsts = Output(Vec(RenameWidth, new DecodedInst)) 52 val isVset = Output(Bool()) 53 val readyToIBuf = Output(Vec(DecodeWidth, Bool())) 54 val validToRename = Output(Vec(RenameWidth, Bool())) 55 val complexNum = Output(UInt(3.W)) 56 } 57 val csrCtrl = Input(new CustomCSRCtrlIO) 58} 59 60/** 61 * @author zly 62 */ 63class DecodeUnitComp()(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 64 val io = IO(new DecodeUnitCompIO) 65 66 val maxUopSize = MaxUopSize 67 //input bits 68 val staticInst = Wire(new StaticInst) 69 private val inst: XSInstBitFields = staticInst.asTypeOf(new XSInstBitFields) 70 71 staticInst := io.enq.staticInst 72 73 val src1 = Cat(0.U(1.W), inst.RS1) 74 val src2 = Cat(0.U(1.W), inst.RS2) 75 val dest = Cat(0.U(1.W), inst.RD) 76 val width = inst.RM //Vector LS eew 77 val eew = Cat(0.U(1.W), width(1, 0)) 78 79 //output bits 80 val decodedInsts = Wire(Vec(RenameWidth, new DecodedInst)) 81 val validToRename = Wire(Vec(RenameWidth, Bool())) 82 val readyToIBuf = Wire(Vec(DecodeWidth, Bool())) 83 val complexNum = Wire(UInt(3.W)) 84 85 //output of DecodeUnit 86 val decodedInstsSimple = Wire(new DecodedInst) 87 val isVsetSimple = Wire(Bool()) 88 89 //pre decode 90 val simple = Module(new DecodeUnit) 91 simple.io.enq.ctrlFlow := staticInst 92 simple.io.enq.vtype := io.vtype 93 simple.io.csrCtrl := io.csrCtrl 94 decodedInstsSimple := simple.io.deq.decodedInst 95 isVsetSimple := simple.io.deq.decodedInst.isVset 96 when(isVsetSimple) { 97 when(dest === 0.U && src1 === 0.U) { 98 decodedInstsSimple.fuOpType := VSETOpType.keepVl(simple.io.deq.decodedInst.fuOpType) 99 }.elsewhen(src1 === 0.U) { 100 decodedInstsSimple.fuOpType := VSETOpType.setVlmax(simple.io.deq.decodedInst.fuOpType) 101 } 102 when(io.vtype.illegal){ 103 decodedInstsSimple.flushPipe := true.B 104 } 105 } 106 //Type of uop Div 107 val typeOfSplit = decodedInstsSimple.uopSplitType 108 109 val sew = Cat(0.U(1.W), simple.io.enq.vtype.vsew) 110 val vlmul = simple.io.enq.vtype.vlmul 111 112 //LMUL 113 val lmul = MuxLookup(simple.io.enq.vtype.vlmul, 1.U(4.W), Array( 114 "b001".U -> 2.U, 115 "b010".U -> 4.U, 116 "b011".U -> 8.U 117 )) 118 val numOfUopVslide = MuxLookup(simple.io.enq.vtype.vlmul, 1.U(log2Up(maxUopSize+1).W), Array( 119 "b001".U -> 3.U, 120 "b010".U -> 10.U, 121 "b011".U -> 36.U 122 )) 123 val numOfUopVrgather = MuxLookup(simple.io.enq.vtype.vlmul, 1.U(log2Up(maxUopSize + 1).W), Array( 124 "b001".U -> 4.U, 125 "b010".U -> 16.U, 126 "b011".U -> 64.U 127 )) 128 val numOfUopVrgatherei16 = Mux((!simple.io.enq.vtype.vsew.orR) && (simple.io.enq.vtype.vlmul =/= "b011".U), 129 Cat(numOfUopVrgather, 0.U(1.W)), 130 numOfUopVrgather 131 ) 132 val numOfUopVcompress = MuxLookup(simple.io.enq.vtype.vlmul, 1.U(4.W), Array( 133 "b001".U -> 4.U, 134 "b010".U -> 13.U, 135 "b011".U -> 43.U 136 )) 137 val vemul : UInt = eew.asUInt + 1.U + vlmul.asUInt + ~sew.asUInt 138 val emul = MuxLookup(vemul, 1.U(4.W), Array( 139 "b001".U -> 2.U, 140 "b010".U -> 4.U, 141 "b011".U -> 8.U 142 )) //TODO : eew and emul illegal exception need to be handled 143 144 //number of uop 145 val numOfUop = MuxLookup(typeOfSplit, 1.U(log2Up(maxUopSize+1).W), Array( 146 UopSplitType.VEC_0XV -> 2.U, 147 UopSplitType.DIR -> Mux(dest =/= 0.U, 2.U, 148 Mux(src1 =/= 0.U, 1.U, 149 Mux(VSETOpType.isVsetvl(decodedInstsSimple.fuOpType), 2.U, 1.U))), 150 UopSplitType.VEC_VVV -> lmul, 151 UopSplitType.VEC_EXT2 -> lmul, 152 UopSplitType.VEC_EXT4 -> lmul, 153 UopSplitType.VEC_EXT8 -> lmul, 154 UopSplitType.VEC_VVM -> lmul, 155 UopSplitType.VEC_VXM -> (lmul +& 1.U), 156 UopSplitType.VEC_VXV -> (lmul +& 1.U), 157 UopSplitType.VEC_VVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 158 UopSplitType.VEC_WVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 159 UopSplitType.VEC_VXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 160 UopSplitType.VEC_WXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 161 UopSplitType.VEC_WVV -> Cat(lmul, 0.U(1.W)), // lmul <= 4 162 UopSplitType.VEC_WXV -> Cat(lmul, 1.U(1.W)), // lmul <= 4 163 UopSplitType.VEC_SLIDE1UP -> (lmul +& 1.U), 164 UopSplitType.VEC_FSLIDE1UP -> lmul, 165 UopSplitType.VEC_SLIDE1DOWN -> Cat(lmul, 0.U(1.W)), 166 UopSplitType.VEC_FSLIDE1DOWN -> (Cat(lmul, 0.U(1.W)) -1.U), 167 UopSplitType.VEC_VRED -> lmul, 168 UopSplitType.VEC_SLIDEUP -> (numOfUopVslide + 1.U), 169 UopSplitType.VEC_ISLIDEUP -> numOfUopVslide, 170 UopSplitType.VEC_SLIDEDOWN -> (numOfUopVslide + 1.U), 171 UopSplitType.VEC_ISLIDEDOWN -> numOfUopVslide, 172 UopSplitType.VEC_M0X -> (lmul +& 1.U), 173 UopSplitType.VEC_MVV -> (Cat(lmul, 0.U(1.W)) -1.U), 174 UopSplitType.VEC_M0X_VFIRST -> 2.U, 175 UopSplitType.VEC_VWW -> Cat(lmul, 0.U(1.W)), 176 UopSplitType.VEC_RGATHER -> numOfUopVrgather, 177 UopSplitType.VEC_RGATHER_VX -> (numOfUopVrgather +& 1.U), 178 UopSplitType.VEC_RGATHEREI16 -> numOfUopVrgatherei16, 179 UopSplitType.VEC_US_LD -> (emul +& 1.U), 180 )) 181 182 //uop div up to maxUopSize 183 val csBundle = Wire(Vec(maxUopSize, new DecodedInst)) 184 csBundle.map { case dst => 185 dst := decodedInstsSimple 186 dst.firstUop := false.B 187 dst.lastUop := false.B 188 } 189 190 csBundle(0).numUops := numOfUop 191 csBundle(0).firstUop := true.B 192 csBundle(numOfUop - 1.U).lastUop := true.B 193 194 switch(typeOfSplit) { 195 is(UopSplitType.DIR) { 196 when(isVsetSimple) { 197 when(dest =/= 0.U) { 198 csBundle(0).fuType := FuType.vsetiwi.U 199 csBundle(0).fuOpType := VSETOpType.switchDest(decodedInstsSimple.fuOpType) 200 csBundle(0).flushPipe := false.B 201 csBundle(0).rfWen := true.B 202 csBundle(0).vecWen := false.B 203 csBundle(1).ldest := VCONFIG_IDX.U 204 csBundle(1).rfWen := false.B 205 csBundle(1).vecWen := true.B 206 }.elsewhen(src1 =/= 0.U) { 207 csBundle(0).ldest := VCONFIG_IDX.U 208 }.elsewhen(VSETOpType.isVsetvli(decodedInstsSimple.fuOpType)) { 209 csBundle(0).fuType := FuType.vsetfwf.U 210 csBundle(0).srcType(0) := SrcType.vp 211 csBundle(0).lsrc(0) := VCONFIG_IDX.U 212 }.elsewhen(VSETOpType.isVsetvl(decodedInstsSimple.fuOpType)) { 213 csBundle(0).srcType(0) := SrcType.reg 214 csBundle(0).srcType(1) := SrcType.imm 215 csBundle(0).lsrc(1) := 0.U 216 csBundle(0).ldest := FP_TMP_REG_MV.U 217 csBundle(0).fuType := FuType.i2f.U 218 csBundle(0).rfWen := false.B 219 csBundle(0).fpWen := true.B 220 csBundle(0).vecWen := false.B 221 csBundle(0).fpu.isAddSub := false.B 222 csBundle(0).fpu.typeTagIn := FPU.D 223 csBundle(0).fpu.typeTagOut := FPU.D 224 csBundle(0).fpu.fromInt := true.B 225 csBundle(0).fpu.wflags := false.B 226 csBundle(0).fpu.fpWen := true.B 227 csBundle(0).fpu.div := false.B 228 csBundle(0).fpu.sqrt := false.B 229 csBundle(0).fpu.fcvt := false.B 230 csBundle(0).flushPipe := false.B 231 csBundle(1).fuType := FuType.vsetfwf.U 232 csBundle(1).srcType(0) := SrcType.vp 233 csBundle(1).lsrc(0) := VCONFIG_IDX.U 234 csBundle(1).srcType(1) := SrcType.fp 235 csBundle(1).lsrc(1) := FP_TMP_REG_MV.U 236 csBundle(1).ldest := VCONFIG_IDX.U 237 } 238 } 239 } 240 is(UopSplitType.VEC_VVV) { 241 for (i <- 0 until MAX_VLMUL) { 242 csBundle(i).lsrc(0) := src1 + i.U 243 csBundle(i).lsrc(1) := src2 + i.U 244 csBundle(i).lsrc(2) := dest + i.U 245 csBundle(i).ldest := dest + i.U 246 csBundle(i).uopIdx := i.U 247 } 248 } 249 is(UopSplitType.VEC_EXT2) { 250 for (i <- 0 until MAX_VLMUL / 2) { 251 csBundle(2 * i).lsrc(1) := src2 + i.U 252 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 253 csBundle(2 * i).ldest := dest + (2 * i).U 254 csBundle(2 * i).uopIdx := (2 * i).U 255 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 256 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 257 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 258 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 259 } 260 } 261 is(UopSplitType.VEC_EXT4) { 262 for (i <- 0 until MAX_VLMUL / 4) { 263 csBundle(4 * i).lsrc(1) := src2 + i.U 264 csBundle(4 * i).lsrc(2) := dest + (4 * i).U 265 csBundle(4 * i).ldest := dest + (4 * i).U 266 csBundle(4 * i).uopIdx := (4 * i).U 267 csBundle(4 * i + 1).lsrc(1) := src2 + i.U 268 csBundle(4 * i + 1).lsrc(2) := dest + (4 * i + 1).U 269 csBundle(4 * i + 1).ldest := dest + (4 * i + 1).U 270 csBundle(4 * i + 1).uopIdx := (4 * i + 1).U 271 csBundle(4 * i + 2).lsrc(1) := src2 + i.U 272 csBundle(4 * i + 2).lsrc(2) := dest + (4 * i + 2).U 273 csBundle(4 * i + 2).ldest := dest + (4 * i + 2).U 274 csBundle(4 * i + 2).uopIdx := (4 * i + 2).U 275 csBundle(4 * i + 3).lsrc(1) := src2 + i.U 276 csBundle(4 * i + 3).lsrc(2) := dest + (4 * i + 3).U 277 csBundle(4 * i + 3).ldest := dest + (4 * i + 3).U 278 csBundle(4 * i + 3).uopIdx := (4 * i + 3).U 279 } 280 } 281 is(UopSplitType.VEC_EXT8) { 282 for (i <- 0 until MAX_VLMUL) { 283 csBundle(i).lsrc(1) := src2 284 csBundle(i).lsrc(2) := dest + i.U 285 csBundle(i).ldest := dest + i.U 286 csBundle(i).uopIdx := i.U 287 } 288 } 289 is(UopSplitType.VEC_0XV) { 290 /* 291 FMV.D.X 292 */ 293 csBundle(0).srcType(0) := SrcType.reg 294 csBundle(0).srcType(1) := SrcType.imm 295 csBundle(0).lsrc(1) := 0.U 296 csBundle(0).ldest := FP_TMP_REG_MV.U 297 csBundle(0).fuType := FuType.i2f.U 298 csBundle(0).rfWen := false.B 299 csBundle(0).fpWen := true.B 300 csBundle(0).vecWen := false.B 301 csBundle(0).fpu.isAddSub := false.B 302 csBundle(0).fpu.typeTagIn := FPU.D 303 csBundle(0).fpu.typeTagOut := FPU.D 304 csBundle(0).fpu.fromInt := true.B 305 csBundle(0).fpu.wflags := false.B 306 csBundle(0).fpu.fpWen := true.B 307 csBundle(0).fpu.div := false.B 308 csBundle(0).fpu.sqrt := false.B 309 csBundle(0).fpu.fcvt := false.B 310 /* 311 vfmv.s.f 312 */ 313 csBundle(1).srcType(0) := SrcType.fp 314 csBundle(1).srcType(1) := SrcType.vp 315 csBundle(1).srcType(2) := SrcType.vp 316 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 317 csBundle(1).lsrc(1) := 0.U 318 csBundle(1).lsrc(2) := dest 319 csBundle(1).ldest := dest 320 csBundle(1).fuType := FuType.vppu.U 321 csBundle(1).fuOpType := VpermType.dummy 322 csBundle(1).rfWen := false.B 323 csBundle(1).fpWen := false.B 324 csBundle(1).vecWen := true.B 325 } 326 is(UopSplitType.VEC_VXV) { 327 /* 328 FMV.D.X 329 */ 330 csBundle(0).srcType(0) := SrcType.reg 331 csBundle(0).srcType(1) := SrcType.imm 332 csBundle(0).lsrc(1) := 0.U 333 csBundle(0).ldest := FP_TMP_REG_MV.U 334 csBundle(0).fuType := FuType.i2f.U 335 csBundle(0).rfWen := false.B 336 csBundle(0).fpWen := true.B 337 csBundle(0).vecWen := false.B 338 csBundle(0).fpu.isAddSub := false.B 339 csBundle(0).fpu.typeTagIn := FPU.D 340 csBundle(0).fpu.typeTagOut := FPU.D 341 csBundle(0).fpu.fromInt := true.B 342 csBundle(0).fpu.wflags := false.B 343 csBundle(0).fpu.fpWen := true.B 344 csBundle(0).fpu.div := false.B 345 csBundle(0).fpu.sqrt := false.B 346 csBundle(0).fpu.fcvt := false.B 347 /* 348 LMUL 349 */ 350 for (i <- 0 until MAX_VLMUL) { 351 csBundle(i + 1).srcType(0) := SrcType.fp 352 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 353 csBundle(i + 1).lsrc(1) := src2 + i.U 354 csBundle(i + 1).lsrc(2) := dest + i.U 355 csBundle(i + 1).ldest := dest + i.U 356 csBundle(i + 1).uopIdx := i.U 357 } 358 } 359 is(UopSplitType.VEC_VVW) { 360 for (i <- 0 until MAX_VLMUL / 2) { 361 csBundle(2 * i).lsrc(0) := src1 + i.U 362 csBundle(2 * i).lsrc(1) := src2 + i.U 363 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 364 csBundle(2 * i).ldest := dest + (2 * i).U 365 csBundle(2 * i).uopIdx := (2 * i).U 366 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 367 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 368 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 369 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 370 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 371 } 372 } 373 is(UopSplitType.VEC_WVW) { 374 for (i <- 0 until MAX_VLMUL / 2) { 375 csBundle(2 * i).lsrc(0) := src1 + i.U 376 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 377 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 378 csBundle(2 * i).ldest := dest + (2 * i).U 379 csBundle(2 * i).uopIdx := (2 * i).U 380 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 381 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 382 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 383 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 384 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 385 } 386 } 387 is(UopSplitType.VEC_VXW) { 388 /* 389 FMV.D.X 390 */ 391 csBundle(0).srcType(0) := SrcType.reg 392 csBundle(0).srcType(1) := SrcType.imm 393 csBundle(0).lsrc(1) := 0.U 394 csBundle(0).ldest := FP_TMP_REG_MV.U 395 csBundle(0).fuType := FuType.i2f.U 396 csBundle(0).rfWen := false.B 397 csBundle(0).fpWen := true.B 398 csBundle(0).vecWen := false.B 399 csBundle(0).fpu.isAddSub := false.B 400 csBundle(0).fpu.typeTagIn := FPU.D 401 csBundle(0).fpu.typeTagOut := FPU.D 402 csBundle(0).fpu.fromInt := true.B 403 csBundle(0).fpu.wflags := false.B 404 csBundle(0).fpu.fpWen := true.B 405 csBundle(0).fpu.div := false.B 406 csBundle(0).fpu.sqrt := false.B 407 csBundle(0).fpu.fcvt := false.B 408 409 for (i <- 0 until MAX_VLMUL / 2) { 410 csBundle(2 * i + 1).srcType(0) := SrcType.fp 411 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 412 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 413 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 414 csBundle(2 * i + 1).ldest := dest + (2 * i).U 415 csBundle(2 * i + 1).uopIdx := (2 * i).U 416 csBundle(2 * i + 2).srcType(0) := SrcType.fp 417 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 418 csBundle(2 * i + 2).lsrc(1) := src2 + i.U 419 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 420 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 421 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 422 } 423 } 424 is(UopSplitType.VEC_WXW) { 425 /* 426 FMV.D.X 427 */ 428 csBundle(0).srcType(0) := SrcType.reg 429 csBundle(0).srcType(1) := SrcType.imm 430 csBundle(0).lsrc(1) := 0.U 431 csBundle(0).ldest := FP_TMP_REG_MV.U 432 csBundle(0).fuType := FuType.i2f.U 433 csBundle(0).rfWen := false.B 434 csBundle(0).fpWen := true.B 435 csBundle(0).vecWen := false.B 436 csBundle(0).fpu.isAddSub := false.B 437 csBundle(0).fpu.typeTagIn := FPU.D 438 csBundle(0).fpu.typeTagOut := FPU.D 439 csBundle(0).fpu.fromInt := true.B 440 csBundle(0).fpu.wflags := false.B 441 csBundle(0).fpu.fpWen := true.B 442 csBundle(0).fpu.div := false.B 443 csBundle(0).fpu.sqrt := false.B 444 csBundle(0).fpu.fcvt := false.B 445 446 for (i <- 0 until MAX_VLMUL / 2) { 447 csBundle(2 * i + 1).srcType(0) := SrcType.fp 448 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 449 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 450 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 451 csBundle(2 * i + 1).ldest := dest + (2 * i).U 452 csBundle(2 * i + 1).uopIdx := (2 * i).U 453 csBundle(2 * i + 2).srcType(0) := SrcType.fp 454 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 455 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 456 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 457 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 458 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 459 } 460 } 461 is(UopSplitType.VEC_WVV) { 462 for (i <- 0 until MAX_VLMUL / 2) { 463 464 csBundle(2 * i).lsrc(0) := src1 + i.U 465 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 466 csBundle(2 * i).lsrc(2) := dest + i.U 467 csBundle(2 * i).ldest := dest + i.U 468 csBundle(2 * i).uopIdx := (2 * i).U 469 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 470 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 471 csBundle(2 * i + 1).lsrc(2) := dest + i.U 472 csBundle(2 * i + 1).ldest := dest + i.U 473 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 474 } 475 } 476 is(UopSplitType.VEC_WXV) { 477 /* 478 FMV.D.X 479 */ 480 csBundle(0).srcType(0) := SrcType.reg 481 csBundle(0).srcType(1) := SrcType.imm 482 csBundle(0).lsrc(1) := 0.U 483 csBundle(0).ldest := FP_TMP_REG_MV.U 484 csBundle(0).fuType := FuType.i2f.U 485 csBundle(0).rfWen := false.B 486 csBundle(0).fpWen := true.B 487 csBundle(0).vecWen := false.B 488 csBundle(0).fpu.isAddSub := false.B 489 csBundle(0).fpu.typeTagIn := FPU.D 490 csBundle(0).fpu.typeTagOut := FPU.D 491 csBundle(0).fpu.fromInt := true.B 492 csBundle(0).fpu.wflags := false.B 493 csBundle(0).fpu.fpWen := true.B 494 csBundle(0).fpu.div := false.B 495 csBundle(0).fpu.sqrt := false.B 496 csBundle(0).fpu.fcvt := false.B 497 498 for (i <- 0 until MAX_VLMUL / 2) { 499 csBundle(2 * i + 1).srcType(0) := SrcType.fp 500 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 501 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 502 csBundle(2 * i + 1).lsrc(2) := dest + i.U 503 csBundle(2 * i + 1).ldest := dest + i.U 504 csBundle(2 * i + 1).uopIdx := (2 * i).U 505 csBundle(2 * i + 2).srcType(0) := SrcType.fp 506 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 507 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 508 csBundle(2 * i + 2).lsrc(2) := dest + i.U 509 csBundle(2 * i + 2).ldest := dest + i.U 510 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 511 } 512 } 513 is(UopSplitType.VEC_VVM) { 514 csBundle(0).lsrc(2) := dest 515 csBundle(0).ldest := dest 516 csBundle(0).uopIdx := 0.U 517 for (i <- 1 until MAX_VLMUL) { 518 csBundle(i).lsrc(0) := src1 + i.U 519 csBundle(i).lsrc(1) := src2 + i.U 520 csBundle(i).lsrc(2) := dest 521 csBundle(i).ldest := dest 522 csBundle(i).uopIdx := i.U 523 } 524 csBundle(numOfUop - 1.U).ldest := dest 525 } 526 is(UopSplitType.VEC_VXM) { 527 /* 528 FMV.D.X 529 */ 530 csBundle(0).srcType(0) := SrcType.reg 531 csBundle(0).srcType(1) := SrcType.imm 532 csBundle(0).lsrc(1) := 0.U 533 csBundle(0).ldest := FP_TMP_REG_MV.U 534 csBundle(0).fuType := FuType.i2f.U 535 csBundle(0).rfWen := false.B 536 csBundle(0).fpWen := true.B 537 csBundle(0).vecWen := false.B 538 csBundle(0).fpu.isAddSub := false.B 539 csBundle(0).fpu.typeTagIn := FPU.D 540 csBundle(0).fpu.typeTagOut := FPU.D 541 csBundle(0).fpu.fromInt := true.B 542 csBundle(0).fpu.wflags := false.B 543 csBundle(0).fpu.fpWen := true.B 544 csBundle(0).fpu.div := false.B 545 csBundle(0).fpu.sqrt := false.B 546 csBundle(0).fpu.fcvt := false.B 547 //LMUL 548 csBundle(1).srcType(0) := SrcType.fp 549 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 550 csBundle(1).lsrc(2) := dest 551 csBundle(1).ldest := dest 552 csBundle(1).uopIdx := 0.U 553 for (i <- 1 until MAX_VLMUL) { 554 csBundle(i + 1).srcType(0) := SrcType.fp 555 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 556 csBundle(i + 1).lsrc(1) := src2 + i.U 557 csBundle(i + 1).lsrc(2) := dest 558 csBundle(i + 1).ldest := dest 559 csBundle(i + 1).uopIdx := i.U 560 } 561 csBundle(numOfUop - 1.U).ldest := dest 562 } 563 is(UopSplitType.VEC_SLIDE1UP) { 564 /* 565 FMV.D.X 566 */ 567 csBundle(0).srcType(0) := SrcType.reg 568 csBundle(0).srcType(1) := SrcType.imm 569 csBundle(0).lsrc(1) := 0.U 570 csBundle(0).ldest := FP_TMP_REG_MV.U 571 csBundle(0).fuType := FuType.i2f.U 572 csBundle(0).rfWen := false.B 573 csBundle(0).fpWen := true.B 574 csBundle(0).vecWen := false.B 575 csBundle(0).fpu.isAddSub := false.B 576 csBundle(0).fpu.typeTagIn := FPU.D 577 csBundle(0).fpu.typeTagOut := FPU.D 578 csBundle(0).fpu.fromInt := true.B 579 csBundle(0).fpu.wflags := false.B 580 csBundle(0).fpu.fpWen := true.B 581 csBundle(0).fpu.div := false.B 582 csBundle(0).fpu.sqrt := false.B 583 csBundle(0).fpu.fcvt := false.B 584 //LMUL 585 csBundle(1).srcType(0) := SrcType.fp 586 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 587 csBundle(1).lsrc(2) := dest 588 csBundle(1).ldest := dest 589 csBundle(1).uopIdx := 0.U 590 for (i <- 1 until MAX_VLMUL) { 591 csBundle(i + 1).srcType(0) := SrcType.vp 592 csBundle(i + 1).lsrc(0) := src2 + (i - 1).U 593 csBundle(i + 1).lsrc(1) := src2 + i.U 594 csBundle(i + 1).lsrc(2) := dest + i.U 595 csBundle(i + 1).ldest := dest + i.U 596 csBundle(i + 1).uopIdx := i.U 597 } 598 } 599 is(UopSplitType.VEC_FSLIDE1UP) { 600 //LMUL 601 csBundle(0).srcType(0) := SrcType.fp 602 csBundle(0).lsrc(0) := src1 603 csBundle(0).lsrc(1) := src2 604 csBundle(0).lsrc(2) := dest 605 csBundle(0).ldest := dest 606 csBundle(0).uopIdx := 0.U 607 for (i <- 1 until MAX_VLMUL) { 608 csBundle(i).srcType(0) := SrcType.vp 609 csBundle(i).lsrc(0) := src2 + (i - 1).U 610 csBundle(i).lsrc(1) := src2 + i.U 611 csBundle(i).lsrc(2) := dest + i.U 612 csBundle(i).ldest := dest + i.U 613 csBundle(i).uopIdx := i.U 614 } 615 } 616 is(UopSplitType.VEC_SLIDE1DOWN) { // lmul+lmul = 16 617 /* 618 FMV.D.X 619 */ 620 csBundle(0).srcType(0) := SrcType.reg 621 csBundle(0).srcType(1) := SrcType.imm 622 csBundle(0).lsrc(1) := 0.U 623 csBundle(0).ldest := FP_TMP_REG_MV.U 624 csBundle(0).fuType := FuType.i2f.U 625 csBundle(0).rfWen := false.B 626 csBundle(0).fpWen := true.B 627 csBundle(0).vecWen := false.B 628 csBundle(0).fpu.isAddSub := false.B 629 csBundle(0).fpu.typeTagIn := FPU.D 630 csBundle(0).fpu.typeTagOut := FPU.D 631 csBundle(0).fpu.fromInt := true.B 632 csBundle(0).fpu.wflags := false.B 633 csBundle(0).fpu.fpWen := true.B 634 csBundle(0).fpu.div := false.B 635 csBundle(0).fpu.sqrt := false.B 636 csBundle(0).fpu.fcvt := false.B 637 //LMUL 638 for (i <- 0 until MAX_VLMUL) { 639 csBundle(2 * i + 1).srcType(0) := SrcType.vp 640 csBundle(2 * i + 1).srcType(1) := SrcType.vp 641 csBundle(2 * i + 1).lsrc(0) := src2 + (i + 1).U 642 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 643 csBundle(2 * i + 1).lsrc(2) := dest + i.U 644 csBundle(2 * i + 1).ldest := VECTOR_TMP_REG_LMUL.U 645 csBundle(2 * i + 1).uopIdx := (2 * i).U 646 if (2 * i + 2 < MAX_VLMUL * 2) { 647 csBundle(2 * i + 2).srcType(0) := SrcType.fp 648 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 649 // csBundle(2 * i + 2).lsrc(1) := src2 + i.U // DontCare 650 csBundle(2 * i + 2).lsrc(2) := VECTOR_TMP_REG_LMUL.U 651 csBundle(2 * i + 2).ldest := dest + i.U 652 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 653 } 654 } 655 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 656 csBundle(numOfUop - 1.U).lsrc(0) := FP_TMP_REG_MV.U 657 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 658 } 659 is(UopSplitType.VEC_FSLIDE1DOWN) { 660 //LMUL 661 for (i <- 0 until MAX_VLMUL) { 662 csBundle(2 * i).srcType(0) := SrcType.vp 663 csBundle(2 * i).srcType(1) := SrcType.vp 664 csBundle(2 * i).lsrc(0) := src2 + (i + 1).U 665 csBundle(2 * i).lsrc(1) := src2 + i.U 666 csBundle(2 * i).lsrc(2) := dest + i.U 667 csBundle(2 * i).ldest := VECTOR_TMP_REG_LMUL.U 668 csBundle(2 * i).uopIdx := (2 * i).U 669 csBundle(2 * i + 1).srcType(0) := SrcType.fp 670 csBundle(2 * i + 1).lsrc(0) := src1 671 csBundle(2 * i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 672 csBundle(2 * i + 1).ldest := dest + i.U 673 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 674 } 675 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 676 csBundle(numOfUop - 1.U).lsrc(0) := src1 677 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 678 } 679 is(UopSplitType.VEC_VRED) { 680 when(simple.io.enq.vtype.vlmul === "b001".U) { 681 csBundle(0).srcType(2) := SrcType.DC 682 csBundle(0).lsrc(0) := src2 + 1.U 683 csBundle(0).lsrc(1) := src2 684 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 685 csBundle(0).uopIdx := 0.U 686 } 687 when(simple.io.enq.vtype.vlmul === "b010".U) { 688 csBundle(0).srcType(2) := SrcType.DC 689 csBundle(0).lsrc(0) := src2 + 1.U 690 csBundle(0).lsrc(1) := src2 691 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 692 csBundle(0).uopIdx := 0.U 693 694 csBundle(1).srcType(2) := SrcType.DC 695 csBundle(1).lsrc(0) := src2 + 3.U 696 csBundle(1).lsrc(1) := src2 + 2.U 697 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 698 csBundle(1).uopIdx := 1.U 699 700 csBundle(2).srcType(2) := SrcType.DC 701 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 702 csBundle(2).lsrc(1) := VECTOR_TMP_REG_LMUL.U 703 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 704 csBundle(2).uopIdx := 2.U 705 } 706 when(simple.io.enq.vtype.vlmul === "b011".U) { 707 for (i <- 0 until MAX_VLMUL) { 708 if (i < MAX_VLMUL - MAX_VLMUL / 2) { 709 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 710 csBundle(i).lsrc(1) := src2 + (i * 2).U 711 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 712 } else if (i < MAX_VLMUL - MAX_VLMUL / 4) { 713 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL / 2) * 2 + 1).U 714 csBundle(i).lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL / 2) * 2).U 715 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 716 } else if (i < MAX_VLMUL - MAX_VLMUL / 8) { 717 csBundle(6).lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 718 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 719 csBundle(6).ldest := (VECTOR_TMP_REG_LMUL + 6).U 720 } 721 csBundle(i).srcType(2) := SrcType.DC 722 csBundle(i).uopIdx := i.U 723 } 724 } 725 when(simple.io.enq.vtype.vlmul.orR()) { 726 csBundle(numOfUop - 1.U).srcType(2) := SrcType.vp 727 csBundle(numOfUop - 1.U).lsrc(0) := src1 728 csBundle(numOfUop - 1.U).lsrc(1) := VECTOR_TMP_REG_LMUL.U + numOfUop - 2.U 729 csBundle(numOfUop - 1.U).lsrc(2) := dest 730 csBundle(numOfUop - 1.U).ldest := dest 731 csBundle(numOfUop - 1.U).uopIdx := numOfUop - 1.U 732 } 733 } 734 735 is(UopSplitType.VEC_SLIDEUP) { 736 // FMV.D.X 737 csBundle(0).srcType(0) := SrcType.reg 738 csBundle(0).srcType(1) := SrcType.imm 739 csBundle(0).lsrc(1) := 0.U 740 csBundle(0).ldest := FP_TMP_REG_MV.U 741 csBundle(0).fuType := FuType.i2f.U 742 csBundle(0).rfWen := false.B 743 csBundle(0).fpWen := true.B 744 csBundle(0).vecWen := false.B 745 csBundle(0).fpu.isAddSub := false.B 746 csBundle(0).fpu.typeTagIn := FPU.D 747 csBundle(0).fpu.typeTagOut := FPU.D 748 csBundle(0).fpu.fromInt := true.B 749 csBundle(0).fpu.wflags := false.B 750 csBundle(0).fpu.fpWen := true.B 751 csBundle(0).fpu.div := false.B 752 csBundle(0).fpu.sqrt := false.B 753 csBundle(0).fpu.fcvt := false.B 754 // LMUL 755 for (i <- 0 until MAX_VLMUL) 756 for (j <- 0 to i) { 757 val old_vd = if (j == 0) { 758 dest + i.U 759 } else (VECTOR_TMP_REG_LMUL + j - 1).U 760 val vd = if (j == i) { 761 dest + i.U 762 } else (VECTOR_TMP_REG_LMUL + j).U 763 csBundle(i * (i + 1) / 2 + j + 1).srcType(0) := SrcType.fp 764 csBundle(i * (i + 1) / 2 + j + 1).lsrc(0) := FP_TMP_REG_MV.U 765 csBundle(i * (i + 1) / 2 + j + 1).lsrc(1) := src2 + j.U 766 csBundle(i * (i + 1) / 2 + j + 1).lsrc(2) := old_vd 767 csBundle(i * (i + 1) / 2 + j + 1).ldest := vd 768 csBundle(i * (i + 1) / 2 + j + 1).uopIdx := (i * (i + 1) / 2 + j).U 769 } 770 } 771 772 is(UopSplitType.VEC_ISLIDEUP) { 773 // LMUL 774 for (i <- 0 until MAX_VLMUL) 775 for (j <- 0 to i) { 776 val old_vd = if (j == 0) { 777 dest + i.U 778 } else (VECTOR_TMP_REG_LMUL + j - 1).U 779 val vd = if (j == i) { 780 dest + i.U 781 } else (VECTOR_TMP_REG_LMUL + j).U 782 csBundle(i * (i + 1) / 2 + j).lsrc(1) := src2 + j.U 783 csBundle(i * (i + 1) / 2 + j).lsrc(2) := old_vd 784 csBundle(i * (i + 1) / 2 + j).ldest := vd 785 csBundle(i * (i + 1) / 2 + j).uopIdx := (i * (i + 1) / 2 + j).U 786 } 787 } 788 789 is(UopSplitType.VEC_SLIDEDOWN) { 790 // FMV.D.X 791 csBundle(0).srcType(0) := SrcType.reg 792 csBundle(0).srcType(1) := SrcType.imm 793 csBundle(0).lsrc(1) := 0.U 794 csBundle(0).ldest := FP_TMP_REG_MV.U 795 csBundle(0).fuType := FuType.i2f.U 796 csBundle(0).rfWen := false.B 797 csBundle(0).fpWen := true.B 798 csBundle(0).vecWen := false.B 799 csBundle(0).fpu.isAddSub := false.B 800 csBundle(0).fpu.typeTagIn := FPU.D 801 csBundle(0).fpu.typeTagOut := FPU.D 802 csBundle(0).fpu.fromInt := true.B 803 csBundle(0).fpu.wflags := false.B 804 csBundle(0).fpu.fpWen := true.B 805 csBundle(0).fpu.div := false.B 806 csBundle(0).fpu.sqrt := false.B 807 csBundle(0).fpu.fcvt := false.B 808 // LMUL 809 for (i <- 0 until MAX_VLMUL) 810 for (j <- (0 to i).reverse) { 811 when(i.U < lmul) { 812 val old_vd = if (j == 0) { 813 dest + lmul - 1.U - i.U 814 } else (VECTOR_TMP_REG_LMUL + j - 1).U 815 val vd = if (j == i) { 816 dest + lmul - 1.U - i.U 817 } else (VECTOR_TMP_REG_LMUL + j).U 818 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).srcType(0) := SrcType.fp 819 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(0) := FP_TMP_REG_MV.U 820 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(1) := src2 + lmul - 1.U - j.U 821 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(2) := old_vd 822 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).ldest := vd 823 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).uopIdx := numOfUop - (i * (i + 1) / 2 + i - j + 2).U 824 } 825 } 826 } 827 828 is(UopSplitType.VEC_ISLIDEDOWN) { 829 // LMUL 830 for (i <- 0 until MAX_VLMUL) 831 for (j <- (0 to i).reverse) { 832 when(i.U < lmul) { 833 val old_vd = if (j == 0) { 834 dest + lmul - 1.U - i.U 835 } else (VECTOR_TMP_REG_LMUL + j - 1).U 836 val vd = if (j == i) { 837 dest + lmul - 1.U - i.U 838 } else (VECTOR_TMP_REG_LMUL + j).U 839 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(1) := src2 + lmul - 1.U - j.U 840 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(2) := old_vd 841 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).ldest := vd 842 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).uopIdx := numOfUop - (i * (i + 1) / 2 + i - j + 1).U 843 } 844 } 845 } 846 847 is(UopSplitType.VEC_M0X) { 848 // LMUL 849 for (i <- 0 until MAX_VLMUL) { 850 val srcType0 = if (i == 0) SrcType.DC else SrcType.vp 851 val ldest = (VECTOR_TMP_REG_LMUL + i).U 852 csBundle(i).srcType(0) := srcType0 853 csBundle(i).srcType(1) := SrcType.vp 854 csBundle(i).rfWen := false.B 855 csBundle(i).vecWen := true.B 856 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 857 csBundle(i).lsrc(1) := src2 858 // csBundle(i).lsrc(2) := dest + i.U DontCare 859 csBundle(i).ldest := ldest 860 csBundle(i).uopIdx := i.U 861 } 862 csBundle(lmul - 1.U).vecWen := false.B 863 csBundle(lmul - 1.U).fpWen := true.B 864 csBundle(lmul - 1.U).ldest := FP_TMP_REG_MV.U 865 // FMV_X_D 866 csBundle(lmul).srcType(0) := SrcType.fp 867 csBundle(lmul).srcType(1) := SrcType.imm 868 csBundle(lmul).lsrc(0) := FP_TMP_REG_MV.U 869 csBundle(lmul).lsrc(1) := 0.U 870 csBundle(lmul).ldest := dest 871 csBundle(lmul).fuType := FuType.fmisc.U 872 csBundle(lmul).rfWen := true.B 873 csBundle(lmul).fpWen := false.B 874 csBundle(lmul).vecWen := false.B 875 csBundle(lmul).fpu.isAddSub := false.B 876 csBundle(lmul).fpu.typeTagIn := FPU.D 877 csBundle(lmul).fpu.typeTagOut := FPU.D 878 csBundle(lmul).fpu.fromInt := false.B 879 csBundle(lmul).fpu.wflags := false.B 880 csBundle(lmul).fpu.fpWen := false.B 881 csBundle(lmul).fpu.div := false.B 882 csBundle(lmul).fpu.sqrt := false.B 883 csBundle(lmul).fpu.fcvt := false.B 884 } 885 886 is(UopSplitType.VEC_MVV) { 887 // LMUL 888 for (i <- 0 until MAX_VLMUL) { 889 val srcType0 = if (i == 0) SrcType.DC else SrcType.vp 890 csBundle(i * 2 + 0).srcType(0) := srcType0 891 csBundle(i * 2 + 0).srcType(1) := SrcType.vp 892 csBundle(i * 2 + 0).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 893 csBundle(i * 2 + 0).lsrc(1) := src2 894 csBundle(i * 2 + 0).lsrc(2) := dest + i.U 895 csBundle(i * 2 + 0).ldest := dest + i.U 896 csBundle(i * 2 + 0).uopIdx := (i * 2 + 0).U 897 898 csBundle(i * 2 + 1).srcType(0) := srcType0 899 csBundle(i * 2 + 1).srcType(1) := SrcType.vp 900 csBundle(i * 2 + 1).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 901 csBundle(i * 2 + 1).lsrc(1) := src2 902 // csBundle(i).lsrc(2) := dest + i.U DontCare 903 csBundle(i * 2 + 1).ldest := (VECTOR_TMP_REG_LMUL + i).U 904 csBundle(i * 2 + 1).uopIdx := (i * 2 + 1).U 905 } 906 } 907 908 is(UopSplitType.VEC_M0X_VFIRST) { 909 // LMUL 910 csBundle(0).rfWen := false.B 911 csBundle(0).fpWen := true.B 912 csBundle(0).ldest := FP_TMP_REG_MV.U 913 // FMV_X_D 914 csBundle(1).srcType(0) := SrcType.fp 915 csBundle(1).srcType(1) := SrcType.imm 916 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 917 csBundle(1).lsrc(1) := 0.U 918 csBundle(1).ldest := dest 919 csBundle(1).fuType := FuType.fmisc.U 920 csBundle(1).rfWen := true.B 921 csBundle(1).fpWen := false.B 922 csBundle(1).vecWen := false.B 923 csBundle(1).fpu.isAddSub := false.B 924 csBundle(1).fpu.typeTagIn := FPU.D 925 csBundle(1).fpu.typeTagOut := FPU.D 926 csBundle(1).fpu.fromInt := false.B 927 csBundle(1).fpu.wflags := false.B 928 csBundle(1).fpu.fpWen := false.B 929 csBundle(1).fpu.div := false.B 930 csBundle(1).fpu.sqrt := false.B 931 csBundle(1).fpu.fcvt := false.B 932 } 933 is(UopSplitType.VEC_VWW) { 934 for (i <- 0 until MAX_VLMUL*2) { 935 when(i.U < lmul){ 936 csBundle(i).srcType(2) := SrcType.DC 937 csBundle(i).lsrc(0) := src2 + i.U 938 csBundle(i).lsrc(1) := src2 + i.U 939 // csBundle(i).lsrc(2) := dest + (2 * i).U 940 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 941 csBundle(i).uopIdx := i.U 942 } otherwise { 943 csBundle(i).srcType(2) := SrcType.DC 944 csBundle(i).lsrc(0) := VECTOR_TMP_REG_LMUL.U + Cat((i.U-lmul),0.U(1.W)) + 1.U 945 csBundle(i).lsrc(1) := VECTOR_TMP_REG_LMUL.U + Cat((i.U-lmul),0.U(1.W)) 946 // csBundle(i).lsrc(2) := dest + (2 * i).U 947 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 948 csBundle(i).uopIdx := i.U 949 } 950 csBundle(numOfUop-1.U).srcType(2) := SrcType.vp 951 csBundle(numOfUop-1.U).lsrc(0) := src1 952 csBundle(numOfUop-1.U).lsrc(2) := dest 953 csBundle(numOfUop-1.U).ldest := dest 954 } 955 } 956 is(UopSplitType.VEC_RGATHER) { 957 def genCsBundle_VEC_RGATHER(len:Int): Unit ={ 958 for (i <- 0 until len) 959 for (j <- 0 until len) { 960 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 961 // csBundle(i * len + j).srcType(1) := SrcType.vp 962 // csBundle(i * len + j).srcType(2) := SrcType.vp 963 csBundle(i * len + j).lsrc(0) := src1 + i.U 964 csBundle(i * len + j).lsrc(1) := src2 + j.U 965 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j - 1).U 966 csBundle(i * len + j).lsrc(2) := vd_old 967 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 968 csBundle(i * len + j).ldest := vd 969 csBundle(i * len + j).uopIdx := (i * len + j).U 970 } 971 } 972 switch(simple.io.enq.vtype.vlmul) { 973 is("b001".U ){ 974 genCsBundle_VEC_RGATHER(2) 975 } 976 is("b010".U ){ 977 genCsBundle_VEC_RGATHER(4) 978 } 979 is("b011".U ){ 980 genCsBundle_VEC_RGATHER(8) 981 } 982 } 983 } 984 is(UopSplitType.VEC_RGATHER_VX) { 985 def genCsBundle_RGATHER_VX(len:Int): Unit ={ 986 for (i <- 0 until len) 987 for (j <- 0 until len) { 988 csBundle(i * len + j + 1).srcType(0) := SrcType.fp 989 // csBundle(i * len + j + 1).srcType(1) := SrcType.vp 990 // csBundle(i * len + j + 1).srcType(2) := SrcType.vp 991 csBundle(i * len + j + 1).lsrc(0) := FP_TMP_REG_MV.U 992 csBundle(i * len + j + 1).lsrc(1) := src2 + j.U 993 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j - 1).U 994 csBundle(i * len + j + 1).lsrc(2) := vd_old 995 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 996 csBundle(i * len + j + 1).ldest := vd 997 csBundle(i * len + j + 1).uopIdx := (i * len + j).U 998 } 999 } 1000 // FMV.D.X 1001 csBundle(0).srcType(0) := SrcType.reg 1002 csBundle(0).srcType(1) := SrcType.imm 1003 csBundle(0).lsrc(1) := 0.U 1004 csBundle(0).ldest := FP_TMP_REG_MV.U 1005 csBundle(0).fuType := FuType.i2f.U 1006 csBundle(0).rfWen := false.B 1007 csBundle(0).fpWen := true.B 1008 csBundle(0).vecWen := false.B 1009 csBundle(0).fpu.isAddSub := false.B 1010 csBundle(0).fpu.typeTagIn := FPU.D 1011 csBundle(0).fpu.typeTagOut := FPU.D 1012 csBundle(0).fpu.fromInt := true.B 1013 csBundle(0).fpu.wflags := false.B 1014 csBundle(0).fpu.fpWen := true.B 1015 csBundle(0).fpu.div := false.B 1016 csBundle(0).fpu.sqrt := false.B 1017 csBundle(0).fpu.fcvt := false.B 1018 switch(simple.io.enq.vtype.vlmul) { 1019 is("b000".U ){ 1020 genCsBundle_RGATHER_VX(1) 1021 } 1022 is("b001".U ){ 1023 genCsBundle_RGATHER_VX(2) 1024 } 1025 is("b010".U ){ 1026 genCsBundle_RGATHER_VX(4) 1027 } 1028 is("b011".U ){ 1029 genCsBundle_RGATHER_VX(8) 1030 } 1031 } 1032 } 1033 is(UopSplitType.VEC_RGATHEREI16) { 1034 def genCsBundle_VEC_RGATHEREI16_SEW8(len:Int): Unit ={ 1035 for (i <- 0 until len) 1036 for (j <- 0 until len) { 1037 val vd_old0 = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j*2-1).U 1038 val vd0 = (VECTOR_TMP_REG_LMUL + j*2 ).U 1039 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 1040 // csBundle(i * len + j).srcType(1) := SrcType.vp 1041 // csBundle(i * len + j).srcType(2) := SrcType.vp 1042 csBundle((i * len + j)*2+0).lsrc(0) := src1 + (i*2+0).U 1043 csBundle((i * len + j)*2+0).lsrc(1) := src2 + j.U 1044 csBundle((i * len + j)*2+0).lsrc(2) := vd_old0 1045 csBundle((i * len + j)*2+0).ldest := vd0 1046 csBundle((i * len + j)*2+0).uopIdx := ((i * len + j)*2+0).U 1047 val vd_old1 = (VECTOR_TMP_REG_LMUL + j*2).U 1048 val vd1 = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j*2+1 ).U 1049 csBundle((i * len + j)*2+1).lsrc(0) := src1 + (i*2+1).U 1050 csBundle((i * len + j)*2+1).lsrc(1) := src2 + j.U 1051 csBundle((i * len + j)*2+1).lsrc(2) := vd_old1 1052 csBundle((i * len + j)*2+1).ldest := vd1 1053 csBundle((i * len + j)*2+1).uopIdx := ((i * len + j)*2+1).U 1054 } 1055 } 1056 def genCsBundle_VEC_RGATHEREI16(len:Int): Unit ={ 1057 for (i <- 0 until len) 1058 for (j <- 0 until len) { 1059 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j-1).U 1060 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 1061 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 1062 // csBundle(i * len + j).srcType(1) := SrcType.vp 1063 // csBundle(i * len + j).srcType(2) := SrcType.vp 1064 csBundle(i * len + j).lsrc(0) := src1 + i.U 1065 csBundle(i * len + j).lsrc(1) := src2 + j.U 1066 csBundle(i * len + j).lsrc(2) := vd_old 1067 csBundle(i * len + j).ldest := vd 1068 csBundle(i * len + j).uopIdx := (i * len + j).U 1069 } 1070 } 1071 switch(simple.io.enq.vtype.vlmul) { 1072 is("b000".U ){ 1073 when(!simple.io.enq.vtype.vsew.orR){ 1074 genCsBundle_VEC_RGATHEREI16_SEW8(1) 1075 } .otherwise{ 1076 genCsBundle_VEC_RGATHEREI16(1) 1077 } 1078 } 1079 is("b001".U) { 1080 when(!simple.io.enq.vtype.vsew.orR) { 1081 genCsBundle_VEC_RGATHEREI16_SEW8(2) 1082 }.otherwise { 1083 genCsBundle_VEC_RGATHEREI16(2) 1084 } 1085 } 1086 is("b010".U) { 1087 when(!simple.io.enq.vtype.vsew.orR) { 1088 genCsBundle_VEC_RGATHEREI16_SEW8(4) 1089 }.otherwise { 1090 genCsBundle_VEC_RGATHEREI16(4) 1091 } 1092 } 1093 is("b011".U) { 1094 genCsBundle_VEC_RGATHEREI16(8) 1095 } 1096 } 1097 } 1098 is(UopSplitType.VEC_COMPRESS) { 1099 def genCsBundle_VEC_COMPRESS(len:Int): Unit ={ 1100 for (i <- 0 until len){ 1101 val jlen = if (i == len-1) i+1 else i+2 1102 for (j <- 0 until jlen) { 1103 val vd_old = if(i==j) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j + 1).U 1104 val vd = if(i==len-1) (dest + j.U) else{ 1105 if (j == i+1) VECTOR_TMP_REG_LMUL.U else (VECTOR_TMP_REG_LMUL + j + 1).U 1106 } 1107 val src23Type = if (j == i+1) DontCare else SrcType.vp 1108 csBundle(i*(i+3)/2 + j).srcType(0) := SrcType.vp 1109 csBundle(i*(i+3)/2 + j).srcType(1) := src23Type 1110 csBundle(i*(i+3)/2 + j).srcType(2) := src23Type 1111 csBundle(i*(i+3)/2 + j).lsrc(0) := src1 1112 csBundle(i*(i+3)/2 + j).lsrc(1) := src2 + i.U 1113 csBundle(i*(i+3)/2 + j).lsrc(2) := vd_old 1114 // csBundle(i*(i+3)/2 + j).lsrc(3) := VECTOR_TMP_REG_LMUL.U 1115 csBundle(i*(i+3)/2 + j).ldest := vd 1116 csBundle(i*(i+3)/2 + j).uopIdx := (i*(i+3)/2 + j).U 1117 } 1118 } 1119 } 1120 switch(simple.io.enq.vtype.vlmul) { 1121 is("b001".U ){ 1122 genCsBundle_VEC_COMPRESS(2) 1123 } 1124 is("b010".U ){ 1125 genCsBundle_VEC_COMPRESS(4) 1126 } 1127 is("b011".U ){ 1128 genCsBundle_VEC_COMPRESS(8) 1129 } 1130 } 1131 } 1132 is(UopSplitType.VEC_US_LD) { 1133 /* 1134 FMV.D.X 1135 */ 1136 csBundle(0).srcType(0) := SrcType.reg 1137 csBundle(0).srcType(1) := SrcType.imm 1138 csBundle(0).lsrc(1) := 0.U 1139 csBundle(0).ldest := FP_TMP_REG_MV.U 1140 csBundle(0).fuType := FuType.i2f.U 1141 csBundle(0).rfWen := false.B 1142 csBundle(0).fpWen := true.B 1143 csBundle(0).vecWen := false.B 1144 csBundle(0).fpu.isAddSub := false.B 1145 csBundle(0).fpu.typeTagIn := FPU.D 1146 csBundle(0).fpu.typeTagOut := FPU.D 1147 csBundle(0).fpu.fromInt := true.B 1148 csBundle(0).fpu.wflags := false.B 1149 csBundle(0).fpu.fpWen := true.B 1150 csBundle(0).fpu.div := false.B 1151 csBundle(0).fpu.sqrt := false.B 1152 csBundle(0).fpu.fcvt := false.B 1153 //LMUL 1154 for (i <- 0 until MAX_VLMUL) { 1155 csBundle(i + 1).srcType(0) := SrcType.fp 1156 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 1157 csBundle(i + 1).ldest := dest + i.U 1158 csBundle(i + 1).uopIdx := i.U 1159 } 1160 } 1161 } 1162 1163 //uops dispatch 1164 val s_normal :: s_ext :: Nil = Enum(2) 1165 val state = RegInit(s_normal) 1166 val state_next = WireDefault(state) 1167 val uopRes = RegInit(0.U) 1168 1169 //readyFromRename Counter 1170 val readyCounter = PriorityMuxDefault(io.readyFromRename.map(x => !x).zip((0 to (RenameWidth - 1)).map(_.U)), RenameWidth.U) 1171 1172 switch(state) { 1173 is(s_normal) { 1174 state_next := Mux(io.validFromIBuf(0) && (numOfUop > readyCounter) && (readyCounter =/= 0.U), s_ext, s_normal) 1175 } 1176 is(s_ext) { 1177 state_next := Mux(io.validFromIBuf(0) && (uopRes > readyCounter), s_ext, s_normal) 1178 } 1179 } 1180 1181 state := state_next 1182 1183 val uopRes0 = Mux(state === s_normal, numOfUop, uopRes) 1184 val uopResJudge = Mux(state === s_normal, 1185 io.validFromIBuf(0) && (readyCounter =/= 0.U) && (uopRes0 > readyCounter), 1186 io.validFromIBuf(0) && (uopRes0 > readyCounter)) 1187 uopRes := Mux(uopResJudge, uopRes0 - readyCounter, 0.U) 1188 1189 for(i <- 0 until RenameWidth) { 1190 decodedInsts(i) := MuxCase(csBundle(i), Seq( 1191 (state === s_normal) -> csBundle(i), 1192 (state === s_ext) -> Mux((i.U + numOfUop -uopRes) < maxUopSize.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxUopSize - 1)) 1193 )) 1194 } 1195 1196 1197 val validSimple = Wire(Vec(DecodeWidth - 1, Bool())) 1198 validSimple.zip(io.validFromIBuf.drop(1).zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 1199 val notInf = Wire(Vec(DecodeWidth - 1, Bool())) 1200 notInf.zip(io.validFromIBuf.drop(1).zip(validSimple)).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 1201 val notInfVec = Wire(Vec(DecodeWidth, Bool())) 1202 notInfVec.drop(1).zip(0 until DecodeWidth - 1).map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 1203 notInfVec(0) := true.B 1204 1205 complexNum := Mux(io.validFromIBuf(0) && readyCounter.orR , 1206 Mux(uopRes0 > readyCounter, readyCounter, uopRes0), 1207 1.U) 1208 validToRename.zipWithIndex.foreach{ 1209 case(dst, i) => 1210 dst := MuxCase(false.B, Seq( 1211 (io.validFromIBuf(0) && uopRes0 > readyCounter ) -> Mux(readyCounter > i.U, true.B, false.B), 1212 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)), 1213 )) 1214 } 1215 1216 readyToIBuf.zipWithIndex.foreach { 1217 case (dst, i) => 1218 dst := MuxCase(true.B, Seq( 1219 (io.validFromIBuf(0) && uopRes0 > readyCounter) -> false.B, 1220 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> (if (i==0) true.B else Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B)), 1221 )) 1222 } 1223 1224 io.deq.decodedInsts := decodedInsts 1225 io.deq.isVset := isVsetSimple 1226 io.deq.complexNum := complexNum 1227 io.deq.validToRename := validToRename 1228 io.deq.readyToIBuf := readyToIBuf 1229 1230} 1231