1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import xiangshan._ 8import xiangshan.backend.datapath.DataConfig._ 9import xiangshan.backend.datapath.WbConfig.WbConfig 10import xiangshan.backend.decode.{ImmUnion, XDecode} 11import xiangshan.backend.exu.ExeUnitParams 12import xiangshan.backend.fu.FuType 13import xiangshan.backend.issue.{IssueBlockParams, IssueQueueJumpBundle, SchedulerType, StatusArrayDeqRespBundle} 14import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig} 15import xiangshan.backend.rob.RobPtr 16import xiangshan.frontend._ 17import xiangshan.mem.{LqPtr, SqPtr} 18 19object Bundles { 20 21 // frontend -> backend 22 class StaticInst(implicit p: Parameters) extends XSBundle { 23 val instr = UInt(32.W) 24 val pc = UInt(VAddrBits.W) 25 val foldpc = UInt(MemPredPCWidth.W) 26 val exceptionVec = ExceptionVec() 27 val trigger = new TriggerCf 28 val preDecodeInfo = new PreDecodeInfo 29 val pred_taken = Bool() 30 val crossPageIPFFix = Bool() 31 val ftqPtr = new FtqPtr 32 val ftqOffset = UInt(log2Up(PredictWidth).W) 33 34 def connectCtrlFlow(source: CtrlFlow): Unit = { 35 this.instr := source.instr 36 this.pc := source.pc 37 this.foldpc := source.foldpc 38 this.exceptionVec := source.exceptionVec 39 this.trigger := source.trigger 40 this.preDecodeInfo := source.pd 41 this.pred_taken := source.pred_taken 42 this.crossPageIPFFix := source.crossPageIPFFix 43 this.ftqPtr := source.ftqPtr 44 this.ftqOffset := source.ftqOffset 45 } 46 } 47 48 // StaticInst --[Decode]--> DecodedInst 49 class DecodedInst(implicit p: Parameters) extends XSBundle { 50 def numPSrc = 5 51 def numLSrc = 3 52 // passed from StaticInst 53 val instr = UInt(32.W) 54 val pc = UInt(VAddrBits.W) 55 val foldpc = UInt(MemPredPCWidth.W) 56 val exceptionVec = ExceptionVec() 57 val trigger = new TriggerCf 58 val preDecodeInfo = new PreDecodeInfo 59 val pred_taken = Bool() 60 val crossPageIPFFix = Bool() 61 val ftqPtr = new FtqPtr 62 val ftqOffset = UInt(log2Up(PredictWidth).W) 63 // decoded 64 val srcType = Vec(numLSrc, SrcType()) 65 val lsrc = Vec(numLSrc, UInt(6.W)) 66 val ldest = UInt(6.W) 67 val fuType = FuType() 68 val fuOpType = FuOpType() 69 val rfWen = Bool() 70 val fpWen = Bool() 71 val vecWen = Bool() 72 val isXSTrap = Bool() 73 val waitForward = Bool() // no speculate execution 74 val blockBackward = Bool() 75 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 76 val selImm = SelImm() 77 val imm = UInt(ImmUnion.maxLen.W) 78 val fpu = new FPUCtrlSignals 79 val vpu = new VPUCtrlSignals 80 val isMove = Bool() 81 val uopIdx = UInt(5.W) 82 val vtype = new VType 83 val uopDivType = UopDivType() 84 val isVset = Bool() 85 val firstUop = Bool() 86 val lastUop = Bool() 87 val commitType = CommitType() // Todo: remove it 88 89 private def allSignals = srcType.take(3) ++ Seq(fuType, fuOpType, rfWen, fpWen, vecWen, 90 isXSTrap, waitForward, blockBackward, flushPipe, uopDivType, selImm) 91 92 def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): DecodedInst = { 93 val decoder: Seq[UInt] = ListLookup( 94 inst, XDecode.decodeDefault.map(bitPatToUInt), 95 table.map{ case (pat, pats) => (pat, pats.map(bitPatToUInt)) }.toArray 96 ) 97 allSignals zip decoder foreach { case (s, d) => s := d } 98 this 99 } 100 101 def isSoftPrefetch: Bool = { 102 fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U 103 } 104 105 def connectStaticInst(source: StaticInst): Unit = { 106 for ((name, data) <- this.elements) { 107 if (source.elements.contains(name)) { 108 data := source.elements(name) 109 } 110 } 111 } 112 } 113 114 // DecodedInst --[Rename]--> DynInst 115 class DynInst(implicit p: Parameters) extends XSBundle { 116 def numLSrc = 3 117 // vector inst need vs1, vs2, vd, v0, vl&vtype, 5 psrcs 118 def numPSrc = 5 119 // passed from StaticInst 120 val instr = UInt(32.W) 121 val pc = UInt(VAddrBits.W) 122 val foldpc = UInt(MemPredPCWidth.W) 123 val exceptionVec = ExceptionVec() 124 val trigger = new TriggerCf 125 val preDecodeInfo = new PreDecodeInfo 126 val pred_taken = Bool() 127 val crossPageIPFFix = Bool() 128 val ftqPtr = new FtqPtr 129 val ftqOffset = UInt(log2Up(PredictWidth).W) 130 // passed from DecodedInst 131 val srcType = Vec(numLSrc, SrcType()) 132 val lsrc = Vec(numLSrc, UInt(6.W)) 133 val ldest = UInt(6.W) 134 val fuType = FuType() 135 val fuOpType = FuOpType() 136 val rfWen = Bool() 137 val fpWen = Bool() 138 val vecWen = Bool() 139 val isXSTrap = Bool() 140 val waitForward = Bool() // no speculate execution 141 val blockBackward = Bool() 142 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 143 val selImm = SelImm() 144 val imm = UInt(XLEN.W) // Todo: check if it need minimized 145 val fpu = new FPUCtrlSignals 146 val vpu = new VPUCtrlSignals 147 val isMove = Bool() 148 val uopIdx = UInt(5.W) 149 val vtype = new VType 150 val isVset = Bool() 151 val firstUop = Bool() 152 val lastUop = Bool() 153 val commitType = CommitType() 154 // rename 155 val srcState = Vec(numPSrc, SrcState()) 156 val psrc = Vec(numPSrc, UInt(PhyRegIdxWidth.W)) 157 val pdest = UInt(PhyRegIdxWidth.W) 158 val oldPdest = UInt(PhyRegIdxWidth.W) 159 val robIdx = new RobPtr 160 161 val eliminatedMove = Bool() 162 val debugInfo = new PerfDebugInfo 163 val storeSetHit = Bool() // inst has been allocated an store set 164 val waitForRobIdx = new RobPtr // store set predicted previous store robIdx 165 // Load wait is needed 166 // load inst will not be executed until former store (predicted by mdp) addr calcuated 167 val loadWaitBit = Bool() 168 // If (loadWaitBit && loadWaitStrict), strict load wait is needed 169 // load inst will not be executed until ALL former store addr calcuated 170 val loadWaitStrict = Bool() 171 val ssid = UInt(SSIDWidth.W) 172 // Todo 173 val lqIdx = new LqPtr 174 val sqIdx = new SqPtr 175 // debug module 176 val singleStep = Bool() 177 // schedule 178 val replayInst = Bool() 179 180 def isLUI: Bool = this.fuType === FuType.alu.U && this.selImm === SelImm.IMM_U 181 def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi 182 183 def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush 184 def isSvinval(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.sfence && !flush 185 def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush 186 187 def srcIsReady: Vec[Bool] = { 188 VecInit(this.srcType.zip(this.srcState).map { 189 case (t, s) => SrcType.isNotReg(t) || SrcState.isReady(s) 190 }) 191 } 192 193 def clearExceptions( 194 exceptionBits: Seq[Int] = Seq(), 195 flushPipe : Boolean = false, 196 replayInst : Boolean = false 197 ): DynInst = { 198 this.exceptionVec.zipWithIndex.filterNot(x => exceptionBits.contains(x._2)).foreach(_._1 := false.B) 199 if (!flushPipe) { this.flushPipe := false.B } 200 if (!replayInst) { this.replayInst := false.B } 201 this 202 } 203 204 def asWakeUpBundle: IssueQueueWakeUpBundle = { 205 val wakeup = Output(new IssueQueueWakeUpBundle(pdest.getWidth)) 206 wakeup.rfWen := this.rfWen 207 wakeup.fpWen := this.fpWen 208 wakeup.vecWen := this.vecWen 209 wakeup.pdest := this.pdest 210 wakeup 211 } 212 } 213 214 trait BundleSource { 215 var source = "not exist" 216 } 217 218 class IssueQueueWakeUpBundle(PregIdxWidth: Int) extends Bundle with BundleSource { 219 val rfWen = Bool() 220 val fpWen = Bool() 221 val vecWen = Bool() 222 val pdest = UInt(PregIdxWidth.W) 223 224 /** 225 * @param successor Seq[(psrc, srcType)] 226 * @return Seq[if wakeup psrc] 227 */ 228 def wakeUp(successor: Seq[(UInt, UInt)], valid: Bool): Seq[Bool]= { 229 successor.map { case (thatPsrc, srcType) => 230 val pdestMatch = pdest === thatPsrc 231 pdestMatch && ( 232 SrcType.isFp(srcType) && this.fpWen || 233 SrcType.isXp(srcType) && this.rfWen || 234 SrcType.isVp(srcType) && this.vecWen 235 ) && valid 236 } 237 } 238 } 239 240 object VsewBundle { 241 def apply() = UInt(2.W) // 8/16/32/64 --> 0/1/2/3 242 } 243 244 class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { 245 val vlmul = SInt(3.W) // 1/8~8 --> -3~3 246 val vsew = VsewBundle() 247 val vta = Bool() // 1: agnostic, 0: undisturbed 248 val vma = Bool() // 1: agnostic, 0: undisturbed 249 val vm = Bool() // 0: need v0.t 250 val vill = Bool() 251 // vector load/store 252 val nf = UInt(3.W) 253 val lsumop = UInt(5.W) // lumop or sumop 254 // used for vector index load/store and vrgatherei16.vv 255 val idxEmul = UInt(3.W) 256 } 257 258 // DynInst --[IssueQueue]--> DataPath 259 class IssueQueueIssueBundle( 260 iqParams: IssueBlockParams, 261 exuParams: ExeUnitParams, 262 addrWidth: Int, 263 vaddrBits: Int 264 )(implicit 265 p: Parameters 266 ) extends Bundle { 267 private val rfReadDataCfgSet: Seq[Set[DataConfig]] = exuParams.getRfReadDataCfgSet 268 269 val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec( 270 rfReadDataCfgSet.map((set: Set[DataConfig]) => 271 MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, addrWidth)).toSeq) 272 ) 273 )) 274 val srcType = Vec(exuParams.numRegSrc, SrcType()) // used to select imm or reg data 275 val immType = SelImm() // used to select imm extractor 276 val common = new ExuInput(exuParams) 277 val jmp = if (exuParams.needPc) Some(Flipped(new IssueQueueJumpBundle)) else None 278 val addrOH = UInt(iqParams.numEntries.W) 279 280 def getSource: SchedulerType = exuParams.getWBSource 281 def getIntRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readInt) 282 def getFpRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(x => x.readFp || x.readVec) 283 } 284 285 class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle { 286 val og0resp = Valid(new StatusArrayDeqRespBundle) 287 val og1resp = Valid(new StatusArrayDeqRespBundle) 288 } 289 290 // DataPath --[ExuInput]--> Exu 291 class ExuInput(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 292 val fuType = FuType() 293 val fuOpType = FuOpType() 294 val src = Vec(params.numRegSrc, UInt(params.dataBitsMax.W)) 295 val imm = UInt(XLEN.W) 296 val robIdx = new RobPtr 297 val iqIdx = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet 298 val isFirstIssue = Bool() // Only used by store yet 299 val pdest = UInt(params.wbPregIdxWidth.W) 300 val rfWen = if (params.writeIntRf) Some(Bool()) else None 301 val fpWen = if (params.writeFpRf) Some(Bool()) else None 302 val vecWen = if (params.writeVecRf) Some(Bool()) else None 303 val fpu = if (params.needFPUCtrl) Some(new FPUCtrlSignals) else None 304 val flushPipe = if (params.flushPipe) Some(Bool()) else None 305 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 306 val jalrTarget = if (params.hasJmpFu) Some(UInt(VAddrData().dataWidth.W)) else None 307 val preDecode = if (params.hasPredecode) Some(new PreDecodeInfo) else None 308 val ftqIdx = if (params.needPc || params.replayInst) 309 Some(new FtqPtr) else None 310 val ftqOffset = if (params.needPc || params.replayInst) 311 Some(UInt(log2Up(PredictWidth).W)) else None 312 val predictInfo = if (params.hasPredecode) Some(new Bundle { 313 val target = UInt(VAddrData().dataWidth.W) 314 val taken = Bool() 315 }) else None 316 val sqIdx = if (params.hasMemAddrFu || params.hasStdFu) Some(new SqPtr) else None 317 val lqIdx = if (params.hasMemAddrFu) Some(new LqPtr) else None 318 319 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = { 320 // src is assigned to rfReadData 321 this.fuType := source.common.fuType 322 this.fuOpType := source.common.fuOpType 323 this.imm := source.common.imm 324 this.robIdx := source.common.robIdx 325 this.pdest := source.common.pdest 326 this.isFirstIssue := source.common.isFirstIssue // Only used by mem debug log 327 this.iqIdx := source.common.iqIdx // Only used by mem feedback 328 this.rfWen .foreach(_ := source.common.rfWen.get) 329 this.fpWen .foreach(_ := source.common.fpWen.get) 330 this.vecWen .foreach(_ := source.common.vecWen.get) 331 this.fpu .foreach(_ := source.common.fpu.get) 332 this.flushPipe .foreach(_ := source.common.flushPipe.get) 333 this.pc .foreach(_ := source.jmp.get.pc) 334 this.jalrTarget .foreach(_ := source.jmp.get.target) 335 this.preDecode .foreach(_ := source.common.preDecode.get) 336 this.ftqIdx .foreach(_ := source.common.ftqIdx.get) 337 this.ftqOffset .foreach(_ := source.common.ftqOffset.get) 338 this.predictInfo .foreach(_ := source.common.predictInfo.get) 339 this.lqIdx .foreach(_ := source.common.lqIdx.get) 340 this.sqIdx .foreach(_ := source.common.sqIdx.get) 341 } 342 } 343 344 // ExuInput --[FuncUnit]--> ExuOutput 345 class ExuOutput( 346 val params: ExeUnitParams, 347 )(implicit 348 val p: Parameters 349 ) extends Bundle with BundleSource with HasXSParameter { 350 val data = UInt(params.dataBitsMax.W) 351 val pdest = UInt(params.wbPregIdxWidth.W) 352 val robIdx = new RobPtr 353 val intWen = if (params.writeIntRf) Some(Bool()) else None 354 val fpWen = if (params.writeFpRf) Some(Bool()) else None 355 val vecWen = if (params.writeVecRf) Some(Bool()) else None 356 val redirect = if (params.hasRedirect) Some(ValidIO(new Redirect)) else None 357 val fflags = if (params.writeFflags) Some(UInt(5.W)) else None 358 val exceptionVec = if (params.exceptionOut.nonEmpty) Some(ExceptionVec()) else None 359 val flushPipe = if (params.flushPipe) Some(Bool()) else None 360 val replay = if (params.replayInst) Some(Bool()) else None 361 val lqIdx = if (params.hasLoadFu) Some(new LqPtr()) else None 362 val sqIdx = if (params.hasStoreAddrFu || params.hasStdFu) 363 Some(new SqPtr()) else None 364 val ftqIdx = if (params.needPc || params.replayInst) 365 Some(new FtqPtr) else None 366 val ftqOffset = if (params.needPc || params.replayInst) 367 Some(UInt(log2Up(PredictWidth).W)) else None 368 // uop info 369 val predecodeInfo = if(params.hasPredecode) Some(new PreDecodeInfo) else None 370 val debug = new DebugBundle 371 val debugInfo = new PerfDebugInfo 372 } 373 374 // ExuOutput + DynInst --> WriteBackBundle 375 class WriteBackBundle(val params: WbConfig)(implicit p: Parameters) extends Bundle with BundleSource { 376 val rfWen = Bool() 377 val fpWen = Bool() 378 val vecWen = Bool() 379 val pdest = UInt(params.pregIdxWidth.W) 380 val data = UInt(params.dataWidth.W) 381 val robIdx = new RobPtr()(p) 382 val flushPipe = Bool() 383 val replayInst = Bool() 384 val redirect = ValidIO(new Redirect) 385 val fflags = UInt(5.W) 386 val exceptionVec = ExceptionVec() 387 val debug = new DebugBundle 388 val debugInfo = new PerfDebugInfo 389 390 def fromExuOutput(source: ExuOutput) = { 391 this.rfWen := source.intWen.getOrElse(false.B) 392 this.fpWen := source.fpWen.getOrElse(false.B) 393 this.vecWen := source.vecWen.getOrElse(false.B) 394 this.pdest := source.pdest 395 this.data := source.data 396 this.robIdx := source.robIdx 397 this.flushPipe := source.flushPipe.getOrElse(false.B) 398 this.replayInst := source.replay.getOrElse(false.B) 399 this.redirect := source.redirect.getOrElse(0.U.asTypeOf(this.redirect)) 400 this.fflags := source.fflags.getOrElse(0.U.asTypeOf(this.fflags)) 401 this.exceptionVec := source.exceptionVec.getOrElse(0.U.asTypeOf(this.exceptionVec)) 402 this.debug := source.debug 403 this.debugInfo := source.debugInfo 404 } 405 406 def asWakeUpBundle: IssueQueueWakeUpBundle = { 407 val wakeup = Output(new IssueQueueWakeUpBundle(params.pregIdxWidth)) 408 wakeup.rfWen := this.rfWen 409 wakeup.fpWen := this.fpWen 410 wakeup.vecWen := this.vecWen 411 wakeup.pdest := this.pdest 412 wakeup.source = this.source 413 wakeup 414 } 415 416 def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 417 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, this.params.pregIdxWidth))) 418 rfWrite.wen := this.rfWen && fire 419 rfWrite.addr := this.pdest 420 rfWrite.data := this.data 421 rfWrite.intWen := this.rfWen 422 rfWrite.fpWen := false.B 423 rfWrite.vecWen := false.B 424 rfWrite 425 } 426 427 def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 428 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, this.params.pregIdxWidth))) 429 rfWrite.wen := (this.fpWen || this.vecWen) && fire 430 rfWrite.addr := this.pdest 431 rfWrite.data := this.data 432 rfWrite.intWen := false.B 433 rfWrite.fpWen := this.fpWen 434 rfWrite.vecWen := this.vecWen 435 rfWrite 436 } 437 } 438 439 class ExceptionInfo extends Bundle { 440 val pc = UInt(VAddrData().dataWidth.W) 441 val instr = UInt(32.W) 442 val commitType = CommitType() 443 val exceptionVec = ExceptionVec() 444 val singleStep = Bool() 445 val crossPageIPFFix = Bool() 446 val isInterrupt = Bool() 447 } 448 449 class MemExuInput(implicit p: Parameters) extends XSBundle { 450 val uop = new DynInst 451 val src = Vec(3, UInt(XLEN.W)) 452 val iqIdx = UInt(log2Up(MemIQSizeMax).W) 453 val isFirstIssue = Bool() 454 } 455 456 class MemExuOutput(implicit p: Parameters) extends XSBundle { 457 val uop = new DynInst 458 val data = UInt(XLEN.W) 459 val debug = new DebugBundle 460 } 461 462 class MemMicroOpRbExt(implicit p: Parameters) extends XSBundle { 463 val uop = new DynInst 464 val flag = UInt(1.W) 465 } 466} 467