1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.ZeroExt 8import xiangshan._ 9import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, MemExuInput, MemExuOutput, LoadShouldCancel} 10import xiangshan.backend.ctrlblock.{DebugLSIO, LsTopdownInfo} 11import xiangshan.backend.datapath.DataConfig.{IntData, VecData} 12import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 13import xiangshan.backend.datapath.WbConfig._ 14import xiangshan.backend.datapath._ 15import xiangshan.backend.exu.ExuBlock 16import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 17import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, PerfCounterIO} 18import xiangshan.backend.issue.{CancelNetwork, Scheduler} 19import xiangshan.backend.rob.RobLsqIO 20import xiangshan.frontend.{FtqPtr, FtqRead} 21import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 22 23class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 24 with HasXSParameter { 25 26 /* Only update the idx in mem-scheduler here 27 * Idx in other schedulers can be updated the same way if needed 28 * 29 * Also note that we filter out the 'stData issue-queues' when counting 30 */ 31 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 32 ibp.updateIdx(idx) 33 } 34 35 println(params.iqWakeUpParams) 36 37 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 38 schdCfg.bindBackendParam(params) 39 } 40 41 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 42 iqCfg.bindBackendParam(params) 43 } 44 45 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 46 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 47 exuCfg.updateExuIdx(i) 48 exuCfg.bindBackendParam(params) 49 } 50 51 println("[Backend] ExuConfigs:") 52 for (exuCfg <- params.allExuParams) { 53 val fuConfigs = exuCfg.fuConfigs 54 val wbPortConfigs = exuCfg.wbPortConfigs 55 val immType = exuCfg.immType 56 57 println("[Backend] " + 58 s"${exuCfg.name}: " + 59 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 60 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 61 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 62 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " 63 ) 64 require( 65 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 66 fuConfigs.map(_.writeIntRf).reduce(_ || _), 67 "int wb port has no priority" 68 ) 69 require( 70 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 71 fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _), 72 "vec wb port has no priority" 73 ) 74 } 75 76 println(s"[Backend] all fu configs") 77 for (cfg <- FuConfig.allConfigs) { 78 println(s"[Backend] $cfg") 79 } 80 81 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 82 for ((port, seq) <- params.getRdPortParams(IntData())) { 83 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 84 } 85 86 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 87 for ((port, seq) <- params.getWbPortParams(IntData())) { 88 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 89 } 90 91 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 92 for ((port, seq) <- params.getRdPortParams(VecData())) { 93 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 94 } 95 96 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 97 for ((port, seq) <- params.getWbPortParams(VecData())) { 98 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 99 } 100 101 val ctrlBlock = LazyModule(new CtrlBlock(params)) 102 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 103 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 104 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 105 val cancelNetwork = LazyModule(new CancelNetwork(params)) 106 val dataPath = LazyModule(new DataPath(params)) 107 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 108 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 109 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 110 111 lazy val module = new BackendImp(this) 112} 113 114class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 115 with HasXSParameter { 116 implicit private val params = wrapper.params 117 118 val io = IO(new BackendIO()(p, wrapper.params)) 119 120 private val ctrlBlock = wrapper.ctrlBlock.module 121 private val intScheduler = wrapper.intScheduler.get.module 122 private val vfScheduler = wrapper.vfScheduler.get.module 123 private val memScheduler = wrapper.memScheduler.get.module 124 private val cancelNetwork = wrapper.cancelNetwork.module 125 private val dataPath = wrapper.dataPath.module 126 private val intExuBlock = wrapper.intExuBlock.get.module 127 private val vfExuBlock = wrapper.vfExuBlock.get.module 128 private val bypassNetwork = Module(new BypassNetwork) 129 private val wbDataPath = Module(new WbDataPath(params)) 130 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 131 132 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 133 intScheduler.io.toSchedulers.wakeupVec ++ 134 vfScheduler.io.toSchedulers.wakeupVec ++ 135 memScheduler.io.toSchedulers.wakeupVec 136 ).map(x => (x.bits.exuIdx, x)).toMap 137 138 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 139 140 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 141 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 142 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 143 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 144 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 145 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 146 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 147 148 wbDataPath.io.fromIntExu.flatten.filter(x => x.bits.params.writeIntRf) 149 150 private val vconfig = dataPath.io.vconfigReadPort.data 151 private val og1CancelVec: Vec[Bool] = dataPath.io.og1CancelVec 152 private val og0CancelVecFromDataPath: Vec[Bool] = dataPath.io.og0CancelVec 153 private val og0CancelVecFromCancelNet: Vec[Bool] = cancelNetwork.io.out.og0CancelVec 154 private val og0CancelVecFromFinalIssue: Vec[Bool] = Wire(chiselTypeOf(dataPath.io.og0CancelVec)) 155 private val og0CancelVec: Seq[Bool] = og0CancelVecFromDataPath.zip(og0CancelVecFromCancelNet).zip(og0CancelVecFromFinalIssue).map(x => x._1._1 | x._1._2 | x._2) 156 private val cancelToBusyTable = dataPath.io.cancelToBusyTable 157 158 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 159 ctrlBlock.io.frontend <> io.frontend 160 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 161 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 162 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 163 ctrlBlock.io.lqCanAccept := io.mem.lqCanAccept 164 ctrlBlock.io.sqCanAccept := io.mem.sqCanAccept 165 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 166 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 167 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 168 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 169 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 170 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 171 ctrlBlock.io.robio.lsTopdownInfo <> io.mem.lsTopdownInfo 172 ctrlBlock.io.robio.debug_ls <> io.mem.debugLS 173 ctrlBlock.io.fromDataPath.vtype := vconfig(7, 0).asTypeOf(new VType) 174 175 intScheduler.io.fromTop.hartId := io.fromTop.hartId 176 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 177 intScheduler.io.fromCtrlBlock.pcVec := ctrlBlock.io.toIssueBlock.pcVec 178 intScheduler.io.fromCtrlBlock.targetVec := ctrlBlock.io.toIssueBlock.targetVec 179 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 180 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 181 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 182 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 183 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 184 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 185 intScheduler.io.fromDataPath.og0Cancel := og0CancelVec 186 intScheduler.io.fromDataPath.og1Cancel := og1CancelVec 187 intScheduler.io.ldCancel := io.mem.ldCancel 188 intScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 189 190 memScheduler.io.fromTop.hartId := io.fromTop.hartId 191 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 192 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 193 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 194 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 195 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 196 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 197 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 198 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 199 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 200 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 201 memScheduler.io.fromMem.get.memWaitUpdateReq.staIssue.zip(io.mem.stIn).foreach { case (sink, source) => 202 sink.valid := source.valid 203 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 204 sink.bits.uop.robIdx := source.bits.robIdx 205 } 206 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 207 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 208 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 209 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 210 memScheduler.io.fromDataPath.og0Cancel := og0CancelVec 211 memScheduler.io.fromDataPath.og1Cancel := og1CancelVec 212 memScheduler.io.ldCancel := io.mem.ldCancel 213 memScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 214 215 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 216 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 217 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 218 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 219 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 220 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 221 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 222 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 223 vfScheduler.io.fromDataPath.og0Cancel := og0CancelVec 224 vfScheduler.io.fromDataPath.og1Cancel := og1CancelVec 225 vfScheduler.io.ldCancel := io.mem.ldCancel 226 vfScheduler.io.fromDataPath.cancelToBusyTable := cancelToBusyTable 227 228 cancelNetwork.io.in.int <> intScheduler.io.toDataPath 229 cancelNetwork.io.in.vf <> vfScheduler.io.toDataPath 230 cancelNetwork.io.in.mem <> memScheduler.io.toDataPath 231 cancelNetwork.io.in.og0CancelVec := og0CancelVecFromDataPath.zip(og0CancelVecFromFinalIssue).map(x => x._1 || x._2) 232 cancelNetwork.io.in.og1CancelVec := og1CancelVec 233 intScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.int 234 vfScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.vf 235 memScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.mem 236 237 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 238 dataPath.io.vconfigReadPort.addr := ctrlBlock.io.toDataPath.vtypeAddr 239 240 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 241 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 242 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 243 244 dataPath.io.ldCancel := io.mem.ldCancel 245 246 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 247 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 248 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 249 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 250 dataPath.io.debugIntRat := ctrlBlock.io.debug_int_rat 251 dataPath.io.debugFpRat := ctrlBlock.io.debug_fp_rat 252 dataPath.io.debugVecRat := ctrlBlock.io.debug_vec_rat 253 dataPath.io.debugVconfigRat := ctrlBlock.io.debug_vconfig_rat 254 255 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 256 bypassNetwork.io.fromDataPath.vf <> dataPath.io.toFpExu 257 bypassNetwork.io.fromDataPath.mem <> dataPath.io.toMemExu 258 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 259 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 260 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 261 sink.valid := source.valid 262 sink.bits.pdest := source.bits.uop.pdest 263 sink.bits.data := source.bits.data 264 } 265 266 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 267 for (i <- 0 until intExuBlock.io.in.length) { 268 for (j <- 0 until intExuBlock.io.in(i).length) { 269 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.int(i)(j).bits.loadDependency, io.mem.ldCancel) 270 NewPipelineConnect( 271 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 272 Mux( 273 bypassNetwork.io.toExus.int(i)(j).fire, 274 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 275 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 276 ) 277 ) 278 } 279 } 280 281 private val csrio = intExuBlock.io.csrio.get 282 csrio.hartId := io.fromTop.hartId 283 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 284 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 285 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 286 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 287 csrio.fpu.isIllegal := false.B // Todo: remove it 288 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 289 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 290 291 val debugVconfig = dataPath.io.debugVconfig.asTypeOf(new VConfig) 292 val debugVtype = VType.toVtypeStruct(debugVconfig.vtype).asUInt 293 val debugVl = debugVconfig.vl 294 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 295 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vcsrFlag 296 csrio.vpu.set_vstart.bits := 0.U 297 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 298 csrio.vpu.set_vtype.bits := ZeroExt(debugVtype, XLEN) 299 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 300 csrio.vpu.set_vl.bits := ZeroExt(debugVl, XLEN) 301 csrio.exception := ctrlBlock.io.robio.exception 302 csrio.memExceptionVAddr := io.mem.exceptionVAddr 303 csrio.externalInterrupt := io.fromTop.externalInterrupt 304 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 305 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 306 csrio.perf <> io.perf 307 private val fenceio = intExuBlock.io.fenceio.get 308 fenceio.disableSfence := csrio.disableSfence 309 io.fenceio <> fenceio 310 311 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 312 for (i <- 0 until vfExuBlock.io.in.size) { 313 for (j <- 0 until vfExuBlock.io.in(i).size) { 314 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.vf(i)(j).bits.loadDependency, io.mem.ldCancel) 315 NewPipelineConnect( 316 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 317 Mux( 318 bypassNetwork.io.toExus.vf(i)(j).fire, 319 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 320 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 321 ) 322 ) 323 324 vfExuBlock.io.in(i)(j).bits.vpu.foreach(_.vstart := csrio.vpu.vstart) 325 } 326 } 327 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 328 329 wbDataPath.io.flush := ctrlBlock.io.redirect 330 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 331 wbDataPath.io.fromIntExu <> intExuBlock.io.out 332 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 333 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 334 sink.valid := source.valid 335 source.ready := sink.ready 336 sink.bits.data := source.bits.data 337 sink.bits.pdest := source.bits.uop.pdest 338 sink.bits.robIdx := source.bits.uop.robIdx 339 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 340 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 341 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 342 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 343 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 344 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 345 sink.bits.debug := source.bits.debug 346 sink.bits.debugInfo := 0.U.asTypeOf(sink.bits.debugInfo) 347 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 348 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 349 sink.bits.ftqIdx.foreach(_ := source.bits.uop.ftqPtr) 350 sink.bits.ftqOffset.foreach(_ := source.bits.uop.ftqOffset) 351 } 352 353 // to mem 354 private val memIssueParams = params.memSchdParams.get.issueBlockParams 355 private val memExuBlocksHasLDU = memIssueParams.map(_.exuBlockParams.map(_.fuConfigs.contains(FuConfig.LduCfg))) 356 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 357 for (i <- toMem.indices) { 358 for (j <- toMem(i).indices) { 359 val shouldLdCancel = LoadShouldCancel(bypassNetwork.io.toExus.mem(i)(j).bits.loadDependency, io.mem.ldCancel) 360 val issueTimeout = 361 if (memExuBlocksHasLDU(i)(j)) 362 Counter(0 until 16, toMem(i)(j).valid && !toMem(i)(j).fire, bypassNetwork.io.toExus.mem(i)(j).fire)._2 363 else 364 false.B 365 366 if (memScheduler.io.loadFinalIssueResp(i).nonEmpty) { 367 memScheduler.io.loadFinalIssueResp(i)(j).valid := issueTimeout 368 memScheduler.io.loadFinalIssueResp(i)(j).bits.dataInvalidSqIdx := DontCare 369 memScheduler.io.loadFinalIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType 370 memScheduler.io.loadFinalIssueResp(i)(j).bits.respType := RSFeedbackType.fuBusy 371 memScheduler.io.loadFinalIssueResp(i)(j).bits.rfWen := toMem(i)(j).bits.rfWen.getOrElse(false.B) 372 memScheduler.io.loadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx 373 } 374 375 NewPipelineConnect( 376 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 377 Mux( 378 bypassNetwork.io.toExus.mem(i)(j).fire, 379 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || shouldLdCancel, 380 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) || issueTimeout 381 ) 382 ) 383 } 384 } 385 386 io.mem.redirect := ctrlBlock.io.redirect 387 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 388 sink.valid := source.valid 389 source.ready := sink.ready 390 sink.bits.iqIdx := source.bits.iqIdx 391 sink.bits.isFirstIssue := source.bits.isFirstIssue 392 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 393 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 394 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 395 sink.bits.deqPortIdx := source.bits.deqPortIdx.getOrElse(0.U) 396 sink.bits.uop.fuType := source.bits.fuType 397 sink.bits.uop.fuOpType := source.bits.fuOpType 398 sink.bits.uop.imm := source.bits.imm 399 sink.bits.uop.robIdx := source.bits.robIdx 400 sink.bits.uop.pdest := source.bits.pdest 401 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 402 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 403 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 404 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 405 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 406 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 407 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 408 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 409 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 410 } 411 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 412 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 413 io.mem.tlbCsr := csrio.tlb 414 io.mem.csrCtrl := csrio.customCtrl 415 io.mem.sfence := fenceio.sfence 416 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 417 require(io.mem.loadPcRead.size == params.LduCnt) 418 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 419 loadPcRead.data := ctrlBlock.io.memLdPcRead(i).data 420 ctrlBlock.io.memLdPcRead(i).ptr := loadPcRead.ptr 421 ctrlBlock.io.memLdPcRead(i).offset := loadPcRead.offset 422 } 423 424 ctrlBlock.io.robio.robHeadLsIssue := io.mem.issueUops.map(deq => deq.fire && deq.bits.uop.robIdx === ctrlBlock.io.robio.robDeqPtr).reduce(_ || _) 425 426 // mem io 427 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 428 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 429 io.mem.toSbuffer <> fenceio.sbuffer 430 431 private val intFinalIssueBlock = intExuBlock.io.in.flatten.map(_ => false.B) 432 private val vfFinalIssueBlock = vfExuBlock.io.in.flatten.map(_ => false.B) 433 private val memFinalIssueBlock = io.mem.issueUops zip memExuBlocksHasLDU.flatten map { 434 case (out, isLdu) => 435 if (isLdu) RegNext(out.valid && !out.ready, false.B) 436 else false.B 437 } 438 og0CancelVecFromFinalIssue := intFinalIssueBlock ++ vfFinalIssueBlock ++ memFinalIssueBlock 439 440 io.frontendSfence := fenceio.sfence 441 io.frontendTlbCsr := csrio.tlb 442 io.frontendCsrCtrl := csrio.customCtrl 443 444 io.tlb <> csrio.tlb 445 446 io.csrCustomCtrl := csrio.customCtrl 447 448 dontTouch(memScheduler.io) 449 dontTouch(io.mem) 450 dontTouch(dataPath.io.toMemExu) 451 dontTouch(wbDataPath.io.fromMemExu) 452} 453 454class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 455 // params alias 456 private val LoadQueueSize = VirtualLoadQueueSize 457 // In/Out // Todo: split it into one-direction bundle 458 val lsqEnqIO = Flipped(new LsqEnqIO) 459 val robLsqIO = new RobLsqIO 460 val toSbuffer = new FenceToSbuffer 461 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 462 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 463 val ldCancel = Vec(params.LduCnt, Flipped(new LoadCancelIO)) 464 val loadPcRead = Vec(params.LduCnt, Flipped(new FtqRead(UInt(VAddrBits.W)))) 465 466 // Input 467 val writeBack = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(Flipped(DecoupledIO(new MemExuOutput()))) ++ Seq.fill(params.VlduCnt)(Flipped(DecoupledIO(new MemExuOutput(true))))) 468 469 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 470 val stIn = Input(Vec(params.StaCnt, ValidIO(new DynInst()))) 471 val memoryViolation = Flipped(ValidIO(new Redirect)) 472 val exceptionVAddr = Input(UInt(VAddrBits.W)) 473 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 474 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 475 476 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 477 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 478 479 val lqCanAccept = Input(Bool()) 480 val sqCanAccept = Input(Bool()) 481 482 val otherFastWakeup = Flipped(Vec(params.LduCnt + 2 * params.StaCnt, ValidIO(new DynInst))) 483 val stIssuePtr = Input(new SqPtr()) 484 485 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 486 487 val debugLS = Flipped(Output(new DebugLSIO)) 488 489 val lsTopdownInfo = Vec(params.LduCnt, Flipped(Output(new LsTopdownInfo))) 490 // Output 491 val redirect = ValidIO(new Redirect) // rob flush MemBlock 492 val issueUops = MixedVec(Seq.fill(params.LduCnt + params.StaCnt + params.StdCnt)(DecoupledIO(new MemExuInput())) ++ Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 493 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 494 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 495 496 val tlbCsr = Output(new TlbCsrBundle) 497 val csrCtrl = Output(new CustomCSRCtrlIO) 498 val sfence = Output(new SfenceBundle) 499 val isStoreException = Output(Bool()) 500} 501 502class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 503 val fromTop = new Bundle { 504 val hartId = Input(UInt(8.W)) 505 val externalInterrupt = new ExternalInterruptIO 506 } 507 508 val toTop = new Bundle { 509 val cpuHalted = Output(Bool()) 510 } 511 512 val fenceio = new FenceIO 513 // Todo: merge these bundles into BackendFrontendIO 514 val frontend = Flipped(new FrontendToCtrlIO) 515 val frontendSfence = Output(new SfenceBundle) 516 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 517 val frontendTlbCsr = Output(new TlbCsrBundle) 518 // distributed csr write 519 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 520 521 val mem = new BackendMemIO 522 523 val perf = Input(new PerfCounterIO) 524 525 val tlb = Output(new TlbCsrBundle) 526 527 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 528} 529