1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.Bundles._ 23import xiangshan.backend.datapath.DataConfig._ 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.datapath.{WakeUpConfig, WbArbiterParams} 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.issue._ 29import xiangshan.backend.regfile._ 30 31import scala.reflect.{ClassTag, classTag} 32 33case class BackendParams( 34 schdParams : Map[SchedulerType, SchdBlockParams], 35 pregParams : Seq[PregParams], 36 iqWakeUpParams : Seq[WakeUpConfig], 37) { 38 39 configChecks 40 41 def intSchdParams = schdParams.get(IntScheduler()) 42 def vfSchdParams = schdParams.get(VfScheduler()) 43 def memSchdParams = schdParams.get(MemScheduler()) 44 def allSchdParams: Seq[SchdBlockParams] = 45 (Seq(intSchdParams) :+ vfSchdParams :+ memSchdParams) 46 .filter(_.nonEmpty) 47 .map(_.get) 48 def allIssueParams: Seq[IssueBlockParams] = 49 allSchdParams.map(_.issueBlockParams).flatten 50 def allExuParams: Seq[ExeUnitParams] = 51 allIssueParams.map(_.exuBlockParams).flatten 52 53 def intPregParams: IntPregParams = pregParams.collectFirst { case x: IntPregParams => x }.get 54 def vfPregParams: VfPregParams = pregParams.collectFirst { case x: VfPregParams => x }.get 55 def getPregParams: Map[DataConfig, PregParams] = { 56 pregParams.map(x => (x.dataCfg, x)).toMap 57 } 58 59 def pregIdxWidth = pregParams.map(_.addrWidth).max 60 61 def numSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numSrc).max).max 62 def numRegSrc : Int = allSchdParams.map(_.issueBlockParams.map(_.numRegSrc).max).max 63 def numVecRegSrc: Int = allSchdParams.map(_.issueBlockParams.map(_.numVecSrc).max).max 64 65 66 def AluCnt = allSchdParams.map(_.AluCnt).sum 67 def StaCnt = allSchdParams.map(_.StaCnt).sum 68 def StdCnt = allSchdParams.map(_.StdCnt).sum 69 def LduCnt = allSchdParams.map(_.LduCnt).sum 70 def VlduCnt = allSchdParams.map(_.VlduCnt).sum 71 def LsExuCnt = StaCnt + LduCnt 72 def JmpCnt = allSchdParams.map(_.JmpCnt).sum 73 def BrhCnt = allSchdParams.map(_.BrhCnt).sum 74 def IqCnt = allSchdParams.map(_.issueBlockParams.length).sum 75 76 def numPcReadPort = allSchdParams.map(_.numPcReadPort).sum 77 78 def numPregRd(dataCfg: DataConfig) = this.getRfReadSize(dataCfg) 79 def numPregWb(dataCfg: DataConfig) = this.getRfWriteSize(dataCfg) 80 81 def numNoDataWB = allSchdParams.map(_.numNoDataWB).sum 82 def numExu = allSchdParams.map(_.numExu).sum 83 def vconfigPort = 0 // Todo: remove it 84 85 def numException = allExuParams.count(_.exceptionOut.nonEmpty) 86 87 def numRedirect = allSchdParams.map(_.numRedirect).sum 88 89 def genIntWriteBackBundle(implicit p: Parameters) = { 90 Seq.fill(this.getIntRfWriteSize)(new RfWritePortWithConfig(IntData(), intPregParams.addrWidth)) 91 } 92 93 def genVfWriteBackBundle(implicit p: Parameters) = { 94 Seq.fill(this.getVfRfWriteSize)(new RfWritePortWithConfig(VecData(), vfPregParams.addrWidth)) 95 } 96 97 def genWriteBackBundles(implicit p: Parameters): Seq[RfWritePortWithConfig] = { 98 genIntWriteBackBundle ++ genVfWriteBackBundle 99 } 100 101 def genWrite2CtrlBundles(implicit p: Parameters): MixedVec[ValidIO[ExuOutput]] = { 102 MixedVec(allSchdParams.map(_.genExuOutputValidBundle.flatten).reduce(_ ++ _)) 103 } 104 105 def getIntWbArbiterParams: WbArbiterParams = { 106 val intWbCfgs: Seq[IntWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(_.writeInt)).map(_.asInstanceOf[IntWB]) 107 datapath.WbArbiterParams(intWbCfgs, intPregParams, this) 108 } 109 110 def getVfWbArbiterParams: WbArbiterParams = { 111 val vfWbCfgs: Seq[VfWB] = allSchdParams.flatMap(_.getWbCfgs.flatten.flatten.filter(x => x.writeVec || x.writeFp)).map(_.asInstanceOf[VfWB]) 112 datapath.WbArbiterParams(vfWbCfgs, vfPregParams, this) 113 } 114 115 /** 116 * Get regfile read port params 117 * 118 * @param dataCfg [[IntData]] or [[VecData]] 119 * @return Seq[port->Seq[(exuIdx, priority)] 120 */ 121 def getRdPortParams(dataCfg: DataConfig) = { 122 // port -> Seq[exuIdx, priority] 123 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allExuParams 124 .flatMap(x => x.rfrPortConfigs.flatten.map(xx => (xx, x.exuIdx))) 125 .filter { x => x._1.getDataConfig == dataCfg } 126 .map(x => (x._1.port, (x._2, x._1.priority))) 127 .groupBy(_._1) 128 .map(x => (x._1, x._2.map(_._2).sortBy({ case (priority, _) => priority }))) 129 .toSeq 130 .sortBy(_._1) 131 cfgs 132 } 133 134 /** 135 * Get regfile write back port params 136 * 137 * @param dataCfg [[IntData]] or [[VecData]] 138 * @return Seq[port->Seq[(exuIdx, priority)] 139 */ 140 def getWbPortParams(dataCfg: DataConfig) = { 141 val cfgs: Seq[(Int, Seq[(Int, Int)])] = allExuParams 142 .flatMap(x => x.wbPortConfigs.map(xx => (xx, x.exuIdx))) 143 .filter { x => x._1.dataCfg == dataCfg } 144 .map(x => (x._1.port, (x._2, x._1.priority))) 145 .groupBy(_._1) 146 .map(x => (x._1, x._2.map(_._2))) 147 .toSeq 148 .sortBy(_._1) 149 cfgs 150 } 151 152 def getRdPortIndices(dataCfg: DataConfig) = { 153 this.getRdPortParams(dataCfg).map(_._1) 154 } 155 156 def getWbPortIndices(dataCfg: DataConfig) = { 157 this.getWbPortParams(dataCfg).map(_._1) 158 } 159 160 def getRdCfgs[T <: RdConfig](implicit tag: ClassTag[T]): Seq[Seq[Seq[RdConfig]]] = { 161 val rdCfgs: Seq[Seq[Seq[RdConfig]]] = allIssueParams.map( 162 _.exuBlockParams.map( 163 _.rfrPortConfigs.map( 164 _.collectFirst{ case x: T => x } 165 .getOrElse(NoRD()) 166 ) 167 ) 168 ) 169 rdCfgs 170 } 171 172 def getAllWbCfgs: Seq[Seq[Set[PregWB]]] = { 173 allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.toSet)) 174 } 175 176 def getWbCfgs[T <: PregWB](implicit tag: ClassTag[T]): Seq[Seq[PregWB]] = { 177 val wbCfgs: Seq[Seq[PregWB]] = allIssueParams.map(_.exuBlockParams.map(_.wbPortConfigs.collectFirst{ case x: T => x }.getOrElse(NoWB()))) 178 wbCfgs 179 } 180 181 /** 182 * Get size of read ports of int regfile 183 * 184 * @return if [[IntPregParams.numRead]] is [[None]], get size of ports in [[IntRD]] 185 */ 186 def getIntRfReadSize = { 187 this.intPregParams.numRead.getOrElse(this.getRdPortIndices(IntData()).size) 188 } 189 190 /** 191 * Get size of write ports of vf regfile 192 * 193 * @return if [[IntPregParams.numWrite]] is [[None]], get size of ports in [[IntWB]] 194 */ 195 def getIntRfWriteSize = { 196 this.intPregParams.numWrite.getOrElse(this.getWbPortIndices(IntData()).size) 197 } 198 199 /** 200 * Get size of read ports of int regfile 201 * 202 * @return if [[VfPregParams.numRead]] is [[None]], get size of ports in [[VfRD]] 203 */ 204 def getVfRfReadSize = { 205 this.vfPregParams.numRead.getOrElse(this.getRdPortIndices(VecData()).size) 206 } 207 208 /** 209 * Get size of write ports of vf regfile 210 * 211 * @return if [[VfPregParams.numWrite]] is [[None]], get size of ports in [[VfWB]] 212 */ 213 def getVfRfWriteSize = { 214 this.vfPregParams.numWrite.getOrElse(this.getWbPortIndices(VecData()).size) 215 } 216 217 def getRfReadSize(dataCfg: DataConfig) = { 218 this.getPregParams(dataCfg).numRead.getOrElse(this.getRdPortIndices(dataCfg).size) 219 } 220 221 def getRfWriteSize(dataCfg: DataConfig) = { 222 this.getPregParams(dataCfg).numWrite.getOrElse(this.getWbPortIndices(dataCfg).size) 223 } 224 225 def getExuIdx(name: String): Int = { 226 val exuParams = allExuParams 227 if (name != "WB") { 228 val foundExu = exuParams.find(_.name == name) 229 require(foundExu.nonEmpty, s"exu $name not find") 230 foundExu.get.exuIdx 231 } else 232 -1 233 } 234 235 def getExuName(idx: Int): String = { 236 val exuParams = allExuParams 237 exuParams(idx).name 238 } 239 240 def getIntWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allExuParams.groupBy(x => x.getIntWBPort.getOrElse(IntWB(port = -1)).port).filter(_._1 != -1) 241 def getVfWBExeGroup: Map[Int, Seq[ExeUnitParams]] = allExuParams.groupBy(x => x.getVfWBPort.getOrElse(VfWB(port = -1)).port).filter(_._1 != -1) 242 243 private def isContinuous(portIndices: Seq[Int]): Boolean = { 244 val portIndicesSet = portIndices.toSet 245 portIndicesSet.min == 0 && portIndicesSet.max == portIndicesSet.size - 1 246 } 247 248 def configChecks = { 249 checkReadPortContinuous 250 checkWritePortContinuous 251 configCheck 252 } 253 254 def checkReadPortContinuous = { 255 pregParams.foreach { x => 256 if (x.numRead.isEmpty) { 257 val portIndices: Seq[Int] = getRdPortIndices(x.dataCfg) 258 require(isContinuous(portIndices), 259 s"The read ports of ${x.getClass.getSimpleName} should be continuous, " + 260 s"when numRead of ${x.getClass.getSimpleName} is None. The read port indices are $portIndices") 261 } 262 } 263 } 264 265 def checkWritePortContinuous = { 266 pregParams.foreach { x => 267 if (x.numWrite.isEmpty) { 268 val portIndices: Seq[Int] = getWbPortIndices(x.dataCfg) 269 require( 270 isContinuous(portIndices), 271 s"The write ports of ${x.getClass.getSimpleName} should be continuous, " + 272 s"when numWrite of ${x.getClass.getSimpleName} is None. The write port indices are $portIndices" 273 ) 274 } 275 } 276 } 277 278 def configCheck = { 279 // check 0 280 val maxPortSource = 2 281 282 allExuParams.map { 283 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: IntWB => x } 284 }.filter(_.isDefined).groupBy(_.get.port).foreach { 285 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Int WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 286 } 287 allExuParams.map { 288 case exuParam => exuParam.wbPortConfigs.collectFirst { case x: VfWB => x } 289 }.filter(_.isDefined).groupBy(_.get.port).foreach { 290 case (wbPort, priorities) => assert(priorities.size <= maxPortSource, "There has " + priorities.size + " exu's " + "Vf WBport is " + wbPort + ", but the maximum is " + maxPortSource + ".") 291 } 292 293 // check 1 294 val wbTypes = Seq(IntWB(), VfWB()) 295 val rdTypes = Seq(IntRD(), VfRD()) 296 for(wbType <- wbTypes){ 297 for(rdType <- rdTypes){ 298 allExuParams.map { 299 case exuParam => 300 val wbPortConfigs = exuParam.wbPortConfigs 301 val wbConfigs = wbType match{ 302 case _: IntWB => wbPortConfigs.collectFirst { case x: IntWB => x } 303 case _: VfWB => wbPortConfigs.collectFirst { case x: VfWB => x } 304 case _ => None 305 } 306 val rfReadPortConfigs = exuParam.rfrPortConfigs 307 val rdConfigs = rdType match{ 308 case _: IntRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[IntRD]) 309 case _: VfRD => rfReadPortConfigs.flatten.filter(_.isInstanceOf[VfRD]) 310 case _ => Seq() 311 } 312 (wbConfigs, rdConfigs) 313 }.filter(_._1.isDefined) 314 .sortBy(_._1.get.priority) 315 .groupBy(_._1.get.port).map { 316 case (_, intWbRdPairs) => 317 intWbRdPairs.map(_._2).flatten 318 }.map(rdCfgs => rdCfgs.groupBy(_.port).foreach { 319 case (_, rdCfgs) => 320 rdCfgs.zip(rdCfgs.drop(1)).foreach { case (cfg0, cfg1) => assert(cfg0.priority <= cfg1.priority) } 321 }) 322 } 323 } 324 } 325} 326 327 328 329 330