1package xiangshan.backend.datapath 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import difftest.{DifftestArchFpRegState, DifftestArchIntRegState, DifftestArchVecRegState} 7import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 8import utility._ 9import xiangshan._ 10import xiangshan.backend.BackendParams 11import xiangshan.backend.datapath.DataConfig._ 12import xiangshan.backend.datapath.RdConfig._ 13import xiangshan.backend.issue.{ImmExtractor, IntScheduler, MemScheduler, VfScheduler} 14import xiangshan.backend.Bundles._ 15import xiangshan.backend.regfile._ 16 17class RFArbiterBundle(addrWidth: Int)(implicit p: Parameters) extends XSBundle { 18 val addr = UInt(addrWidth.W) 19} 20 21class RFReadArbiterIO(inPortSize: Int, outPortSize: Int, pregWidth: Int)(implicit p: Parameters) extends XSBundle { 22 val in = Vec(inPortSize, Flipped(DecoupledIO(new RFArbiterBundle(pregWidth)))) 23 val out = Vec(outPortSize, Valid(new RFArbiterBundle(pregWidth))) 24 val flush = Flipped(ValidIO(new Redirect)) 25} 26 27class RFReadArbiter(isInt: Boolean)(implicit p: Parameters) extends XSModule { 28 val allExuParams = backendParams.allExuParams 29 30 val portConfigs: Seq[RdConfig] = allExuParams.map(_.rfrPortConfigs.flatten).flatten.filter{ 31 rfrPortConfigs => 32 if(isInt){ 33 rfrPortConfigs.isInstanceOf[IntRD] 34 } 35 else{ 36 rfrPortConfigs.isInstanceOf[VfRD] 37 } 38 } 39 40 private val moduleName = this.getClass.getName + (if (isInt) "Int" else "Vf") 41 42 println(s"[$moduleName] ports(${portConfigs.size})") 43 for (portCfg <- portConfigs) { 44 println(s"[$moduleName] port: ${portCfg.port}, priority: ${portCfg.priority}") 45 } 46 47 val pregParams = if(isInt) backendParams.intPregParams else backendParams.vfPregParams 48 49 val io = IO(new RFReadArbiterIO(portConfigs.size, backendParams.numRfRead, pregParams.addrWidth)) 50 // inGroup[port -> Bundle] 51 val inGroup: Map[Int, IndexedSeq[(DecoupledIO[RFArbiterBundle], RdConfig)]] = io.in.zip(portConfigs).groupBy{ case(port, config) => config.port} 52 // sort by priority 53 val inGroupSorted: Map[Int, IndexedSeq[(DecoupledIO[RFArbiterBundle], RdConfig)]] = inGroup.map{ 54 case(key, value) => (key -> value.sortBy{ case(port, config) => config.priority}) 55 } 56 57 private val arbiters: Seq[Option[Arbiter[RFArbiterBundle]]] = Seq.tabulate(backendParams.numRfRead) { x => { 58 if (inGroupSorted.contains(x)) { 59 Some(Module(new Arbiter(new RFArbiterBundle(pregParams.addrWidth), inGroupSorted(x).length))) 60 } else { 61 None 62 } 63 }} 64 65 arbiters.zipWithIndex.foreach { case (arb, i) => 66 if (arb.nonEmpty) { 67 arb.get.io.in.zip(inGroupSorted(i).map(_._1)).foreach { case (arbIn, addrIn) => 68 arbIn <> addrIn 69 } 70 } 71 } 72 73 io.out.zip(arbiters).foreach { case (addrOut, arb) => 74 if (arb.nonEmpty) { 75 val arbOut = arb.get.io.out 76 arbOut.ready := true.B 77 addrOut.valid := arbOut.valid 78 addrOut.bits := arbOut.bits 79 } else { 80 addrOut := 0.U.asTypeOf(addrOut) 81 } 82 } 83} 84 85class DataPath(params: BackendParams)(implicit p: Parameters) extends LazyModule { 86 private implicit val dpParams: BackendParams = params 87 lazy val module = new DataPathImp(this) 88} 89 90class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params: BackendParams) 91 extends LazyModuleImp(wrapper) with HasXSParameter { 92 93 private val VCONFIG_PORT = params.vconfigPort 94 95 val io = IO(new DataPathIO()) 96 97 private val (fromIntIQ, toIntIQ, toIntExu) = (io.fromIntIQ, io.toIntIQ, io.toIntExu) 98 private val (fromMemIQ, toMemIQ, toMemExu) = (io.fromMemIQ, io.toMemIQ, io.toMemExu) 99 private val (fromVfIQ , toVfIQ , toVfExu ) = (io.fromVfIQ , io.toVfIQ , io.toFpExu) 100 101 println(s"[DataPath] IntIQ(${fromIntIQ.size}), MemIQ(${fromMemIQ.size})") 102 println(s"[DataPath] IntExu(${fromIntIQ.map(_.size).sum}), MemExu(${fromMemIQ.map(_.size).sum})") 103 104 // just refences for convience 105 private val fromIQ = fromIntIQ ++ fromVfIQ ++ fromMemIQ 106 107 private val toIQs = toIntIQ ++ toVfIQ ++ toMemIQ 108 109 private val toExu = toIntExu ++ toVfExu ++ toMemExu 110 111 private val intRFReadArbiter = Module(new RFReadArbiter(true)) 112 private val vfRFReadArbiter = Module(new RFReadArbiter(false)) 113 114 private val issuePortsIn = fromIQ.flatten 115 private val intBlocks = fromIQ.map{ case iq => Wire(Vec(iq.size, Bool())) } 116 private val intBlocksSeq = intBlocks.flatten 117 private val vfBlocks = fromIQ.map { case iq => Wire(Vec(iq.size, Bool())) } 118 private val vfBlocksSeq = vfBlocks.flatten 119 120 val intReadPortInSize: IndexedSeq[Int] = issuePortsIn.map(issuePortIn => issuePortIn.bits.getIntRfReadBundle.size).scan(0)(_ + _) 121 issuePortsIn.zipWithIndex.foreach{ 122 case (issuePortIn, idx) => 123 val readPortIn = issuePortIn.bits.getIntRfReadBundle 124 val l = intReadPortInSize(idx) 125 val r = intReadPortInSize(idx + 1) 126 val arbiterIn = intRFReadArbiter.io.in.slice(l, r) 127 arbiterIn.zip(readPortIn).foreach{ 128 case(sink, source) => 129 sink.bits.addr := source.addr 130 sink.valid := issuePortIn.valid && SrcType.isXp(source.srcType) 131 } 132 if(r > l){ 133 intBlocksSeq(idx) := !arbiterIn.zip(readPortIn).map { 134 case (sink, source) => Mux(SrcType.isXp(source.srcType), sink.ready, true.B) 135 }.reduce(_ & _) 136 } 137 else{ 138 intBlocksSeq(idx) := false.B 139 } 140 } 141 intRFReadArbiter.io.flush := io.flush 142 143 val vfReadPortInSize = issuePortsIn.map(issuePortIn => issuePortIn.bits.getFpRfReadBundle.size).scan(0)(_ + _) 144 issuePortsIn.zipWithIndex.foreach { 145 case (issuePortIn, idx) => 146 val readPortIn = issuePortIn.bits.getFpRfReadBundle 147 val l = vfReadPortInSize(idx) 148 val r = vfReadPortInSize(idx + 1) 149 val arbiterIn = vfRFReadArbiter.io.in.slice(l, r) 150 arbiterIn.zip(readPortIn).foreach { 151 case (sink, source) => 152 sink.bits.addr := source.addr 153 sink.valid := issuePortIn.valid && SrcType.isVfp(source.srcType) 154 } 155 if (r > l) { 156 vfBlocksSeq(idx) := !arbiterIn.zip(readPortIn).map { 157 case (sink, source) => Mux(SrcType.isVfp(source.srcType), sink.ready, true.B) 158 }.reduce(_ & _) 159 } 160 else { 161 vfBlocksSeq(idx) := false.B 162 } 163 } 164 vfRFReadArbiter.io.flush := io.flush 165 166 private val intSchdParams = params.schdParams(IntScheduler()) 167 private val vfSchdParams = params.schdParams(VfScheduler()) 168 private val memSchdParams = params.schdParams(MemScheduler()) 169 170 private val numIntRfReadByExu = intSchdParams.numIntRfReadByExu + memSchdParams.numIntRfReadByExu 171 private val numVfRfReadByExu = vfSchdParams.numVfRfReadByExu + memSchdParams.numVfRfReadByExu 172 // Todo: limit read port 173 private val numIntR = numIntRfReadByExu 174 private val numVfR = numVfRfReadByExu 175 println(s"[DataPath] RegFile read req needed by Exu: Int(${numIntRfReadByExu}), Vf(${numVfRfReadByExu})") 176 println(s"[DataPath] RegFile read port: Int(${numIntR}), Vf(${numVfR})") 177 178 private val schdParams = params.allSchdParams 179 180 private val intRfRaddr = Wire(Vec(params.numRfRead, UInt(intSchdParams.pregIdxWidth.W))) 181 private val intRfRdata = Wire(Vec(params.numRfRead, UInt(intSchdParams.rfDataWidth.W))) 182 private val intRfWen = Wire(Vec(io.fromIntWb.length, Bool())) 183 private val intRfWaddr = Wire(Vec(io.fromIntWb.length, UInt(intSchdParams.pregIdxWidth.W))) 184 private val intRfWdata = Wire(Vec(io.fromIntWb.length, UInt(intSchdParams.rfDataWidth.W))) 185 186 private val vfRfSplitNum = VLEN / XLEN 187 private val vfRfRaddr = Wire(Vec(params.numRfRead, UInt(vfSchdParams.pregIdxWidth.W))) 188 private val vfRfRdata = Wire(Vec(params.numRfRead, UInt(vfSchdParams.rfDataWidth.W))) 189 private val vfRfWen = Wire(Vec(vfRfSplitNum, Vec(io.fromVfWb.length, Bool()))) 190 private val vfRfWaddr = Wire(Vec(io.fromVfWb.length, UInt(vfSchdParams.pregIdxWidth.W))) 191 private val vfRfWdata = Wire(Vec(io.fromVfWb.length, UInt(vfSchdParams.rfDataWidth.W))) 192 193 private val intDebugRead: Option[(Vec[UInt], Vec[UInt])] = 194 if (env.AlwaysBasicDiff || env.EnableDifftest) { 195 Some(Wire(Vec(32, UInt(intSchdParams.pregIdxWidth.W))), Wire(Vec(32, UInt(XLEN.W)))) 196 } else { None } 197 private val vfDebugRead: Option[(Vec[UInt], Vec[UInt])] = 198 if (env.AlwaysBasicDiff || env.EnableDifftest) { 199 Some(Wire(Vec(32 + 32 + 1, UInt(vfSchdParams.pregIdxWidth.W))), Wire(Vec(32 + 32 + 1, UInt(VLEN.W)))) 200 } else { None } 201 202 private val fpDebugReadData: Option[Vec[UInt]] = 203 if (env.AlwaysBasicDiff || env.EnableDifftest) { 204 Some(Wire(Vec(32, UInt(XLEN.W)))) 205 } else { None } 206 private val vecDebugReadData: Option[Vec[UInt]] = 207 if (env.AlwaysBasicDiff || env.EnableDifftest) { 208 Some(Wire(Vec(64, UInt(64.W)))) // v0 = Cat(Vec(1), Vec(0)) 209 } else { None } 210 211 fpDebugReadData.foreach(_ := vfDebugRead 212 .get._2 213 .slice(0, 32) 214 .map(_(63, 0)) 215 ) // fp only used [63, 0] 216 vecDebugReadData.foreach(_ := vfDebugRead 217 .get._2 218 .slice(32, 64) 219 .map(x => Seq(x(63, 0), x(127, 64))).flatten 220 ) 221 222 io.debugVconfig := vfDebugRead.get._2(64)(63, 0) 223 224 IntRegFile("IntRegFile", intSchdParams.numPregs, intRfRaddr, intRfRdata, intRfWen, intRfWaddr, intRfWdata, 225 debugReadAddr = intDebugRead.map(_._1), 226 debugReadData = intDebugRead.map(_._2)) 227 VfRegFile("VfRegFile", vfSchdParams.numPregs, vfRfSplitNum, vfRfRaddr, vfRfRdata, vfRfWen, vfRfWaddr, vfRfWdata, 228 debugReadAddr = vfDebugRead.map(_._1), 229 debugReadData = vfDebugRead.map(_._2)) 230 231 intRfWaddr := io.fromIntWb.map(_.addr) 232 intRfWdata := io.fromIntWb.map(_.data) 233 intRfWen := io.fromIntWb.map(_.wen) 234 235 intRFReadArbiter.io.out.map(_.bits.addr).zip(intRfRaddr).foreach{ case(source, sink) => sink := source } 236 237 vfRfWaddr := io.fromVfWb.map(_.addr) 238 vfRfWdata := io.fromVfWb.map(_.data) 239 vfRfWen.foreach(_.zip(io.fromVfWb.map(_.wen)).foreach { case (wenSink, wenSource) => wenSink := wenSource } )// Todo: support fp multi-write 240 241 vfRFReadArbiter.io.out.map(_.bits.addr).zip(vfRfRaddr).foreach{ case(source, sink) => sink := source } 242 vfRfRaddr(VCONFIG_PORT) := io.vconfigReadPort.addr 243 io.vconfigReadPort.data := vfRfRdata(VCONFIG_PORT) 244 245 intDebugRead.foreach { case (addr, _) => 246 addr := io.debugIntRat 247 } 248 249 vfDebugRead.foreach { case (addr, _) => 250 addr := io.debugFpRat ++ io.debugVecRat :+ io.debugVconfigRat 251 } 252 println(s"[DataPath] " + 253 s"has intDebugRead: ${intDebugRead.nonEmpty}, " + 254 s"has vfDebugRead: ${vfDebugRead.nonEmpty}") 255 256 val s1_addrOHs = Reg(MixedVec( 257 fromIQ.map(x => MixedVec(x.map(_.bits.addrOH.cloneType))) 258 )) 259 val s1_toExuValid: MixedVec[MixedVec[Bool]] = Reg(MixedVec( 260 toExu.map(x => MixedVec(x.map(_.valid.cloneType))) 261 )) 262 val s1_toExuData: MixedVec[MixedVec[ExuInput]] = Reg(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.cloneType))))) 263 val s1_toExuReady = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.ready.cloneType))))) // Todo 264 val s1_srcType: MixedVec[MixedVec[Vec[UInt]]] = MixedVecInit(fromIQ.map(x => MixedVecInit(x.map(xx => RegEnable(xx.bits.srcType, xx.fire))))) 265 266 val s1_intPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType))))) 267 val s1_vfPregRData: MixedVec[MixedVec[Vec[UInt]]] = Wire(MixedVec(toExu.map(x => MixedVec(x.map(_.bits.src.cloneType))))) 268 269 val rfrPortConfigs = schdParams.map(_.issueBlockParams).flatten.map(_.exuBlockParams.map(_.rfrPortConfigs)) 270 271 println(s"[DataPath] s1_intPregRData.flatten.flatten.size: ${s1_intPregRData.flatten.flatten.size}, intRfRdata.size: ${intRfRdata.size}") 272 s1_intPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 273 s1_intPregRData.zip(rfrPortConfigs).foreach { case (iqRdata, iqCfg) => 274 iqRdata.zip(iqCfg).foreach { case (iuRdata, iuCfg) => 275 val realIuCfg = iuCfg.map(x => if(x.size > 1) x.filter(_.isInstanceOf[IntRD]) else x).flatten 276 assert(iuRdata.size == realIuCfg.size, "iuRdata.size != realIuCfg.size") 277 iuRdata.zip(realIuCfg) 278 .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[IntRD] } 279 .foreach { case (sink, cfg) => sink := intRfRdata(cfg.port) } 280 } 281 } 282 283 println(s"[DataPath] s1_vfPregRData.flatten.flatten.size: ${s1_vfPregRData.flatten.flatten.size}, vfRfRdata.size: ${vfRfRdata.size}") 284 s1_vfPregRData.foreach(_.foreach(_.foreach(_ := 0.U))) 285 s1_vfPregRData.zip(rfrPortConfigs).foreach{ case(iqRdata, iqCfg) => 286 iqRdata.zip(iqCfg).foreach{ case(iuRdata, iuCfg) => 287 val realIuCfg = iuCfg.map(x => if(x.size > 1) x.filter(_.isInstanceOf[VfRD]) else x).flatten 288 assert(iuRdata.size == realIuCfg.size, "iuRdata.size != realIuCfg.size") 289 iuRdata.zip(realIuCfg) 290 .filter { case (_, rfrPortConfig) => rfrPortConfig.isInstanceOf[VfRD] } 291 .foreach { case (sink, cfg) => sink := vfRfRdata(cfg.port) } 292 } 293 } 294 295 // var intRfRdataIdx = 0 296// var vfRfRdataIdx = 0 297// for (iqIdx <- toExu.indices) { 298// for (exuIdx <- toExu(iqIdx).indices) { 299// for (srcIdx <- toExu(iqIdx)(exuIdx).bits.src.indices) { 300// val readDataCfgSet = toExu(iqIdx)(exuIdx).bits.params.getSrcDataType(srcIdx) 301// // need read int reg 302// if (readDataCfgSet.intersect(IntRegSrcDataSet).nonEmpty) { 303// println(s"[DataPath] (iqIdx, exuIdx, srcIdx): ($iqIdx, $exuIdx, $srcIdx)") 304// s1_intPregRData(iqIdx)(exuIdx)(srcIdx) := intRfRdata(intRfRdataIdx) 305// } else { 306// // better for debug, should never assigned to other bundles 307// s1_intPregRData(iqIdx)(exuIdx)(srcIdx) := "hdead_beef_dead_beef".U 308// } 309// // need read vf reg 310// if (readDataCfgSet.intersect(VfRegSrcDataSet).nonEmpty) { 311// s1_vfPregRData(iqIdx)(exuIdx)(srcIdx) := vfRfRdata(vfRfRdataIdx) 312// vfRfRdataIdx += 1 313// } else { 314// // better for debug, should never assigned to other bundles 315// s1_vfPregRData(iqIdx)(exuIdx)(srcIdx) := "hdead_beef_dead_beef_dead_beef_dead_beef".U 316// } 317// } 318// } 319// } 320// 321// println(s"[DataPath] assigned RegFile Rdata: int(${intRfRdataIdx}), vf(${vfRfRdataIdx})") 322 323 for (i <- fromIQ.indices) { 324 for (j <- fromIQ(i).indices) { 325 // IQ(s0) --[Ctrl]--> s1Reg ---------- begin 326 // refs 327 val s1_valid = s1_toExuValid(i)(j) 328 val s1_ready = s1_toExuReady(i)(j) 329 val s1_data = s1_toExuData(i)(j) 330 val s1_addrOH = s1_addrOHs(i)(j) 331 val s0 = fromIQ(i)(j) // s0 332 val block = intBlocks(i)(j) || vfBlocks(i)(j) 333 val s1_flush = s0.bits.common.robIdx.needFlush(Seq(io.flush, RegNextWithEnable(io.flush))) 334 when (s0.fire && !s1_flush && !block) { 335 s1_valid := s0.valid 336 s1_data.fromIssueBundle(s0.bits) // no src data here 337 s1_addrOH := s0.bits.addrOH 338 }.otherwise { 339 s1_valid := false.B 340 } 341 342 s0.ready := (s1_ready || !s1_valid) && !block 343 // IQ(s0) --[Ctrl]--> s1Reg ---------- end 344 345 // IQ(s0) --[Data]--> s1Reg ---------- begin 346 // imm extract 347 when (s0.fire && !s1_flush && !block) { 348 if (s1_data.params.immType.nonEmpty && s1_data.src.size > 1) { 349 // rs1 is always int reg, rs2 may be imm 350 when(SrcType.isImm(s0.bits.srcType(1))) { 351 s1_data.src(1) := ImmExtractor( 352 s0.bits.common.imm, 353 s0.bits.immType, 354 s1_data.DataBits, 355 s1_data.params.immType.map(_.litValue) 356 ) 357 } 358 } 359 if (s1_data.params.hasJmpFu) { 360 when(SrcType.isPc(s0.bits.srcType(0))) { 361 s1_data.src(0) := SignExt(s0.bits.jmp.get.pc, XLEN) 362 } 363 } 364 } 365 // IQ(s0) --[Data]--> s1Reg ---------- end 366 } 367 } 368 369 private val fromIQFire = fromIQ.map(_.map(_.fire)) 370 private val toExuFire = toExu.map(_.map(_.fire)) 371 toIQs.zipWithIndex.foreach { 372 case(toIQ, iqIdx) => 373 toIQ.zipWithIndex.foreach { 374 case (toIU, iuIdx) => 375 // IU: issue unit 376 val og0resp = toIU.og0resp 377 og0resp.valid := fromIQ(iqIdx)(iuIdx).valid && (!fromIQFire(iqIdx)(iuIdx)) 378 og0resp.bits.respType := RSFeedbackType.rfArbitFail 379 og0resp.bits.success := false.B 380 og0resp.bits.addrOH := fromIQ(iqIdx)(iuIdx).bits.addrOH 381 382 val og1resp = toIU.og1resp 383 og1resp.valid := s1_toExuValid(iqIdx)(iuIdx) 384 og1resp.bits.respType := Mux(toExuFire(iqIdx)(iuIdx), RSFeedbackType.fuIdle, RSFeedbackType.fuBusy) 385 og1resp.bits.success := false.B 386 og1resp.bits.addrOH := s1_addrOHs(iqIdx)(iuIdx) 387 } 388 } 389 390 for (i <- toExu.indices) { 391 for (j <- toExu(i).indices) { 392 // s1Reg --[Ctrl]--> exu(s1) ---------- begin 393 // refs 394 val sinkData = toExu(i)(j).bits 395 // assign 396 toExu(i)(j).valid := s1_toExuValid(i)(j) 397 s1_toExuReady(i)(j) := toExu(i)(j).ready 398 sinkData := s1_toExuData(i)(j) 399 // s1Reg --[Ctrl]--> exu(s1) ---------- end 400 401 // s1Reg --[Data]--> exu(s1) ---------- begin 402 // data source1: preg read data 403 for (k <- sinkData.src.indices) { 404 val srcDataTypeSet: Set[DataConfig] = sinkData.params.getSrcDataType(k) 405 406 val readRfMap: Seq[(Bool, UInt)] = (Seq(None) :+ 407 (if (s1_intPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(IntRegSrcDataSet).nonEmpty) 408 Some(SrcType.isXp(s1_srcType(i)(j)(k)) -> s1_intPregRData(i)(j)(k)) 409 else None) :+ 410 (if (s1_vfPregRData(i)(j).isDefinedAt(k) && srcDataTypeSet.intersect(VfRegSrcDataSet).nonEmpty) 411 Some(SrcType.isVfp(s1_srcType(i)(j)(k))-> s1_vfPregRData(i)(j)(k)) 412 else None) 413 ).filter(_.nonEmpty).map(_.get) 414 if (readRfMap.nonEmpty) 415 sinkData.src(k) := Mux1H(readRfMap) 416 } 417 418 // data source2: extracted imm and pc saved in s1Reg 419 if (sinkData.params.immType.nonEmpty && sinkData.src.size > 1) { 420 when(SrcType.isImm(s1_srcType(i)(j)(1))) { 421 sinkData.src(1) := s1_toExuData(i)(j).src(1) 422 } 423 } 424 if (sinkData.params.hasJmpFu) { 425 when(SrcType.isPc(s1_srcType(i)(j)(0))) { 426 sinkData.src(0) := s1_toExuData(i)(j).src(0) 427 } 428 } 429 // s1Reg --[Data]--> exu(s1) ---------- end 430 } 431 } 432 433 if (env.AlwaysBasicDiff || env.EnableDifftest) { 434 val delayedCnt = 2 435 val difftestArchIntRegState = Module(new DifftestArchIntRegState) 436 difftestArchIntRegState.io.clock := clock 437 difftestArchIntRegState.io.coreid := io.hartId 438 difftestArchIntRegState.io.gpr := DelayN(intDebugRead.get._2, delayedCnt) 439 440 val difftestArchFpRegState = Module(new DifftestArchFpRegState) 441 difftestArchFpRegState.io.clock := clock 442 difftestArchFpRegState.io.coreid := io.hartId 443 difftestArchFpRegState.io.fpr := DelayN(fpDebugReadData.get, delayedCnt) 444 445 val difftestArchVecRegState = Module(new DifftestArchVecRegState) 446 difftestArchVecRegState.io.clock := clock 447 difftestArchVecRegState.io.coreid := io.hartId 448 difftestArchVecRegState.io.vpr := DelayN(vecDebugReadData.get, delayedCnt) 449 } 450} 451 452class DataPathIO()(implicit p: Parameters, params: BackendParams) extends XSBundle { 453 // params 454 private val intSchdParams = params.schdParams(IntScheduler()) 455 private val vfSchdParams = params.schdParams(VfScheduler()) 456 private val memSchdParams = params.schdParams(MemScheduler()) 457 // bundles 458 val hartId = Input(UInt(8.W)) 459 460 val flush: ValidIO[Redirect] = Flipped(ValidIO(new Redirect)) 461 462 val vconfigReadPort = new RfReadPort(XLEN, PhyRegIdxWidth) 463 464 val fromIntIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = 465 Flipped(MixedVec(intSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 466 467 val fromMemIQ: MixedVec[MixedVec[DecoupledIO[IssueQueueIssueBundle]]] = 468 Flipped(MixedVec(memSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 469 470 val fromVfIQ = Flipped(MixedVec(vfSchdParams.issueBlockParams.map(_.genIssueDecoupledBundle))) 471 472 val toIntIQ = MixedVec(intSchdParams.issueBlockParams.map(_.genOGRespBundle)) 473 474 val toMemIQ = MixedVec(memSchdParams.issueBlockParams.map(_.genOGRespBundle)) 475 476 val toVfIQ = MixedVec(vfSchdParams.issueBlockParams.map(_.genOGRespBundle)) 477 478 val toIntExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = intSchdParams.genExuInputBundle 479 480 val toFpExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = MixedVec(vfSchdParams.genExuInputBundle) 481 482 val toMemExu: MixedVec[MixedVec[DecoupledIO[ExuInput]]] = memSchdParams.genExuInputBundle 483 484 val fromIntWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genIntWriteBackBundle) 485 486 val fromVfWb: MixedVec[RfWritePortWithConfig] = MixedVec(params.genVfWriteBackBundle) 487 488 val debugIntRat = Input(Vec(32, UInt(intSchdParams.pregIdxWidth.W))) 489 val debugFpRat = Input(Vec(32, UInt(vfSchdParams.pregIdxWidth.W))) 490 val debugVecRat = Input(Vec(32, UInt(vfSchdParams.pregIdxWidth.W))) 491 val debugVconfigRat = Input(UInt(vfSchdParams.pregIdxWidth.W)) 492 val debugVconfig = Output(UInt(XLEN.W)) 493 494} 495