1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import utils.BundleUtils.makeValid 8import utils.OptionWrapper 9import xiangshan._ 10import xiangshan.backend.datapath.DataConfig._ 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.datapath.WbConfig.PregWB 13import xiangshan.backend.decode.{ImmUnion, XDecode} 14import xiangshan.backend.exu.ExeUnitParams 15import xiangshan.backend.fu.FuType 16import xiangshan.backend.fu.fpu.Bundles.Frm 17import xiangshan.backend.fu.vector.Bundles._ 18import xiangshan.backend.issue.{IssueBlockParams, IssueQueueDeqRespBundle, IssueQueueJumpBundle, SchedulerType, EntryDeqRespBundle} 19import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig} 20import xiangshan.backend.rob.RobPtr 21import xiangshan.frontend._ 22import xiangshan.mem.{LqPtr, SqPtr} 23 24object Bundles { 25 26 // frontend -> backend 27 class StaticInst(implicit p: Parameters) extends XSBundle { 28 val instr = UInt(32.W) 29 val pc = UInt(VAddrBits.W) 30 val foldpc = UInt(MemPredPCWidth.W) 31 val exceptionVec = ExceptionVec() 32 val trigger = new TriggerCf 33 val preDecodeInfo = new PreDecodeInfo 34 val pred_taken = Bool() 35 val crossPageIPFFix = Bool() 36 val ftqPtr = new FtqPtr 37 val ftqOffset = UInt(log2Up(PredictWidth).W) 38 39 def connectCtrlFlow(source: CtrlFlow): Unit = { 40 this.instr := source.instr 41 this.pc := source.pc 42 this.foldpc := source.foldpc 43 this.exceptionVec := source.exceptionVec 44 this.trigger := source.trigger 45 this.preDecodeInfo := source.pd 46 this.pred_taken := source.pred_taken 47 this.crossPageIPFFix := source.crossPageIPFFix 48 this.ftqPtr := source.ftqPtr 49 this.ftqOffset := source.ftqOffset 50 } 51 } 52 53 // StaticInst --[Decode]--> DecodedInst 54 class DecodedInst(implicit p: Parameters) extends XSBundle { 55 def numSrc = backendParams.numSrc 56 // passed from StaticInst 57 val instr = UInt(32.W) 58 val pc = UInt(VAddrBits.W) 59 val foldpc = UInt(MemPredPCWidth.W) 60 val exceptionVec = ExceptionVec() 61 val trigger = new TriggerCf 62 val preDecodeInfo = new PreDecodeInfo 63 val pred_taken = Bool() 64 val crossPageIPFFix = Bool() 65 val ftqPtr = new FtqPtr 66 val ftqOffset = UInt(log2Up(PredictWidth).W) 67 // decoded 68 val srcType = Vec(numSrc, SrcType()) 69 val lsrc = Vec(numSrc, UInt(6.W)) 70 val ldest = UInt(6.W) 71 val fuType = FuType() 72 val fuOpType = FuOpType() 73 val rfWen = Bool() 74 val fpWen = Bool() 75 val vecWen = Bool() 76 val isXSTrap = Bool() 77 val waitForward = Bool() // no speculate execution 78 val blockBackward = Bool() 79 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 80 val canRobCompress = Bool() 81 val selImm = SelImm() 82 val imm = UInt(ImmUnion.maxLen.W) 83 val fpu = new FPUCtrlSignals 84 val vpu = new VPUCtrlSignals 85 val wfflags = Bool() 86 val isMove = Bool() 87 val uopIdx = UInt(5.W) 88 val uopSplitType = UopSplitType() 89 val isVset = Bool() 90 val firstUop = Bool() 91 val lastUop = Bool() 92 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 93 val commitType = CommitType() // Todo: remove it 94 95 private def allSignals = srcType.take(3) ++ Seq(fuType, fuOpType, rfWen, fpWen, vecWen, 96 isXSTrap, waitForward, blockBackward, flushPipe, canRobCompress, uopSplitType, selImm) 97 98 def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): DecodedInst = { 99 val decoder: Seq[UInt] = ListLookup( 100 inst, XDecode.decodeDefault.map(bitPatToUInt), 101 table.map{ case (pat, pats) => (pat, pats.map(bitPatToUInt)) }.toArray 102 ) 103 allSignals zip decoder foreach { case (s, d) => s := d } 104 this 105 } 106 107 def isSoftPrefetch: Bool = { 108 fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U 109 } 110 111 def connectStaticInst(source: StaticInst): Unit = { 112 for ((name, data) <- this.elements) { 113 if (source.elements.contains(name)) { 114 data := source.elements(name) 115 } 116 } 117 } 118 } 119 120 // DecodedInst --[Rename]--> DynInst 121 class DynInst(implicit p: Parameters) extends XSBundle { 122 def numSrc = backendParams.numSrc 123 // passed from StaticInst 124 val instr = UInt(32.W) 125 val pc = UInt(VAddrBits.W) 126 val foldpc = UInt(MemPredPCWidth.W) 127 val exceptionVec = ExceptionVec() 128 val trigger = new TriggerCf 129 val preDecodeInfo = new PreDecodeInfo 130 val pred_taken = Bool() 131 val crossPageIPFFix = Bool() 132 val ftqPtr = new FtqPtr 133 val ftqOffset = UInt(log2Up(PredictWidth).W) 134 // passed from DecodedInst 135 val srcType = Vec(numSrc, SrcType()) 136 val lsrc = Vec(numSrc, UInt(6.W)) 137 val ldest = UInt(6.W) 138 val fuType = FuType() 139 val fuOpType = FuOpType() 140 val rfWen = Bool() 141 val fpWen = Bool() 142 val vecWen = Bool() 143 val isXSTrap = Bool() 144 val waitForward = Bool() // no speculate execution 145 val blockBackward = Bool() 146 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 147 val canRobCompress = Bool() 148 val selImm = SelImm() 149 val imm = UInt(XLEN.W) // Todo: check if it need minimized 150 val fpu = new FPUCtrlSignals 151 val vpu = new VPUCtrlSignals 152 val wfflags = Bool() 153 val isMove = Bool() 154 val uopIdx = UInt(5.W) 155 val isVset = Bool() 156 val firstUop = Bool() 157 val lastUop = Bool() 158 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 159 val commitType = CommitType() 160 // rename 161 val srcState = Vec(numSrc, SrcState()) 162 val psrc = Vec(numSrc, UInt(PhyRegIdxWidth.W)) 163 val pdest = UInt(PhyRegIdxWidth.W) 164 val robIdx = new RobPtr 165 val instrSize = UInt(log2Ceil(RenameWidth + 1).W) 166 167 val eliminatedMove = Bool() 168 // Take snapshot at this CFI inst 169 val snapshot = Bool() 170 val debugInfo = new PerfDebugInfo 171 val storeSetHit = Bool() // inst has been allocated an store set 172 val waitForRobIdx = new RobPtr // store set predicted previous store robIdx 173 // Load wait is needed 174 // load inst will not be executed until former store (predicted by mdp) addr calcuated 175 val loadWaitBit = Bool() 176 // If (loadWaitBit && loadWaitStrict), strict load wait is needed 177 // load inst will not be executed until ALL former store addr calcuated 178 val loadWaitStrict = Bool() 179 val ssid = UInt(SSIDWidth.W) 180 // Todo 181 val lqIdx = new LqPtr 182 val sqIdx = new SqPtr 183 // debug module 184 val singleStep = Bool() 185 // schedule 186 val replayInst = Bool() 187 188 def isLUI: Bool = this.fuType === FuType.alu.U && (this.selImm === SelImm.IMM_U || this.selImm === SelImm.IMM_LUI32) 189 def isLUI32: Bool = this.fuType === FuType.alu.U && this.selImm === SelImm.IMM_LUI32 190 def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi 191 192 def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush 193 def isSvinval(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.sfence && !flush 194 def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush 195 196 def srcIsReady: Vec[Bool] = { 197 VecInit(this.srcType.zip(this.srcState).map { 198 case (t, s) => SrcType.isNotReg(t) || SrcState.isReady(s) 199 }) 200 } 201 202 def clearExceptions( 203 exceptionBits: Seq[Int] = Seq(), 204 flushPipe : Boolean = false, 205 replayInst : Boolean = false 206 ): DynInst = { 207 this.exceptionVec.zipWithIndex.filterNot(x => exceptionBits.contains(x._2)).foreach(_._1 := false.B) 208 if (!flushPipe) { this.flushPipe := false.B } 209 if (!replayInst) { this.replayInst := false.B } 210 this 211 } 212 213 def needWriteRf: Bool = (rfWen && ldest =/= 0.U) || fpWen || vecWen 214 } 215 216 trait BundleSource { 217 var wakeupSource = "undefined" 218 var idx = 0 219 } 220 221 /** 222 * 223 * @param pregIdxWidth index width of preg 224 * @param exuIndices exu indices of wakeup bundle 225 */ 226 sealed abstract class IssueQueueWakeUpBaseBundle(pregIdxWidth: Int, val exuIndices: Seq[Int]) extends Bundle { 227 val rfWen = Bool() 228 val fpWen = Bool() 229 val vecWen = Bool() 230 val pdest = UInt(pregIdxWidth.W) 231 232 /** 233 * @param successor Seq[(psrc, srcType)] 234 * @return Seq[if wakeup psrc] 235 */ 236 def wakeUp(successor: Seq[(UInt, UInt)], valid: Bool): Seq[Bool] = { 237 successor.map { case (thatPsrc, srcType) => 238 val pdestMatch = pdest === thatPsrc 239 pdestMatch && ( 240 SrcType.isFp(srcType) && this.fpWen || 241 SrcType.isXp(srcType) && this.rfWen || 242 SrcType.isVp(srcType) && this.vecWen 243 ) && valid 244 } 245 } 246 247 def hasOnlyOneSource: Boolean = exuIndices.size == 1 248 249 def hasMultiSources: Boolean = exuIndices.size > 1 250 251 def isWBWakeUp = this.isInstanceOf[IssueQueueWBWakeUpBundle] 252 253 def isIQWakeUp = this.isInstanceOf[IssueQueueIQWakeUpBundle] 254 255 def exuIdx: Int = { 256 require(hasOnlyOneSource) 257 this.exuIndices.head 258 } 259 } 260 261 class IssueQueueWBWakeUpBundle(exuIndices: Seq[Int], backendParams: BackendParams) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, exuIndices) { 262 263 } 264 265 class IssueQueueIQWakeUpBundle(exuIdx: Int, backendParams: BackendParams) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, Seq(exuIdx)) { 266 def fromExuInput(exuInput: ExuInput, l2ExuVecs: Vec[Vec[Bool]]): Unit = { 267 this.rfWen := exuInput.rfWen.getOrElse(false.B) 268 this.fpWen := exuInput.fpWen.getOrElse(false.B) 269 this.vecWen := exuInput.vecWen.getOrElse(false.B) 270 this.pdest := exuInput.pdest 271 } 272 273 def fromExuInput(exuInput: ExuInput): Unit = { 274 this.rfWen := exuInput.rfWen.getOrElse(false.B) 275 this.fpWen := exuInput.fpWen.getOrElse(false.B) 276 this.vecWen := exuInput.vecWen.getOrElse(false.B) 277 this.pdest := exuInput.pdest 278 } 279 } 280 281 class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { 282 // vtype 283 val vill = Bool() 284 val vma = Bool() // 1: agnostic, 0: undisturbed 285 val vta = Bool() // 1: agnostic, 0: undisturbed 286 val vsew = VSew() 287 val vlmul = VLmul() // 1/8~8 --> -3~3 288 289 val vm = Bool() // 0: need v0.t 290 val vstart = Vl() 291 292 // float rounding mode 293 val frm = Frm() 294 // scalar float instr 295 val fpu = Fpu() 296 // vector fix int rounding mode 297 val vxrm = Vxrm() 298 // vector uop index, exclude other non-vector uop 299 val vuopIdx = UopIdx() 300 // maybe used if data dependancy 301 val vmask = UInt(MaskSrcData().dataWidth.W) 302 val vl = Vl() 303 304 // vector load/store 305 val nf = Nf() 306 307 val needScalaSrc = Bool() 308 val permImmTruncate = Bool() // opivi 309 310 val isReverse = Bool() // vrsub, vrdiv 311 val isExt = Bool() 312 val isNarrow = Bool() 313 val isDstMask = Bool() // vvm, vvvm, mmm 314 val isOpMask = Bool() // vmand, vmnand 315 val isMove = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i 316 317 def vtype: VType = { 318 val res = Wire(VType()) 319 res.illegal := this.vill 320 res.vma := this.vma 321 res.vta := this.vta 322 res.vsew := this.vsew 323 res.vlmul := this.vlmul 324 res 325 } 326 327 def vconfig: VConfig = { 328 val res = Wire(VConfig()) 329 res.vtype := this.vtype 330 res.vl := this.vl 331 res 332 } 333 } 334 335 // DynInst --[IssueQueue]--> DataPath 336 class IssueQueueIssueBundle( 337 iqParams: IssueBlockParams, 338 val exuParams: ExeUnitParams, 339 )(implicit 340 p: Parameters 341 ) extends Bundle { 342 private val rfReadDataCfgSet: Seq[Set[DataConfig]] = exuParams.getRfReadDataCfgSet 343 344 val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec( 345 rfReadDataCfgSet.map((set: Set[DataConfig]) => 346 MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, exuParams.rdPregIdxWidth)).toSeq) 347 ) 348 )) 349 350 val srcType = Vec(exuParams.numRegSrc, SrcType()) // used to select imm or reg data 351 val immType = SelImm() // used to select imm extractor 352 val common = new ExuInput(exuParams) 353 val jmp = if (exuParams.needPc) Some(Flipped(new IssueQueueJumpBundle)) else None 354 val addrOH = UInt(iqParams.numEntries.W) 355 356 def exuIdx = exuParams.exuIdx 357 def getSource: SchedulerType = exuParams.getWBSource 358 def getIntWbBusyBundle = common.rfWen.toSeq 359 def getVfWbBusyBundle = common.getVfWen.toSeq 360 def getIntRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readInt) 361 def getVfRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readVf) 362 363 def getIntRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 364 getIntRfReadBundle.zip(srcType).map { 365 case (rfRd: RfReadPortWithConfig, t: UInt) => 366 makeValid(issueValid && SrcType.isXp(t), rfRd) 367 } 368 } 369 370 def getVfRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 371 getVfRfReadBundle.zip(srcType).map { 372 case (rfRd: RfReadPortWithConfig, t: UInt) => 373 makeValid(issueValid && SrcType.isVfp(t), rfRd) 374 } 375 } 376 377 def getIntRfWriteValidBundle(issueValid: Bool) = { 378 379 } 380 } 381 382 class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle { 383 val issueQueueParams = this.params 384 val og0resp = Valid(new EntryDeqRespBundle) 385 val og1resp = Valid(new EntryDeqRespBundle) 386 } 387 388 class fuBusyRespBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 389 val respType = RSFeedbackType() // update credit if needs replay 390 val rfWen = Bool() // TODO: use params to identify IntWB/VfWB 391 val fuType = FuType() 392 } 393 394 class WbFuBusyTableWriteBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 395 private val intCertainLat = params.intLatencyCertain 396 private val vfCertainLat = params.vfLatencyCertain 397 private val intLat = params.intLatencyValMax 398 private val vfLat = params.vfLatencyValMax 399 400 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 401 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 402 val intDeqRespSet = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 403 val vfDeqRespSet = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 404 } 405 406 class WbFuBusyTableReadBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 407 private val intCertainLat = params.intLatencyCertain 408 private val vfCertainLat = params.vfLatencyCertain 409 private val intLat = params.intLatencyValMax 410 private val vfLat = params.vfLatencyValMax 411 412 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 413 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 414 } 415 416 class WbConflictBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 417 private val intCertainLat = params.intLatencyCertain 418 private val vfCertainLat = params.vfLatencyCertain 419 420 val intConflict = OptionWrapper(intCertainLat, Bool()) 421 val vfConflict = OptionWrapper(vfCertainLat, Bool()) 422 } 423 424 // DataPath --[ExuInput]--> Exu 425 class ExuInput(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 426 val fuType = FuType() 427 val fuOpType = FuOpType() 428 val src = Vec(params.numRegSrc, UInt(params.dataBitsMax.W)) 429 val imm = UInt(XLEN.W) 430 val robIdx = new RobPtr 431 val iqIdx = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet 432 val isFirstIssue = Bool() // Only used by store yet 433 val pdest = UInt(params.wbPregIdxWidth.W) 434 val rfWen = if (params.writeIntRf) Some(Bool()) else None 435 val fpWen = if (params.writeFpRf) Some(Bool()) else None 436 val vecWen = if (params.writeVecRf) Some(Bool()) else None 437 val fpu = if (params.writeFflags) Some(new FPUCtrlSignals) else None 438 val vpu = if (params.needVPUCtrl) Some(new VPUCtrlSignals) else None 439 val flushPipe = if (params.flushPipe) Some(Bool()) else None 440 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 441 val jalrTarget = if (params.hasJmpFu) Some(UInt(VAddrData().dataWidth.W)) else None 442 val preDecode = if (params.hasPredecode) Some(new PreDecodeInfo) else None 443 val ftqIdx = if (params.needPc || params.replayInst) 444 Some(new FtqPtr) else None 445 val ftqOffset = if (params.needPc || params.replayInst) 446 Some(UInt(log2Up(PredictWidth).W)) else None 447 val predictInfo = if (params.hasPredecode) Some(new Bundle { 448 val target = UInt(VAddrData().dataWidth.W) 449 val taken = Bool() 450 }) else None 451 val sqIdx = if (params.hasMemAddrFu || params.hasStdFu) Some(new SqPtr) else None 452 val lqIdx = if (params.hasMemAddrFu) Some(new LqPtr) else None 453 val dataSources = Vec(params.numRegSrc, DataSource()) 454 val l1ExuVec = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, ExuVec())) 455 val srcTimer = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, UInt(3.W))) 456 457 def exuIdx = this.params.exuIdx 458 459 def needCancel(og0CancelVec: Vec[Bool], og1CancelVec: Vec[Bool]) : Bool = { 460 if (params.isIQWakeUpSink) { 461 require( 462 og0CancelVec.size == l1ExuVec.get.head.size, 463 s"cancelVecSize: {og0: ${og0CancelVec.size}, og1: ${og1CancelVec.size}}" 464 ) 465 val l1Cancel: Bool = l1ExuVec.get.zip(srcTimer.get).map { 466 case(exuOH: Vec[Bool], srcTimer: UInt) => 467 (exuOH.asUInt & og0CancelVec.asUInt).orR && srcTimer === 1.U 468 }.reduce(_ | _) 469 l1Cancel 470 } else { 471 false.B 472 } 473 } 474 475 def getVfWen = { 476 if (params.writeFpRf) this.fpWen 477 else if(params.writeVecRf) this.vecWen 478 else None 479 } 480 481 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = { 482 // src is assigned to rfReadData 483 this.fuType := source.common.fuType 484 this.fuOpType := source.common.fuOpType 485 this.imm := source.common.imm 486 this.robIdx := source.common.robIdx 487 this.pdest := source.common.pdest 488 this.isFirstIssue := source.common.isFirstIssue // Only used by mem debug log 489 this.iqIdx := source.common.iqIdx // Only used by mem feedback 490 this.dataSources := source.common.dataSources 491 this.rfWen .foreach(_ := source.common.rfWen.get) 492 this.fpWen .foreach(_ := source.common.fpWen.get) 493 this.vecWen .foreach(_ := source.common.vecWen.get) 494 this.fpu .foreach(_ := source.common.fpu.get) 495 this.vpu .foreach(_ := source.common.vpu.get) 496 this.flushPipe .foreach(_ := source.common.flushPipe.get) 497 this.pc .foreach(_ := source.jmp.get.pc) 498 this.jalrTarget .foreach(_ := source.jmp.get.target) 499 this.preDecode .foreach(_ := source.common.preDecode.get) 500 this.ftqIdx .foreach(_ := source.common.ftqIdx.get) 501 this.ftqOffset .foreach(_ := source.common.ftqOffset.get) 502 this.predictInfo .foreach(_ := source.common.predictInfo.get) 503 this.lqIdx .foreach(_ := source.common.lqIdx.get) 504 this.sqIdx .foreach(_ := source.common.sqIdx.get) 505 this.l1ExuVec .foreach(_ := source.common.l1ExuVec.get) 506 this.srcTimer .foreach(_ := source.common.srcTimer.get) 507 } 508 } 509 510 // ExuInput --[FuncUnit]--> ExuOutput 511 class ExuOutput( 512 val params: ExeUnitParams, 513 )(implicit 514 val p: Parameters 515 ) extends Bundle with BundleSource with HasXSParameter { 516 val data = UInt(params.dataBitsMax.W) 517 val pdest = UInt(params.wbPregIdxWidth.W) 518 val robIdx = new RobPtr 519 val intWen = if (params.writeIntRf) Some(Bool()) else None 520 val fpWen = if (params.writeFpRf) Some(Bool()) else None 521 val vecWen = if (params.writeVecRf) Some(Bool()) else None 522 val redirect = if (params.hasRedirect) Some(ValidIO(new Redirect)) else None 523 val fflags = if (params.writeFflags) Some(UInt(5.W)) else None 524 val wflags = if (params.writeFflags) Some(Bool()) else None 525 val vxsat = if (params.writeVxsat) Some(Bool()) else None 526 val exceptionVec = if (params.exceptionOut.nonEmpty) Some(ExceptionVec()) else None 527 val flushPipe = if (params.flushPipe) Some(Bool()) else None 528 val replay = if (params.replayInst) Some(Bool()) else None 529 val lqIdx = if (params.hasLoadFu) Some(new LqPtr()) else None 530 val sqIdx = if (params.hasStoreAddrFu || params.hasStdFu) 531 Some(new SqPtr()) else None 532 val ftqIdx = if (params.needPc || params.replayInst) 533 Some(new FtqPtr) else None 534 val ftqOffset = if (params.needPc || params.replayInst) 535 Some(UInt(log2Up(PredictWidth).W)) else None 536 // uop info 537 val predecodeInfo = if(params.hasPredecode) Some(new PreDecodeInfo) else None 538 val debug = new DebugBundle 539 val debugInfo = new PerfDebugInfo 540 } 541 542 // ExuOutput + DynInst --> WriteBackBundle 543 class WriteBackBundle(val params: PregWB, backendParams: BackendParams)(implicit p: Parameters) extends Bundle with BundleSource { 544 val rfWen = Bool() 545 val fpWen = Bool() 546 val vecWen = Bool() 547 val pdest = UInt(params.pregIdxWidth(backendParams).W) 548 val data = UInt(params.dataWidth.W) 549 val robIdx = new RobPtr()(p) 550 val flushPipe = Bool() 551 val replayInst = Bool() 552 val redirect = ValidIO(new Redirect) 553 val fflags = UInt(5.W) 554 val vxsat = Bool() 555 val exceptionVec = ExceptionVec() 556 val debug = new DebugBundle 557 val debugInfo = new PerfDebugInfo 558 559 this.wakeupSource = s"WB(${params.toString})" 560 561 def fromExuOutput(source: ExuOutput) = { 562 this.rfWen := source.intWen.getOrElse(false.B) 563 this.fpWen := source.fpWen.getOrElse(false.B) 564 this.vecWen := source.vecWen.getOrElse(false.B) 565 this.pdest := source.pdest 566 this.data := source.data 567 this.robIdx := source.robIdx 568 this.flushPipe := source.flushPipe.getOrElse(false.B) 569 this.replayInst := source.replay.getOrElse(false.B) 570 this.redirect := source.redirect.getOrElse(0.U.asTypeOf(this.redirect)) 571 this.fflags := source.fflags.getOrElse(0.U.asTypeOf(this.fflags)) 572 this.vxsat := source.vxsat.getOrElse(0.U.asTypeOf(this.vxsat)) 573 this.exceptionVec := source.exceptionVec.getOrElse(0.U.asTypeOf(this.exceptionVec)) 574 this.debug := source.debug 575 this.debugInfo := source.debugInfo 576 } 577 578 def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 579 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(IntData()).addrWidth))) 580 rfWrite.wen := this.rfWen && fire 581 rfWrite.addr := this.pdest 582 rfWrite.data := this.data 583 rfWrite.intWen := this.rfWen 584 rfWrite.fpWen := false.B 585 rfWrite.vecWen := false.B 586 rfWrite 587 } 588 589 def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 590 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VecData()).addrWidth))) 591 rfWrite.wen := (this.fpWen || this.vecWen) && fire 592 rfWrite.addr := this.pdest 593 rfWrite.data := this.data 594 rfWrite.intWen := false.B 595 rfWrite.fpWen := this.fpWen 596 rfWrite.vecWen := this.vecWen 597 rfWrite 598 } 599 } 600 601 // ExuOutput --> ExuBypassBundle --[DataPath]-->ExuInput 602 // / 603 // [IssueQueue]--> ExuInput -- 604 class ExuBypassBundle( 605 val params: ExeUnitParams, 606 )(implicit 607 val p: Parameters 608 ) extends Bundle { 609 val data = UInt(params.dataBitsMax.W) 610 val pdest = UInt(params.wbPregIdxWidth.W) 611 } 612 613 class ExceptionInfo extends Bundle { 614 val pc = UInt(VAddrData().dataWidth.W) 615 val instr = UInt(32.W) 616 val commitType = CommitType() 617 val exceptionVec = ExceptionVec() 618 val singleStep = Bool() 619 val crossPageIPFFix = Bool() 620 val isInterrupt = Bool() 621 } 622 623 object UopIdx { 624 def apply()(implicit p: Parameters): UInt = UInt(log2Up(p(XSCoreParamsKey).MaxUopSize + 1).W) 625 } 626 627 object FuLatency { 628 def apply(): UInt = UInt(width.W) 629 630 def width = 4 // 0~15 // Todo: assosiate it with FuConfig 631 } 632 633 object ExuVec { 634 def apply(exuNum: Int): Vec[Bool] = Vec(exuNum, Bool()) 635 636 def apply()(implicit p: Parameters): Vec[Bool] = Vec(width, Bool()) 637 638 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 639 } 640 641 class MemExuInput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 642 val uop = new DynInst 643 val src = if (isVector) Vec(5, UInt(VLEN.W)) else Vec(3, UInt(XLEN.W)) 644 val iqIdx = UInt(log2Up(MemIQSizeMax).W) 645 val isFirstIssue = Bool() 646 } 647 648 class MemExuOutput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 649 val uop = new DynInst 650 val data = if (isVector) UInt(VLEN.W) else UInt(XLEN.W) 651 val debug = new DebugBundle 652 } 653 654 class MemMicroOpRbExt(implicit p: Parameters) extends XSBundle { 655 val uop = new DynInst 656 val flag = UInt(1.W) 657 } 658} 659