1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.regfile 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import xiangshan.backend.datapath.DataConfig.{DataConfig, FpData, IntData, VecData} 24import xiangshan.backend.Bundles.IssueQueueWakeUpBundle 25 26class RfReadPort(dataWidth: Int, addrWidth: Int) extends Bundle { 27 val addr = Input(UInt(addrWidth.W)) 28 val data = Output(UInt(dataWidth.W)) 29} 30 31class RfWritePort(dataWidth: Int, addrWidth: Int) extends Bundle { 32 val wen = Input(Bool()) 33 val addr = Input(UInt(addrWidth.W)) 34 val data = Input(UInt(dataWidth.W)) 35} 36 37class RfReadPortWithConfig(val rfReadDataCfg: DataConfig, addrWidth: Int) extends Bundle { 38 val addr: UInt = Input(UInt(addrWidth.W)) 39 val data: UInt = Output(UInt(rfReadDataCfg.dataWidth.W)) 40 val srcType: UInt = Input(UInt(3.W)) 41 42 def readInt: Boolean = rfReadDataCfg.isInstanceOf[IntData] 43 def readFp : Boolean = rfReadDataCfg.isInstanceOf[FpData] 44 def readVec: Boolean = rfReadDataCfg.isInstanceOf[VecData] 45} 46 47class RfWritePortWithConfig(val rfWriteDataCfg: DataConfig, addrWidth: Int) extends Bundle { 48 val wen = Input(Bool()) 49 val addr = Input(UInt(addrWidth.W)) 50 val data = Input(UInt(rfWriteDataCfg.dataWidth.W)) 51 val intWen = Input(Bool()) 52 val fpWen = Input(Bool()) 53 val vecWen = Input(Bool()) 54 def writeInt: Boolean = rfWriteDataCfg.isInstanceOf[IntData] 55 def writeFp : Boolean = rfWriteDataCfg.isInstanceOf[FpData] 56 def writeVec: Boolean = rfWriteDataCfg.isInstanceOf[VecData] 57 58 def toWakeUpBundle: ValidIO[IssueQueueWakeUpBundle] = { 59 val wakeup = Wire(ValidIO(new IssueQueueWakeUpBundle(addrWidth))) 60 wakeup.bits.pdest := this.addr 61 wakeup.bits.rfWen := this.intWen && this.wen 62 wakeup.bits.fpWen := this.fpWen && this.wen 63 wakeup.bits.vecWen := this.vecWen && this.wen 64 wakeup.valid := this.wen 65 wakeup 66 } 67} 68 69class Regfile 70( 71 name: String, 72 numPregs: Int, 73 numReadPorts: Int, 74 numWritePorts: Int, 75 hasZero: Boolean, 76 len: Int, 77 width: Int, 78) extends Module { 79 val io = IO(new Bundle() { 80 val readPorts = Vec(numReadPorts, new RfReadPort(len, width)) 81 val writePorts = Vec(numWritePorts, new RfWritePort(len, width)) 82 val debug_rports = Vec(65, new RfReadPort(len, width)) 83 }) 84 85 println(name + ": size:" + numPregs + " read: " + numReadPorts + " write: " + numWritePorts) 86 87 val mem = Reg(Vec(numPregs, UInt(len.W))) 88 for (r <- io.readPorts) { 89 val rdata = if (hasZero) Mux(r.addr === 0.U, 0.U, mem(r.addr)) else mem(r.addr) 90 r.data := RegNext(rdata) 91 } 92 for (w <- io.writePorts) { 93 when(w.wen) { 94 mem(w.addr) := w.data 95 } 96 } 97 98 for (rport <- io.debug_rports) { 99 val zero_rdata = Mux(rport.addr === 0.U, 0.U, mem(rport.addr)) 100 rport.data := (if (hasZero) zero_rdata else mem(rport.addr)) 101 } 102} 103 104object Regfile { 105 // non-return version 106 def apply( 107 name : String, 108 numEntries : Int, 109 raddr : Seq[UInt], 110 rdata : Vec[UInt], 111 wen : Seq[Bool], 112 waddr : Seq[UInt], 113 wdata : Seq[UInt], 114 hasZero : Boolean, 115 withReset : Boolean = false, 116 debugReadAddr: Option[Seq[UInt]], 117 debugReadData: Option[Vec[UInt]], 118 )(implicit p: Parameters): Unit = { 119 val numReadPorts = raddr.length 120 val numWritePorts = wen.length 121 require(wen.length == waddr.length) 122 require(wen.length == wdata.length) 123 val dataBits = wdata.map(_.getWidth).min 124 require(wdata.map(_.getWidth).min == wdata.map(_.getWidth).max, s"dataBits != $dataBits") 125 val addrBits = waddr.map(_.getWidth).min 126 require(waddr.map(_.getWidth).min == waddr.map(_.getWidth).max, s"addrBits != $addrBits") 127 128 val regfile = Module(new Regfile(name, numEntries, numReadPorts, numWritePorts, hasZero, dataBits, addrBits)) 129 rdata := regfile.io.readPorts.zip(raddr).map { case (rport, addr) => 130 rport.addr := addr 131 rport.data 132 } 133 134 regfile.io.writePorts.zip(wen).zip(waddr).zip(wdata).foreach{ case (((wport, en), addr), data) => 135 wport.wen := en 136 wport.addr := addr 137 wport.data := data 138 } 139 if (withReset) { 140 val numResetCycles = math.ceil(numEntries / numWritePorts).toInt 141 val resetCounter = RegInit(numResetCycles.U) 142 val resetWaddr = RegInit(VecInit((0 until numWritePorts).map(_.U(log2Up(numEntries + 1).W)))) 143 val inReset = resetCounter =/= 0.U 144 when (inReset) { 145 resetCounter := resetCounter - 1.U 146 resetWaddr := VecInit(resetWaddr.map(_ + numWritePorts.U)) 147 } 148 when (!inReset) { 149 resetWaddr.map(_ := 0.U) 150 } 151 for ((wport, i) <- regfile.io.writePorts.zipWithIndex) { 152 wport.wen := inReset || wen(i) 153 wport.addr := Mux(inReset, resetWaddr(i), waddr(i)) 154 wport.data := wdata(i) 155 } 156 } 157 158 require(debugReadAddr.nonEmpty == debugReadData.nonEmpty, "Both debug addr and data bundles should be empty or not") 159 regfile.io.debug_rports := DontCare 160 if (debugReadAddr.nonEmpty && debugReadData.nonEmpty) { 161 debugReadData.get := VecInit(regfile.io.debug_rports.zip(debugReadAddr.get).map { case (rport, addr) => 162 rport.addr := addr 163 rport.data 164 }) 165 } 166 } 167} 168 169object IntRegFile { 170 // non-return version 171 def apply( 172 name : String, 173 numEntries : Int, 174 raddr : Seq[UInt], 175 rdata : Vec[UInt], 176 wen : Seq[Bool], 177 waddr : Seq[UInt], 178 wdata : Seq[UInt], 179 debugReadAddr: Option[Seq[UInt]], 180 debugReadData: Option[Vec[UInt]], 181 withReset : Boolean = false, 182 )(implicit p: Parameters): Unit = { 183 Regfile( 184 name, numEntries, raddr, rdata, wen, waddr, wdata, 185 hasZero = true, withReset, debugReadAddr, debugReadData) 186 } 187} 188 189object VfRegFile { 190 // non-return version 191 def apply( 192 name : String, 193 numEntries : Int, 194 splitNum : Int, 195 raddr : Seq[UInt], 196 rdata : Vec[UInt], 197 wen : Seq[Seq[Bool]], 198 waddr : Seq[UInt], 199 wdata : Seq[UInt], 200 debugReadAddr: Option[Seq[UInt]], 201 debugReadData: Option[Vec[UInt]], 202 withReset : Boolean = false, 203 )(implicit p: Parameters): Unit = { 204 require(splitNum >= 1, "splitNum should be no less than 1") 205 require(splitNum == wen.length, "splitNum should be equal to length of wen vec") 206 if (splitNum == 1) { 207 Regfile( 208 name, numEntries, raddr, rdata, wen.head, waddr, wdata, 209 hasZero = false, withReset, debugReadAddr, debugReadData) 210 } else { 211 val dataWidth = 64 212 val numReadPorts = raddr.length 213 require(splitNum > 1 && wdata.head.getWidth == dataWidth * splitNum) 214 val wdataVec = Wire(Vec(splitNum, Vec(wdata.length, UInt(dataWidth.W)))) 215 val rdataVec = Wire(Vec(splitNum, Vec(raddr.length, UInt(dataWidth.W)))) 216 val debugRDataVec: Option[Vec[Vec[UInt]]] = debugReadData.map(x => Wire(Vec(splitNum, Vec(x.length, UInt(dataWidth.W))))) 217 for (i <- 0 until splitNum) { 218 wdataVec(i) := wdata.map(_ ((i + 1) * dataWidth - 1, i * dataWidth)) 219 Regfile( 220 name + s"Part${i}", numEntries, raddr, rdataVec(i), wen(i), waddr, wdataVec(i), 221 hasZero = false, withReset, debugReadAddr, debugRDataVec.map(_(i)) 222 ) 223 } 224 for (i <- 0 until rdata.length) { 225 rdata(i) := Cat(rdataVec.map(_ (i)).reverse) 226 } 227 if (debugReadData.nonEmpty) { 228 for (i <- 0 until debugReadData.get.length) { 229 debugReadData.get(i) := Cat(debugRDataVec.get.map(_ (i)).reverse) 230 } 231 } 232 } 233 } 234}