1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.rename 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utility._ 23import utils._ 24import xiangshan._ 25import xiangshan.backend.decode.{FusionDecodeInfo, Imm_I, Imm_LUI_LOAD, Imm_U} 26import xiangshan.backend.fu.FuType 27import xiangshan.backend.rename.freelist._ 28import xiangshan.backend.rob.RobPtr 29import xiangshan.backend.rename.freelist._ 30import xiangshan.mem.mdp._ 31import xiangshan.backend.Bundles.{DecodedInst, DynInst} 32 33class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelper with HasPerfEvents { 34 private val numRegSrc = backendParams.numRegSrc 35 // Todo: move it 36 private val vecOldVdIdx = 2 37 38 println(s"[Rename] numRegSrc: $numRegSrc") 39 40 val io = IO(new Bundle() { 41 val redirect = Flipped(ValidIO(new Redirect)) 42 val robCommits = Input(new RobCommitIO) 43 // from decode 44 val in = Vec(RenameWidth, Flipped(DecoupledIO(new DecodedInst))) 45 val fusionInfo = Vec(DecodeWidth - 1, Flipped(new FusionDecodeInfo)) 46 // ssit read result 47 val ssit = Flipped(Vec(RenameWidth, Output(new SSITEntry))) 48 // waittable read result 49 val waittable = Flipped(Vec(RenameWidth, Output(Bool()))) 50 // to rename table 51 val intReadPorts = Vec(RenameWidth, Vec(3, Input(UInt(PhyRegIdxWidth.W)))) 52 val fpReadPorts = Vec(RenameWidth, Vec(4, Input(UInt(PhyRegIdxWidth.W)))) 53 val vecReadPorts = Vec(RenameWidth, Vec(5, Input(UInt(PhyRegIdxWidth.W)))) 54 val intRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 55 val fpRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 56 val vecRenamePorts = Vec(RenameWidth, Output(new RatWritePort)) 57 // to dispatch1 58 val out = Vec(RenameWidth, DecoupledIO(new DynInst)) 59 // debug arch ports 60 val debug_int_rat = Vec(32, Input(UInt(PhyRegIdxWidth.W))) 61 val debug_vconfig_rat = Input(UInt(PhyRegIdxWidth.W)) 62 val debug_fp_rat = Vec(32, Input(UInt(PhyRegIdxWidth.W))) 63 val debug_vec_rat = Vec(32, Input(UInt(PhyRegIdxWidth.W))) 64 }) 65 66 // create free list and rat 67 val intFreeList = Module(new MEFreeList(NRPhyRegs)) 68 val intRefCounter = Module(new RefCounter(NRPhyRegs)) 69 val fpFreeList = Module(new StdFreeList(NRPhyRegs - FpLogicRegs - VecLogicRegs)) 70 71 intRefCounter.io.commit <> io.robCommits 72 intRefCounter.io.redirect := io.redirect.valid 73 intRefCounter.io.debug_int_rat <> io.debug_int_rat 74 intFreeList.io.commit <> io.robCommits 75 intFreeList.io.debug_rat <> io.debug_int_rat 76 fpFreeList.io.commit <> io.robCommits 77 fpFreeList.io.debug_rat <> io.debug_fp_rat 78 79 // decide if given instruction needs allocating a new physical register (CfCtrl: from decode; RobCommitInfo: from rob) 80 // fp and vec share `fpFreeList` 81 def needDestReg[T <: DecodedInst](reg_t: RegType, x: T): Bool = reg_t match { 82 case Reg_I => x.rfWen && x.ldest =/= 0.U 83 case Reg_F => x.fpWen 84 case Reg_V => x.vecWen 85 } 86 def needDestRegCommit[T <: RobCommitInfo](reg_t: RegType, x: T): Bool = { 87 reg_t match { 88 case Reg_I => x.rfWen 89 case Reg_F => x.fpWen 90 case Reg_V => x.vecWen 91 } 92 } 93 def needDestRegWalk[T <: RobCommitInfo](reg_t: RegType, x: T): Bool = { 94 reg_t match { 95 case Reg_I => x.rfWen && x.ldest =/= 0.U 96 case Reg_F => x.fpWen 97 case Reg_V => x.vecWen 98 } 99 } 100 101 // connect [redirect + walk] ports for __float point__ & __integer__ free list 102 Seq(fpFreeList, intFreeList).foreach { case fl => 103 fl.io.redirect := io.redirect.valid 104 fl.io.walk := io.robCommits.isWalk 105 } 106 // only when both fp and int free list and dispatch1 has enough space can we do allocation 107 // when isWalk, freelist can definitely allocate 108 intFreeList.io.doAllocate := fpFreeList.io.canAllocate && io.out(0).ready || io.robCommits.isWalk 109 fpFreeList.io.doAllocate := intFreeList.io.canAllocate && io.out(0).ready || io.robCommits.isWalk 110 111 // dispatch1 ready ++ float point free list ready ++ int free list ready ++ not walk 112 val canOut = io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk 113 114 115 // speculatively assign the instruction with an robIdx 116 val validCount = PopCount(io.in.map(in => in.valid && in.bits.lastUop)) // number of instructions waiting to enter rob (from decode) 117 val robIdxHead = RegInit(0.U.asTypeOf(new RobPtr)) 118 val lastCycleMisprediction = RegNext(io.redirect.valid && !io.redirect.bits.flushItself()) 119 val robIdxHeadNext = Mux(io.redirect.valid, io.redirect.bits.robIdx, // redirect: move ptr to given rob index 120 Mux(lastCycleMisprediction, robIdxHead + 1.U, // mis-predict: not flush robIdx itself 121 Mux(canOut, robIdxHead + validCount, // instructions successfully entered next stage: increase robIdx 122 /* default */ robIdxHead))) // no instructions passed by this cycle: stick to old value 123 robIdxHead := robIdxHeadNext 124 125 /** 126 * Rename: allocate free physical register and update rename table 127 */ 128 val uops = Wire(Vec(RenameWidth, new DynInst)) 129 uops.foreach( uop => { 130 uop.srcState := DontCare 131 uop.robIdx := DontCare 132 uop.debugInfo := DontCare 133 uop.lqIdx := DontCare 134 uop.sqIdx := DontCare 135 uop.waitForRobIdx := DontCare 136 uop.singleStep := DontCare 137 }) 138 139 require(RenameWidth >= CommitWidth) 140 val needVecDest = Wire(Vec(RenameWidth, Bool())) 141 val needFpDest = Wire(Vec(RenameWidth, Bool())) 142 val needIntDest = Wire(Vec(RenameWidth, Bool())) 143 val hasValid = Cat(io.in.map(_.valid)).orR 144 145 val isMove = io.in.map(_.bits.isMove) 146 147 val walkNeedIntDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 148 val walkNeedFpDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 149 val walkNeedVecDest = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 150 val walkIsMove = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 151 152 val intSpecWen = Wire(Vec(RenameWidth, Bool())) 153 val fpSpecWen = Wire(Vec(RenameWidth, Bool())) 154 val vecSpecWen = Wire(Vec(RenameWidth, Bool())) 155 156 val walkIntSpecWen = WireDefault(VecInit(Seq.fill(RenameWidth)(false.B))) 157 158 val walkPdest = Wire(Vec(RenameWidth, UInt(PhyRegIdxWidth.W))) 159 160 // uop calculation 161 for (i <- 0 until RenameWidth) { 162 for ((name, data) <- uops(i).elements) { 163 if (io.in(i).bits.elements.contains(name)) { 164 data := io.in(i).bits.elements(name) 165 } 166 } 167 168 // update cf according to ssit result 169 uops(i).storeSetHit := io.ssit(i).valid 170 uops(i).loadWaitStrict := io.ssit(i).strict && io.ssit(i).valid 171 uops(i).ssid := io.ssit(i).ssid 172 173 // update cf according to waittable result 174 uops(i).loadWaitBit := io.waittable(i) 175 176 uops(i).replayInst := false.B // set by IQ or MemQ 177 // alloc a new phy reg, fp and vec share the `fpFreeList` 178 needVecDest (i) := io.in(i).valid && needDestReg(Reg_V, io.in(i).bits) 179 needFpDest (i) := io.in(i).valid && needDestReg(Reg_F, io.in(i).bits) 180 needIntDest (i) := io.in(i).valid && needDestReg(Reg_I, io.in(i).bits) 181 if (i < CommitWidth) { 182 walkNeedIntDest(i) := io.robCommits.walkValid(i) && needDestRegWalk(Reg_I, io.robCommits.info(i)) 183 walkNeedFpDest(i) := io.robCommits.walkValid(i) && needDestRegWalk(Reg_F, io.robCommits.info(i)) 184 walkNeedVecDest(i) := io.robCommits.walkValid(i) && needDestRegWalk(Reg_V, io.robCommits.info(i)) 185 walkIsMove(i) := io.robCommits.info(i).isMove 186 } 187 fpFreeList.io.allocateReq(i) := Mux(io.robCommits.isWalk, walkNeedFpDest(i) || walkNeedVecDest(i), needFpDest(i) || needVecDest(i)) 188 intFreeList.io.allocateReq(i) := Mux(io.robCommits.isWalk, walkNeedIntDest(i) && !walkIsMove(i), needIntDest(i) && !isMove(i)) 189 190 // no valid instruction from decode stage || all resources (dispatch1 + both free lists) ready 191 io.in(i).ready := !hasValid || canOut 192 193 uops(i).robIdx := robIdxHead + PopCount(io.in.take(i).map(in => in.valid && in.bits.lastUop)) 194 195 uops(i).psrc(0) := Mux1H(uops(i).srcType(0), Seq(io.intReadPorts(i)(0), io.fpReadPorts(i)(0), io.vecReadPorts(i)(0))) 196 uops(i).psrc(1) := Mux1H(uops(i).srcType(1), Seq(io.intReadPorts(i)(1), io.fpReadPorts(i)(1), io.vecReadPorts(i)(1))) 197 uops(i).psrc(2) := Mux1H(uops(i).srcType(2)(2, 1), Seq(io.fpReadPorts(i)(2), io.vecReadPorts(i)(2))) 198 uops(i).psrc(3) := io.vecReadPorts(i)(3) 199 uops(i).psrc(4) := io.vecReadPorts(i)(4) // Todo: vl read port 200 201 // int psrc2 should be bypassed from next instruction if it is fused 202 if (i < RenameWidth - 1) { 203 when (io.fusionInfo(i).rs2FromRs2 || io.fusionInfo(i).rs2FromRs1) { 204 uops(i).psrc(1) := Mux(io.fusionInfo(i).rs2FromRs2, io.intReadPorts(i + 1)(1), io.intReadPorts(i + 1)(0)) 205 }.elsewhen(io.fusionInfo(i).rs2FromZero) { 206 uops(i).psrc(1) := 0.U 207 } 208 } 209 uops(i).oldPdest := Mux1H(Seq( 210 uops(i).rfWen -> io.intReadPorts(i).last, 211 uops(i).fpWen -> io.fpReadPorts (i).last, 212 uops(i).vecWen -> io.vecReadPorts(i)(vecOldVdIdx), 213 )) 214 uops(i).eliminatedMove := isMove(i) 215 216 // update pdest 217 uops(i).pdest := MuxCase(0.U, Seq( 218 needIntDest(i) -> intFreeList.io.allocatePhyReg(i), 219 (needFpDest(i) || needVecDest(i)) -> fpFreeList.io.allocatePhyReg(i), 220 )) 221 222 // Assign performance counters 223 uops(i).debugInfo.renameTime := GTimer() 224 225 io.out(i).valid := io.in(i).valid && intFreeList.io.canAllocate && fpFreeList.io.canAllocate && !io.robCommits.isWalk 226 io.out(i).bits := uops(i) 227 // Todo: move these shit in decode stage 228 // dirty code for fence. The lsrc is passed by imm. 229 when (io.out(i).bits.fuType === FuType.fence.U) { 230 io.out(i).bits.imm := Cat(io.in(i).bits.lsrc(1), io.in(i).bits.lsrc(0)) 231 } 232 233 // dirty code for SoftPrefetch (prefetch.r/prefetch.w) 234// when (io.in(i).bits.isSoftPrefetch) { 235// io.out(i).bits.fuType := FuType.ldu.U 236// io.out(i).bits.fuOpType := Mux(io.in(i).bits.lsrc(1) === 1.U, LSUOpType.prefetch_r, LSUOpType.prefetch_w) 237// io.out(i).bits.selImm := SelImm.IMM_S 238// io.out(i).bits.imm := Cat(io.in(i).bits.imm(io.in(i).bits.imm.getWidth - 1, 5), 0.U(5.W)) 239// } 240 241 // write speculative rename table 242 // we update rat later inside commit code 243 intSpecWen(i) := needIntDest(i) && intFreeList.io.canAllocate && intFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 244 fpSpecWen(i) := needFpDest(i) && fpFreeList.io.canAllocate && fpFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 245 vecSpecWen(i) := needVecDest(i) && fpFreeList.io.canAllocate && fpFreeList.io.doAllocate && !io.robCommits.isWalk && !io.redirect.valid 246 247 if (i < CommitWidth) { 248 walkIntSpecWen(i) := walkNeedIntDest(i) && !io.redirect.valid 249 walkPdest(i) := io.robCommits.info(i).pdest 250 } else { 251 walkPdest(i) := io.out(i).bits.pdest 252 } 253 254 intRefCounter.io.allocate(i).valid := Mux(io.robCommits.isWalk, walkIntSpecWen(i), intSpecWen(i)) 255 intRefCounter.io.allocate(i).bits := Mux(io.robCommits.isWalk, walkPdest(i), io.out(i).bits.pdest) 256 } 257 258 /** 259 * How to set psrc: 260 * - bypass the pdest to psrc if previous instructions write to the same ldest as lsrc 261 * - default: psrc from RAT 262 * How to set pdest: 263 * - Mux(isMove, psrc, pdest_from_freelist). 264 * 265 * The critical path of rename lies here: 266 * When move elimination is enabled, we need to update the rat with psrc. 267 * However, psrc maybe comes from previous instructions' pdest, which comes from freelist. 268 * 269 * If we expand these logic for pdest(N): 270 * pdest(N) = Mux(isMove(N), psrc(N), freelist_out(N)) 271 * = Mux(isMove(N), Mux(bypass(N, N - 1), pdest(N - 1), 272 * Mux(bypass(N, N - 2), pdest(N - 2), 273 * ... 274 * Mux(bypass(N, 0), pdest(0), 275 * rat_out(N))...)), 276 * freelist_out(N)) 277 */ 278 // a simple functional model for now 279 io.out(0).bits.pdest := Mux(isMove(0), uops(0).psrc.head, uops(0).pdest) 280 281 // psrc(n) + pdest(1) 282 val bypassCond: Vec[MixedVec[UInt]] = Wire(Vec(numRegSrc + 1, MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))))) 283 require(io.in(0).bits.srcType.size == io.in(0).bits.numSrc) 284 private val pdestLoc = io.in.head.bits.srcType.size // 2 vector src: v0, vl&vtype 285 println(s"[Rename] idx of pdest in bypassCond $pdestLoc") 286 for (i <- 1 until RenameWidth) { 287 val vecCond = io.in(i).bits.srcType.map(_ === SrcType.vp) :+ needVecDest(i) 288 val fpCond = io.in(i).bits.srcType.map(_ === SrcType.fp) :+ needFpDest(i) 289 val intCond = io.in(i).bits.srcType.map(_ === SrcType.xp) :+ needIntDest(i) 290 val target = io.in(i).bits.lsrc :+ io.in(i).bits.ldest 291 for (((((cond1, cond2), cond3), t), j) <- vecCond.zip(fpCond).zip(intCond).zip(target).zipWithIndex) { 292 val destToSrc = io.in.take(i).zipWithIndex.map { case (in, j) => 293 val indexMatch = in.bits.ldest === t 294 val writeMatch = cond3 && needIntDest(j) || cond2 && needFpDest(j) || cond1 && needVecDest(j) 295 indexMatch && writeMatch 296 } 297 bypassCond(j)(i - 1) := VecInit(destToSrc).asUInt 298 } 299 io.out(i).bits.psrc(0) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(0)(i-1).asBools).foldLeft(uops(i).psrc(0)) { 300 (z, next) => Mux(next._2, next._1, z) 301 } 302 io.out(i).bits.psrc(1) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(1)(i-1).asBools).foldLeft(uops(i).psrc(1)) { 303 (z, next) => Mux(next._2, next._1, z) 304 } 305 io.out(i).bits.psrc(2) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(2)(i-1).asBools).foldLeft(uops(i).psrc(2)) { 306 (z, next) => Mux(next._2, next._1, z) 307 } 308 io.out(i).bits.psrc(3) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(3)(i-1).asBools).foldLeft(uops(i).psrc(3)) { 309 (z, next) => Mux(next._2, next._1, z) 310 } 311 io.out(i).bits.psrc(4) := io.out.take(i).map(_.bits.pdest).zip(bypassCond(4)(i-1).asBools).foldLeft(uops(i).psrc(4)) { 312 (z, next) => Mux(next._2, next._1, z) 313 } 314 io.out(i).bits.oldPdest := io.out.take(i).map(_.bits.pdest).zip(bypassCond(pdestLoc)(i-1).asBools).foldLeft(uops(i).oldPdest) { 315 (z, next) => Mux(next._2, next._1, z) 316 } 317 io.out(i).bits.pdest := Mux(isMove(i), io.out(i).bits.psrc(0), uops(i).pdest) 318 319 // Todo: better implementation for fields reuse 320 // For fused-lui-load, load.src(0) is replaced by the imm. 321 val last_is_lui = io.in(i - 1).bits.selImm === SelImm.IMM_U && io.in(i - 1).bits.srcType(0) =/= SrcType.pc 322 val this_is_load = io.in(i).bits.fuType === FuType.ldu.U 323 val lui_to_load = io.in(i - 1).valid && io.in(i - 1).bits.ldest === io.in(i).bits.lsrc(0) 324 val fused_lui_load = last_is_lui && this_is_load && lui_to_load && false.B // Todo: enable it 325 when (fused_lui_load) { 326 // The first LOAD operand (base address) is replaced by LUI-imm and stored in {psrc, imm} 327 val lui_imm = io.in(i - 1).bits.imm(19, 0) 328 val ld_imm = io.in(i).bits.imm 329 io.out(i).bits.srcType(0) := SrcType.imm 330 io.out(i).bits.imm := Imm_LUI_LOAD().immFromLuiLoad(lui_imm, ld_imm) 331 val psrcWidth = uops(i).psrc.head.getWidth 332 val lui_imm_in_imm = 20/*Todo: uops(i).imm.getWidth*/ - Imm_I().len 333 val left_lui_imm = Imm_U().len - lui_imm_in_imm 334 require(2 * psrcWidth >= left_lui_imm, "cannot fused lui and load with psrc") 335 io.out(i).bits.psrc(0) := lui_imm(lui_imm_in_imm + psrcWidth - 1, lui_imm_in_imm) 336 io.out(i).bits.psrc(1) := lui_imm(lui_imm.getWidth - 1, lui_imm_in_imm + psrcWidth) 337 } 338 339 } 340 341 /** 342 * Instructions commit: update freelist and rename table 343 */ 344 for (i <- 0 until CommitWidth) { 345 val commitValid = io.robCommits.isCommit && io.robCommits.commitValid(i) 346 val walkValid = io.robCommits.isWalk && io.robCommits.walkValid(i) 347 348 // I. RAT Update 349 // When redirect happens (mis-prediction), don't update the rename table 350 io.intRenamePorts(i).wen := intSpecWen(i) 351 io.intRenamePorts(i).addr := uops(i).ldest 352 io.intRenamePorts(i).data := io.out(i).bits.pdest 353 354 io.fpRenamePorts(i).wen := fpSpecWen(i) 355 io.fpRenamePorts(i).addr := uops(i).ldest 356 io.fpRenamePorts(i).data := fpFreeList.io.allocatePhyReg(i) 357 358 io.vecRenamePorts(i).wen := vecSpecWen(i) 359 io.vecRenamePorts(i).addr := uops(i).ldest 360 io.vecRenamePorts(i).data := fpFreeList.io.allocatePhyReg(i) 361 362 // II. Free List Update 363 intFreeList.io.freeReq(i) := intRefCounter.io.freeRegs(i).valid 364 intFreeList.io.freePhyReg(i) := intRefCounter.io.freeRegs(i).bits 365 fpFreeList.io.freeReq(i) := commitValid && (needDestRegCommit(Reg_F, io.robCommits.info(i)) || needDestRegCommit(Reg_V, io.robCommits.info(i))) 366 fpFreeList.io.freePhyReg(i) := io.robCommits.info(i).old_pdest 367 368 intRefCounter.io.deallocate(i).valid := commitValid && needDestRegCommit(Reg_I, io.robCommits.info(i)) && !io.robCommits.isWalk 369 intRefCounter.io.deallocate(i).bits := io.robCommits.info(i).old_pdest 370 } 371 372 when(io.robCommits.isWalk) { 373 (intFreeList.io.allocateReq zip intFreeList.io.allocatePhyReg).take(CommitWidth) zip io.robCommits.info foreach { 374 case ((reqValid, allocReg), commitInfo) => when(reqValid) { 375 XSError(allocReg =/= commitInfo.pdest, "walk alloc reg =/= rob reg\n") 376 } 377 } 378 (fpFreeList.io.allocateReq zip fpFreeList.io.allocatePhyReg).take(CommitWidth) zip io.robCommits.info foreach { 379 case ((reqValid, allocReg), commitInfo) => when(reqValid) { 380 XSError(allocReg =/= commitInfo.pdest, "walk alloc reg =/= rob reg\n") 381 } 382 } 383 } 384 385 /* 386 Debug and performance counters 387 */ 388 def printRenameInfo(in: DecoupledIO[DecodedInst], out: DecoupledIO[DynInst]) = { 389 XSInfo(out.fire, p"pc:${Hexadecimal(in.bits.pc)} in(${in.valid},${in.ready}) " + 390 p"lsrc(0):${in.bits.lsrc(0)} -> psrc(0):${out.bits.psrc(0)} " + 391 p"lsrc(1):${in.bits.lsrc(1)} -> psrc(1):${out.bits.psrc(1)} " + 392 p"lsrc(2):${in.bits.lsrc(2)} -> psrc(2):${out.bits.psrc(2)} " + 393 p"ldest:${in.bits.ldest} -> pdest:${out.bits.pdest} " + 394 p"old_pdest:${out.bits.oldPdest}\n" 395 // Todo: add no lsrc -> psrc map print 396 ) 397 } 398 399 for ((x,y) <- io.in.zip(io.out)) { 400 printRenameInfo(x, y) 401 } 402 403 XSDebug(io.robCommits.isWalk, p"Walk Recovery Enabled\n") 404 XSDebug(io.robCommits.isWalk, p"validVec:${Binary(io.robCommits.walkValid.asUInt)}\n") 405 for (i <- 0 until CommitWidth) { 406 val info = io.robCommits.info(i) 407 XSDebug(io.robCommits.isWalk && io.robCommits.walkValid(i), p"[#$i walk info] pc:${Hexadecimal(info.pc)} " + 408 p"ldest:${info.ldest} rfWen:${info.rfWen} fpWen:${info.fpWen} vecWen:${info.vecWen}" + 409 p"pdest:${info.pdest} old_pdest:${info.old_pdest}\n") 410 } 411 412 XSDebug(p"inValidVec: ${Binary(Cat(io.in.map(_.valid)))}\n") 413 414 XSPerfAccumulate("in", Mux(RegNext(io.in(0).ready), PopCount(io.in.map(_.valid)), 0.U)) 415 XSPerfAccumulate("utilization", PopCount(io.in.map(_.valid))) 416 XSPerfAccumulate("waitInstr", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready))) 417 XSPerfAccumulate("stall_cycle_dispatch", hasValid && !io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk) 418 XSPerfAccumulate("stall_cycle_fp", hasValid && io.out(0).ready && !fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk) 419 XSPerfAccumulate("stall_cycle_int", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && !intFreeList.io.canAllocate && !io.robCommits.isWalk) 420 XSPerfAccumulate("stall_cycle_walk", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && io.robCommits.isWalk) 421 XSPerfAccumulate("recovery_bubbles", PopCount(io.in.map(_.valid && io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && io.robCommits.isWalk))) 422 423 XSPerfHistogram("slots_fire", PopCount(io.out.map(_.fire)), true.B, 0, RenameWidth+1, 1) 424 // Explaination: when out(0) not fire, PopCount(valid) is not meaningfull 425 XSPerfHistogram("slots_valid_pure", PopCount(io.in.map(_.valid)), io.out(0).fire, 0, RenameWidth+1, 1) 426 XSPerfHistogram("slots_valid_rough", PopCount(io.in.map(_.valid)), true.B, 0, RenameWidth+1, 1) 427 428 XSPerfAccumulate("move_instr_count", PopCount(io.out.map(out => out.fire && out.bits.isMove))) 429 val is_fused_lui_load = io.out.map(o => o.fire && o.bits.fuType === FuType.ldu.U && o.bits.srcType(0) === SrcType.imm) 430 XSPerfAccumulate("fused_lui_load_instr_count", PopCount(is_fused_lui_load)) 431 432 433 val renamePerf = Seq( 434 ("rename_in ", PopCount(io.in.map(_.valid & io.in(0).ready )) ), 435 ("rename_waitinstr ", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready)) ), 436 ("rename_stall_cycle_dispatch", hasValid && !io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk), 437 ("rename_stall_cycle_fp ", hasValid && io.out(0).ready && !fpFreeList.io.canAllocate && intFreeList.io.canAllocate && !io.robCommits.isWalk), 438 ("rename_stall_cycle_int ", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && !intFreeList.io.canAllocate && !io.robCommits.isWalk), 439 ("rename_stall_cycle_walk ", hasValid && io.out(0).ready && fpFreeList.io.canAllocate && intFreeList.io.canAllocate && io.robCommits.isWalk) 440 ) 441 val intFlPerf = intFreeList.getPerfEvents 442 val fpFlPerf = fpFreeList.getPerfEvents 443 val perfEvents = renamePerf ++ intFlPerf ++ fpFlPerf 444 generatePerfEvent() 445} 446