1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import xiangshan.backend.fu.FuType 30import freechips.rocketchip.rocket.Instructions._ 31import xiangshan.backend.Bundles.{DecodedInst, StaticInst} 32import xiangshan.backend.fu.vector.Bundles.VType 33import yunsuan.VpermType 34 35import scala.collection.Seq 36 37trait VectorConstants { 38 val MAX_VLMUL = 8 39 val FP_TMP_REG_MV = 32 40 val VECTOR_TMP_REG_LMUL = 32 // 32~38 -> 7 41 val VECTOR_VCONFIG = 39 42} 43 44class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 45 val enq = new Bundle { val staticInst = Input(new StaticInst) } 46 val vtype = Input(new VType) 47 val isComplex = Input(Vec(DecodeWidth - 1, Bool())) 48 val validFromIBuf = Input(Vec(DecodeWidth, Bool())) 49 val readyFromRename = Input(Vec(RenameWidth, Bool())) 50 val deq = new Bundle { 51 val decodedInsts = Output(Vec(RenameWidth, new DecodedInst)) 52 val isVset = Output(Bool()) 53 val readyToIBuf = Output(Vec(DecodeWidth, Bool())) 54 val validToRename = Output(Vec(RenameWidth, Bool())) 55 val complexNum = Output(UInt(3.W)) 56 } 57 val csrCtrl = Input(new CustomCSRCtrlIO) 58} 59/** 60 * @author zly 61 */ 62class DecodeUnitComp()(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 63 val io = IO(new DecodeUnitCompIO) 64 65 val maxUopSize = MaxUopSize 66 //input bits 67 val staticInst = Wire(new StaticInst) 68 69 staticInst := io.enq.staticInst 70 71 val src1 = Cat(0.U(1.W), staticInst.instr(19, 15)) 72 val src2 = Cat(0.U(1.W), staticInst.instr(24, 20)) 73 val dest = Cat(0.U(1.W), staticInst.instr(11, 7)) 74 75 //output bits 76 val decodedInsts = Wire(Vec(RenameWidth, new DecodedInst)) 77 val validToRename = Wire(Vec(RenameWidth, Bool())) 78 val readyToIBuf = Wire(Vec(DecodeWidth, Bool())) 79 val complexNum = Wire(UInt(3.W)) 80 81 //output of DecodeUnit 82 val decodedInsts_u = Wire(new DecodedInst) 83 val isVset_u = Wire(Bool()) 84 85 //pre decode 86 val simple = Module(new DecodeUnit) 87 simple.io.enq.ctrlFlow := staticInst 88 simple.io.enq.vtype := io.vtype 89 simple.io.csrCtrl := io.csrCtrl 90 decodedInsts_u := simple.io.deq.decodedInst 91 isVset_u := simple.io.deq.decodedInst.isVset 92 when(isVset_u) { 93 when(dest === 0.U && src1 === 0.U) { 94 decodedInsts_u.fuOpType := VSETOpType.keepVl(simple.io.deq.decodedInst.fuOpType) 95 }.elsewhen(src1 === 0.U) { 96 decodedInsts_u.fuOpType := VSETOpType.setVlmax(simple.io.deq.decodedInst.fuOpType) 97 } 98 when(io.vtype.illegal){ 99 decodedInsts_u.flushPipe := true.B 100 } 101 } 102 //Type of uop Div 103 val typeOfDiv = decodedInsts_u.uopDivType 104 105 //LMUL 106 val lmul = MuxLookup(simple.io.enq.vtype.vlmul, 1.U(4.W), Array( 107 "b001".U -> 2.U, 108 "b010".U -> 4.U, 109 "b011".U -> 8.U 110 )) 111 val numOfUopVslide = MuxLookup(simple.io.enq.vtype.vlmul, 1.U(log2Up(maxUopSize+1).W), Array( 112 "b001".U -> 3.U, 113 "b010".U -> 10.U, 114 "b011".U -> 36.U 115 )) 116 //number of uop 117 val numOfUop = MuxLookup(typeOfDiv, 1.U(log2Up(maxUopSize+1).W), Array( 118 UopDivType.VEC_0XV -> 2.U, 119 UopDivType.DIR -> Mux(dest =/= 0.U, 2.U, 120 Mux(src1 =/= 0.U, 1.U, 121 Mux(VSETOpType.isVsetvl(decodedInsts_u.fuOpType), 2.U, 1.U))), 122 UopDivType.VEC_VVV -> lmul, 123 UopDivType.VEC_EXT2 -> lmul, 124 UopDivType.VEC_EXT4 -> lmul, 125 UopDivType.VEC_EXT8 -> lmul, 126 UopDivType.VEC_VVM -> lmul, 127 UopDivType.VEC_VXM -> (lmul +& 1.U), 128 UopDivType.VEC_VXV -> (lmul +& 1.U), 129 UopDivType.VEC_VVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 130 UopDivType.VEC_WVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 131 UopDivType.VEC_VXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 132 UopDivType.VEC_WXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 133 UopDivType.VEC_WVV -> Cat(lmul, 0.U(1.W)), // lmul <= 4 134 UopDivType.VEC_WXV -> Cat(lmul, 1.U(1.W)), // lmul <= 4 135 UopDivType.VEC_SLIDE1UP -> (lmul +& 1.U), 136 UopDivType.VEC_FSLIDE1UP -> lmul, 137 UopDivType.VEC_SLIDE1DOWN -> Cat(lmul, 0.U(1.W)), 138 UopDivType.VEC_FSLIDE1DOWN -> (Cat(lmul, 0.U(1.W)) -1.U), 139 UopDivType.VEC_VRED -> lmul, 140 UopDivType.VEC_SLIDEUP -> (numOfUopVslide + 1.U), 141 UopDivType.VEC_ISLIDEUP -> numOfUopVslide, 142 UopDivType.VEC_SLIDEDOWN -> (numOfUopVslide + 1.U), 143 UopDivType.VEC_ISLIDEDOWN -> numOfUopVslide, 144 UopDivType.VEC_M0X -> (lmul +& 1.U), 145 UopDivType.VEC_MVV -> (Cat(lmul, 0.U(1.W)) -1.U), 146 UopDivType.VEC_M0X_VFIRST -> 2.U, 147 )) 148 149 //uop div up to maxUopSize 150 val csBundle = Wire(Vec(maxUopSize, new DecodedInst)) 151 csBundle.map { case dst => 152 dst := decodedInsts_u 153 dst.firstUop := false.B 154 dst.lastUop := false.B 155 } 156 157 csBundle(0).firstUop := true.B 158 csBundle(numOfUop - 1.U).lastUop := true.B 159 160 switch(typeOfDiv) { 161 is(UopDivType.DIR) { 162 when(isVset_u) { 163 when(dest =/= 0.U) { 164 csBundle(0).fuType := FuType.vsetiwi.U 165 csBundle(0).fuOpType := VSETOpType.switchDest(decodedInsts_u.fuOpType) 166 csBundle(0).flushPipe := false.B 167 csBundle(0).rfWen := true.B 168 csBundle(0).vecWen := false.B 169 csBundle(1).ldest := VECTOR_VCONFIG.U 170 }.elsewhen(src1 =/= 0.U) { 171 csBundle(0).ldest := VECTOR_VCONFIG.U 172 }.elsewhen(VSETOpType.isVsetvli(decodedInsts_u.fuOpType)) { 173 csBundle(0).fuType := FuType.vsetfwf.U 174 csBundle(0).srcType(0) := SrcType.vp 175 csBundle(0).lsrc(0) := VECTOR_VCONFIG.U 176 }.elsewhen(VSETOpType.isVsetvl(decodedInsts_u.fuOpType)) { 177 csBundle(0).srcType(0) := SrcType.reg 178 csBundle(0).srcType(1) := SrcType.imm 179 csBundle(0).lsrc(1) := 0.U 180 csBundle(0).ldest := FP_TMP_REG_MV.U 181 csBundle(0).fuType := FuType.i2f.U 182 csBundle(0).rfWen := false.B 183 csBundle(0).fpWen := true.B 184 csBundle(0).vecWen := false.B 185 csBundle(0).fpu.isAddSub := false.B 186 csBundle(0).fpu.typeTagIn := FPU.D 187 csBundle(0).fpu.typeTagOut := FPU.D 188 csBundle(0).fpu.fromInt := true.B 189 csBundle(0).fpu.wflags := false.B 190 csBundle(0).fpu.fpWen := true.B 191 csBundle(0).fpu.div := false.B 192 csBundle(0).fpu.sqrt := false.B 193 csBundle(0).fpu.fcvt := false.B 194 csBundle(0).flushPipe := false.B 195 csBundle(1).fuType := FuType.vsetfwf.U 196 csBundle(1).srcType(0) := SrcType.vp 197 csBundle(1).lsrc(0) := VECTOR_VCONFIG.U 198 csBundle(1).srcType(1) := SrcType.fp 199 csBundle(1).lsrc(1) := FP_TMP_REG_MV.U 200 csBundle(1).ldest := VECTOR_VCONFIG.U 201 } 202 } 203 } 204 is(UopDivType.VEC_VVV) { 205 for (i <- 0 until MAX_VLMUL) { 206 csBundle(i).lsrc(0) := src1 + i.U 207 csBundle(i).lsrc(1) := src2 + i.U 208 csBundle(i).lsrc(2) := dest + i.U 209 csBundle(i).ldest := dest + i.U 210 csBundle(i).uopIdx := i.U 211 } 212 } 213 is(UopDivType.VEC_EXT2) { 214 for (i <- 0 until MAX_VLMUL / 2) { 215 csBundle(2 * i).lsrc(1) := src2 + i.U 216 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 217 csBundle(2 * i).ldest := dest + (2 * i).U 218 csBundle(2 * i).uopIdx := (2 * i).U 219 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 220 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 221 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 222 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 223 } 224 } 225 is(UopDivType.VEC_EXT4) { 226 for (i <- 0 until MAX_VLMUL / 4) { 227 csBundle(4 * i).lsrc(1) := src2 + i.U 228 csBundle(4 * i).lsrc(2) := dest + (4 * i).U 229 csBundle(4 * i).ldest := dest + (4 * i).U 230 csBundle(4 * i).uopIdx := (4 * i).U 231 csBundle(4 * i + 1).lsrc(1) := src2 + i.U 232 csBundle(4 * i + 1).lsrc(2) := dest + (4 * i + 1).U 233 csBundle(4 * i + 1).ldest := dest + (4 * i + 1).U 234 csBundle(4 * i + 1).uopIdx := (4 * i + 1).U 235 csBundle(4 * i + 2).lsrc(1) := src2 + i.U 236 csBundle(4 * i + 2).lsrc(2) := dest + (4 * i + 2).U 237 csBundle(4 * i + 2).ldest := dest + (4 * i + 2).U 238 csBundle(4 * i + 2).uopIdx := (4 * i + 2).U 239 csBundle(4 * i + 3).lsrc(1) := src2 + i.U 240 csBundle(4 * i + 3).lsrc(2) := dest + (4 * i + 3).U 241 csBundle(4 * i + 3).ldest := dest + (4 * i + 3).U 242 csBundle(4 * i + 3).uopIdx := (4 * i + 3).U 243 } 244 } 245 is(UopDivType.VEC_EXT8) { 246 for (i <- 0 until MAX_VLMUL) { 247 csBundle(i).lsrc(1) := src2 248 csBundle(i).lsrc(2) := dest + i.U 249 csBundle(i).ldest := dest + i.U 250 csBundle(i).uopIdx := i.U 251 } 252 } 253 is(UopDivType.VEC_0XV) { 254 /* 255 FMV.D.X 256 */ 257 csBundle(0).srcType(0) := SrcType.reg 258 csBundle(0).srcType(1) := SrcType.imm 259 csBundle(0).lsrc(1) := 0.U 260 csBundle(0).ldest := FP_TMP_REG_MV.U 261 csBundle(0).fuType := FuType.i2f.U 262 csBundle(0).rfWen := false.B 263 csBundle(0).fpWen := true.B 264 csBundle(0).vecWen := false.B 265 csBundle(0).fpu.isAddSub := false.B 266 csBundle(0).fpu.typeTagIn := FPU.D 267 csBundle(0).fpu.typeTagOut := FPU.D 268 csBundle(0).fpu.fromInt := true.B 269 csBundle(0).fpu.wflags := false.B 270 csBundle(0).fpu.fpWen := true.B 271 csBundle(0).fpu.div := false.B 272 csBundle(0).fpu.sqrt := false.B 273 csBundle(0).fpu.fcvt := false.B 274 /* 275 vfmv.s.f 276 */ 277 csBundle(1).srcType(0) := SrcType.fp 278 csBundle(1).srcType(1) := SrcType.vp 279 csBundle(1).srcType(2) := SrcType.vp 280 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 281 csBundle(1).lsrc(1) := 0.U 282 csBundle(1).lsrc(2) := dest 283 csBundle(1).ldest := dest 284 csBundle(1).fuType := FuType.vppu.U 285 csBundle(1).fuOpType := VpermType.vfmv_s_f 286 csBundle(1).rfWen := false.B 287 csBundle(1).fpWen := false.B 288 csBundle(1).vecWen := true.B 289 } 290 is(UopDivType.VEC_VXV) { 291 /* 292 FMV.D.X 293 */ 294 csBundle(0).srcType(0) := SrcType.reg 295 csBundle(0).srcType(1) := SrcType.imm 296 csBundle(0).lsrc(1) := 0.U 297 csBundle(0).ldest := FP_TMP_REG_MV.U 298 csBundle(0).fuType := FuType.i2f.U 299 csBundle(0).rfWen := false.B 300 csBundle(0).fpWen := true.B 301 csBundle(0).vecWen := false.B 302 csBundle(0).fpu.isAddSub := false.B 303 csBundle(0).fpu.typeTagIn := FPU.D 304 csBundle(0).fpu.typeTagOut := FPU.D 305 csBundle(0).fpu.fromInt := true.B 306 csBundle(0).fpu.wflags := false.B 307 csBundle(0).fpu.fpWen := true.B 308 csBundle(0).fpu.div := false.B 309 csBundle(0).fpu.sqrt := false.B 310 csBundle(0).fpu.fcvt := false.B 311 /* 312 LMUL 313 */ 314 for (i <- 0 until MAX_VLMUL) { 315 csBundle(i + 1).srcType(0) := SrcType.fp 316 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 317 csBundle(i + 1).lsrc(1) := src2 + i.U 318 csBundle(i + 1).lsrc(2) := dest + i.U 319 csBundle(i + 1).ldest := dest + i.U 320 csBundle(i + 1).uopIdx := i.U 321 } 322 } 323 is(UopDivType.VEC_VVW) { 324 for (i <- 0 until MAX_VLMUL / 2) { 325 csBundle(2 * i).lsrc(0) := src1 + i.U 326 csBundle(2 * i).lsrc(1) := src2 + i.U 327 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 328 csBundle(2 * i).ldest := dest + (2 * i).U 329 csBundle(2 * i).uopIdx := (2 * i).U 330 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 331 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 332 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 333 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 334 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 335 } 336 } 337 is(UopDivType.VEC_WVW) { 338 for (i <- 0 until MAX_VLMUL / 2) { 339 csBundle(2 * i).lsrc(0) := src1 + i.U 340 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 341 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 342 csBundle(2 * i).ldest := dest + (2 * i).U 343 csBundle(2 * i).uopIdx := (2 * i).U 344 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 345 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 346 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 347 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 348 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 349 } 350 } 351 is(UopDivType.VEC_VXW) { 352 /* 353 FMV.D.X 354 */ 355 csBundle(0).srcType(0) := SrcType.reg 356 csBundle(0).srcType(1) := SrcType.imm 357 csBundle(0).lsrc(1) := 0.U 358 csBundle(0).ldest := FP_TMP_REG_MV.U 359 csBundle(0).fuType := FuType.i2f.U 360 csBundle(0).rfWen := false.B 361 csBundle(0).fpWen := true.B 362 csBundle(0).vecWen := false.B 363 csBundle(0).fpu.isAddSub := false.B 364 csBundle(0).fpu.typeTagIn := FPU.D 365 csBundle(0).fpu.typeTagOut := FPU.D 366 csBundle(0).fpu.fromInt := true.B 367 csBundle(0).fpu.wflags := false.B 368 csBundle(0).fpu.fpWen := true.B 369 csBundle(0).fpu.div := false.B 370 csBundle(0).fpu.sqrt := false.B 371 csBundle(0).fpu.fcvt := false.B 372 373 for (i <- 0 until MAX_VLMUL / 2) { 374 csBundle(2 * i + 1).srcType(0) := SrcType.fp 375 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 376 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 377 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 378 csBundle(2 * i + 1).ldest := dest + (2 * i).U 379 csBundle(2 * i + 1).uopIdx := (2 * i).U 380 csBundle(2 * i + 2).srcType(0) := SrcType.fp 381 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 382 csBundle(2 * i + 2).lsrc(1) := src2 + i.U 383 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 384 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 385 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 386 } 387 } 388 is(UopDivType.VEC_WXW) { 389 /* 390 FMV.D.X 391 */ 392 csBundle(0).srcType(0) := SrcType.reg 393 csBundle(0).srcType(1) := SrcType.imm 394 csBundle(0).lsrc(1) := 0.U 395 csBundle(0).ldest := FP_TMP_REG_MV.U 396 csBundle(0).fuType := FuType.i2f.U 397 csBundle(0).rfWen := false.B 398 csBundle(0).fpWen := true.B 399 csBundle(0).vecWen := false.B 400 csBundle(0).fpu.isAddSub := false.B 401 csBundle(0).fpu.typeTagIn := FPU.D 402 csBundle(0).fpu.typeTagOut := FPU.D 403 csBundle(0).fpu.fromInt := true.B 404 csBundle(0).fpu.wflags := false.B 405 csBundle(0).fpu.fpWen := true.B 406 csBundle(0).fpu.div := false.B 407 csBundle(0).fpu.sqrt := false.B 408 csBundle(0).fpu.fcvt := false.B 409 410 for (i <- 0 until MAX_VLMUL / 2) { 411 csBundle(2 * i + 1).srcType(0) := SrcType.fp 412 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 413 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 414 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 415 csBundle(2 * i + 1).ldest := dest + (2 * i).U 416 csBundle(2 * i + 1).uopIdx := (2 * i).U 417 csBundle(2 * i + 2).srcType(0) := SrcType.fp 418 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 419 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 420 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 421 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 422 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 423 } 424 } 425 is(UopDivType.VEC_WVV) { 426 for (i <- 0 until MAX_VLMUL / 2) { 427 428 csBundle(2 * i).lsrc(0) := src1 + i.U 429 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 430 csBundle(2 * i).lsrc(2) := dest + i.U 431 csBundle(2 * i).ldest := VECTOR_TMP_REG_LMUL.U 432 csBundle(2 * i).uopIdx := (2 * i).U 433 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 434 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 435 csBundle(2 * i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 436 csBundle(2 * i + 1).ldest := dest + i.U 437 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 438 } 439 } 440 is(UopDivType.VEC_WXV) { 441 /* 442 FMV.D.X 443 */ 444 csBundle(0).srcType(0) := SrcType.reg 445 csBundle(0).srcType(1) := SrcType.imm 446 csBundle(0).lsrc(1) := 0.U 447 csBundle(0).ldest := FP_TMP_REG_MV.U 448 csBundle(0).fuType := FuType.i2f.U 449 csBundle(0).rfWen := false.B 450 csBundle(0).fpWen := true.B 451 csBundle(0).vecWen := false.B 452 csBundle(0).fpu.isAddSub := false.B 453 csBundle(0).fpu.typeTagIn := FPU.D 454 csBundle(0).fpu.typeTagOut := FPU.D 455 csBundle(0).fpu.fromInt := true.B 456 csBundle(0).fpu.wflags := false.B 457 csBundle(0).fpu.fpWen := true.B 458 csBundle(0).fpu.div := false.B 459 csBundle(0).fpu.sqrt := false.B 460 csBundle(0).fpu.fcvt := false.B 461 462 for (i <- 0 until MAX_VLMUL / 2) { 463 csBundle(2 * i + 1).srcType(0) := SrcType.fp 464 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 465 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 466 csBundle(2 * i + 1).lsrc(2) := dest + i.U 467 csBundle(2 * i + 1).ldest := VECTOR_TMP_REG_LMUL.U 468 csBundle(2 * i + 1).uopIdx := (2 * i).U 469 csBundle(2 * i + 2).srcType(0) := SrcType.fp 470 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 471 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 472 csBundle(2 * i + 2).lsrc(2) := VECTOR_TMP_REG_LMUL.U 473 csBundle(2 * i + 2).ldest := dest + i.U 474 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 475 } 476 } 477 is(UopDivType.VEC_VVM) { 478 csBundle(0).lsrc(2) := dest 479 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 480 csBundle(0).uopIdx := 0.U 481 for(i <- 1 until MAX_VLMUL) { 482 csBundle(i).lsrc(0) := src1 + i.U 483 csBundle(i).lsrc(1) := src2 + i.U 484 csBundle(i).lsrc(2) := VECTOR_TMP_REG_LMUL.U 485 csBundle(i).ldest := VECTOR_TMP_REG_LMUL.U 486 csBundle(i).uopIdx := i.U 487 } 488 csBundle(numOfUop - 1.U).ldest := dest 489 } 490 is(UopDivType.VEC_VXM) { 491 /* 492 FMV.D.X 493 */ 494 csBundle(0).srcType(0) := SrcType.reg 495 csBundle(0).srcType(1) := SrcType.imm 496 csBundle(0).lsrc(1) := 0.U 497 csBundle(0).ldest := FP_TMP_REG_MV.U 498 csBundle(0).fuType := FuType.i2f.U 499 csBundle(0).rfWen := false.B 500 csBundle(0).fpWen := true.B 501 csBundle(0).vecWen := false.B 502 csBundle(0).fpu.isAddSub := false.B 503 csBundle(0).fpu.typeTagIn := FPU.D 504 csBundle(0).fpu.typeTagOut := FPU.D 505 csBundle(0).fpu.fromInt := true.B 506 csBundle(0).fpu.wflags := false.B 507 csBundle(0).fpu.fpWen := true.B 508 csBundle(0).fpu.div := false.B 509 csBundle(0).fpu.sqrt := false.B 510 csBundle(0).fpu.fcvt := false.B 511 //LMUL 512 csBundle(1).srcType(0) := SrcType.fp 513 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 514 csBundle(1).lsrc(2) := dest 515 csBundle(1).ldest := VECTOR_TMP_REG_LMUL.U 516 csBundle(1).uopIdx := 0.U 517 for (i <- 1 until MAX_VLMUL) { 518 csBundle(i + 1).srcType(0) := SrcType.fp 519 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 520 csBundle(i + 1).lsrc(1) := src2 + i.U 521 csBundle(i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 522 csBundle(i + 1).ldest := VECTOR_TMP_REG_LMUL.U 523 csBundle(i + 1).uopIdx := i.U 524 } 525 csBundle(numOfUop - 1.U).ldest := dest 526 } 527 is(UopDivType.VEC_SLIDE1UP) { 528 /* 529 FMV.D.X 530 */ 531 csBundle(0).srcType(0) := SrcType.reg 532 csBundle(0).srcType(1) := SrcType.imm 533 csBundle(0).lsrc(1) := 0.U 534 csBundle(0).ldest := FP_TMP_REG_MV.U 535 csBundle(0).fuType := FuType.i2f.U 536 csBundle(0).rfWen := false.B 537 csBundle(0).fpWen := true.B 538 csBundle(0).vecWen := false.B 539 csBundle(0).fpu.isAddSub := false.B 540 csBundle(0).fpu.typeTagIn := FPU.D 541 csBundle(0).fpu.typeTagOut := FPU.D 542 csBundle(0).fpu.fromInt := true.B 543 csBundle(0).fpu.wflags := false.B 544 csBundle(0).fpu.fpWen := true.B 545 csBundle(0).fpu.div := false.B 546 csBundle(0).fpu.sqrt := false.B 547 csBundle(0).fpu.fcvt := false.B 548 //LMUL 549 csBundle(1).srcType(0) := SrcType.fp 550 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 551 csBundle(1).lsrc(2) := dest 552 csBundle(1).ldest := dest 553 csBundle(1).uopIdx := 0.U 554 for (i <- 1 until MAX_VLMUL) { 555 csBundle(i + 1).srcType(0) := SrcType.vp 556 csBundle(i + 1).lsrc(0) := src2 + (i - 1).U 557 csBundle(i + 1).lsrc(1) := src2 + i.U 558 csBundle(i + 1).lsrc(2) := dest + i.U 559 csBundle(i + 1).ldest := dest + i.U 560 csBundle(i + 1).uopIdx := i.U 561 } 562 } 563 is(UopDivType.VEC_FSLIDE1UP) { 564 //LMUL 565 csBundle(0).srcType(0) := SrcType.fp 566 csBundle(0).lsrc(0) := src1 567 csBundle(0).lsrc(1) := src2 568 csBundle(0).lsrc(2) := dest 569 csBundle(0).ldest := dest 570 csBundle(0).uopIdx := 0.U 571 for (i <- 1 until MAX_VLMUL) { 572 csBundle(i).srcType(0) := SrcType.vp 573 csBundle(i).lsrc(0) := src2 + (i - 1).U 574 csBundle(i).lsrc(1) := src2 + i.U 575 csBundle(i).lsrc(2) := dest + i.U 576 csBundle(i).ldest := dest + i.U 577 csBundle(i).uopIdx := i.U 578 } 579 } 580 is(UopDivType.VEC_SLIDE1DOWN) { // lmul+lmul = 16 581 /* 582 FMV.D.X 583 */ 584 csBundle(0).srcType(0) := SrcType.reg 585 csBundle(0).srcType(1) := SrcType.imm 586 csBundle(0).lsrc(1) := 0.U 587 csBundle(0).ldest := FP_TMP_REG_MV.U 588 csBundle(0).fuType := FuType.i2f.U 589 csBundle(0).rfWen := false.B 590 csBundle(0).fpWen := true.B 591 csBundle(0).vecWen := false.B 592 csBundle(0).fpu.isAddSub := false.B 593 csBundle(0).fpu.typeTagIn := FPU.D 594 csBundle(0).fpu.typeTagOut := FPU.D 595 csBundle(0).fpu.fromInt := true.B 596 csBundle(0).fpu.wflags := false.B 597 csBundle(0).fpu.fpWen := true.B 598 csBundle(0).fpu.div := false.B 599 csBundle(0).fpu.sqrt := false.B 600 csBundle(0).fpu.fcvt := false.B 601 //LMUL 602 for (i <- 0 until MAX_VLMUL) { 603 csBundle(2 * i + 1).srcType(0) := SrcType.vp 604 csBundle(2 * i + 1).srcType(1) := SrcType.vp 605 csBundle(2 * i + 1).lsrc(0) := src2 + (i+1).U 606 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 607 csBundle(2 * i + 1).lsrc(2) := dest + i.U 608 csBundle(2 * i + 1).ldest := VECTOR_TMP_REG_LMUL.U 609 csBundle(2 * i + 1).uopIdx := (2 * i).U 610 if (2 * i + 2 < MAX_VLMUL * 2 ){ 611 csBundle(2 * i + 2).srcType(0) := SrcType.fp 612 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 613 // csBundle(2 * i + 2).lsrc(1) := src2 + i.U // DontCare 614 csBundle(2 * i + 2).lsrc(2) := VECTOR_TMP_REG_LMUL.U 615 csBundle(2 * i + 2).ldest := dest + i.U 616 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 617 } 618 } 619 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 620 csBundle(numOfUop - 1.U).lsrc(0) := FP_TMP_REG_MV.U 621 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 622 } 623 is(UopDivType.VEC_FSLIDE1DOWN) { 624 //LMUL 625 for (i <- 0 until MAX_VLMUL) { 626 csBundle(2 * i).srcType(0) := SrcType.vp 627 csBundle(2 * i).srcType(1) := SrcType.vp 628 csBundle(2 * i).lsrc(0) := src2 + (i+1).U 629 csBundle(2 * i).lsrc(1) := src2 + i.U 630 csBundle(2 * i).lsrc(2) := dest + i.U 631 csBundle(2 * i).ldest := VECTOR_TMP_REG_LMUL.U 632 csBundle(2 * i).uopIdx := (2 * i).U 633 csBundle(2 * i + 1).srcType(0) := SrcType.fp 634 csBundle(2 * i + 1).lsrc(0) := src1 635 csBundle(2 * i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 636 csBundle(2 * i + 1).ldest := dest + i.U 637 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 638 } 639 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 640 csBundle(numOfUop - 1.U).lsrc(0) := src1 641 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 642 } 643 is(UopDivType.VEC_VRED) { 644 when(simple.io.enq.vtype.vlmul === "b001".U){ 645 csBundle(0).srcType(2) := SrcType.DC 646 csBundle(0).lsrc(0) := src2 + 1.U 647 csBundle(0).lsrc(1) := src2 648 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 649 csBundle(0).uopIdx := 0.U 650 } 651 when(simple.io.enq.vtype.vlmul === "b010".U) { 652 csBundle(0).srcType(2) := SrcType.DC 653 csBundle(0).lsrc(0) := src2 + 1.U 654 csBundle(0).lsrc(1) := src2 655 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 656 csBundle(0).uopIdx := 0.U 657 658 csBundle(1).srcType(2) := SrcType.DC 659 csBundle(1).lsrc(0) := src2 + 3.U 660 csBundle(1).lsrc(1) := src2 + 2.U 661 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL+1).U 662 csBundle(1).uopIdx := 1.U 663 664 csBundle(2).srcType(2) := SrcType.DC 665 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL+1).U 666 csBundle(2).lsrc(1) := VECTOR_TMP_REG_LMUL.U 667 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL+2).U 668 csBundle(2).uopIdx := 2.U 669 } 670 when(simple.io.enq.vtype.vlmul === "b011".U) { 671 for(i <- 0 until MAX_VLMUL){ 672 if(i < MAX_VLMUL - MAX_VLMUL/2){ 673 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 674 csBundle(i).lsrc(1) := src2 + (i * 2).U 675 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 676 } else if (i < MAX_VLMUL - MAX_VLMUL/4) { 677 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL/2)*2 + 1).U 678 csBundle(i).lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL/2)*2).U 679 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 680 }else if (i < MAX_VLMUL - MAX_VLMUL/8) { 681 csBundle(6).lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 682 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 683 csBundle(6).ldest := (VECTOR_TMP_REG_LMUL + 6).U 684 } 685 csBundle(i).srcType(2) := SrcType.DC 686 csBundle(i).uopIdx := i.U 687 } 688 } 689 when (simple.io.enq.vtype.vlmul.orR()){ 690 csBundle(numOfUop - 1.U).srcType(2) := SrcType.vp 691 csBundle(numOfUop - 1.U).lsrc(0) := src1 692 csBundle(numOfUop - 1.U).lsrc(1) := VECTOR_TMP_REG_LMUL.U + numOfUop - 2.U 693 csBundle(numOfUop - 1.U).lsrc(2) := dest 694 csBundle(numOfUop - 1.U).ldest := dest 695 csBundle(numOfUop - 1.U).uopIdx := numOfUop - 1.U 696 } 697 } 698 699 is(UopDivType.VEC_SLIDEUP) { 700 // FMV.D.X 701 csBundle(0).srcType(0) := SrcType.reg 702 csBundle(0).srcType(1) := SrcType.imm 703 csBundle(0).lsrc(1) := 0.U 704 csBundle(0).ldest := FP_TMP_REG_MV.U 705 csBundle(0).fuType := FuType.i2f.U 706 csBundle(0).rfWen := false.B 707 csBundle(0).fpWen := true.B 708 csBundle(0).vecWen := false.B 709 csBundle(0).fpu.isAddSub := false.B 710 csBundle(0).fpu.typeTagIn := FPU.D 711 csBundle(0).fpu.typeTagOut := FPU.D 712 csBundle(0).fpu.fromInt := true.B 713 csBundle(0).fpu.wflags := false.B 714 csBundle(0).fpu.fpWen := true.B 715 csBundle(0).fpu.div := false.B 716 csBundle(0).fpu.sqrt := false.B 717 csBundle(0).fpu.fcvt := false.B 718 // LMUL 719 for(i <- 0 until MAX_VLMUL) 720 for(j <- 0 to i){ 721 val old_vd = if (j==0) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 722 val vd = if (j==i) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j).U 723 csBundle(i*(i+1)/2+j+1).srcType(0) := SrcType.fp 724 csBundle(i*(i+1)/2+j+1).lsrc(0) := FP_TMP_REG_MV.U 725 csBundle(i*(i+1)/2+j+1).lsrc(1) := src2 + j.U 726 csBundle(i*(i+1)/2+j+1).lsrc(2) := old_vd 727 csBundle(i*(i+1)/2+j+1).ldest := vd 728 csBundle(i*(i+1)/2+j+1).uopIdx := (i*(i+1)/2+j).U 729 } 730 } 731 732 is(UopDivType.VEC_ISLIDEUP) { 733 // LMUL 734 for(i <- 0 until MAX_VLMUL) 735 for(j <- 0 to i){ 736 val old_vd = if (j==0) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 737 val vd = if (j==i) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j).U 738 csBundle(i*(i+1)/2+j).lsrc(1) := src2 + j.U 739 csBundle(i*(i+1)/2+j).lsrc(2) := old_vd 740 csBundle(i*(i+1)/2+j).ldest := vd 741 csBundle(i*(i+1)/2+j).uopIdx := (i*(i+1)/2+j).U 742 } 743 } 744 745 is(UopDivType.VEC_SLIDEDOWN) { 746 // FMV.D.X 747 csBundle(0).srcType(0) := SrcType.reg 748 csBundle(0).srcType(1) := SrcType.imm 749 csBundle(0).lsrc(1) := 0.U 750 csBundle(0).ldest := FP_TMP_REG_MV.U 751 csBundle(0).fuType := FuType.i2f.U 752 csBundle(0).rfWen := false.B 753 csBundle(0).fpWen := true.B 754 csBundle(0).vecWen := false.B 755 csBundle(0).fpu.isAddSub := false.B 756 csBundle(0).fpu.typeTagIn := FPU.D 757 csBundle(0).fpu.typeTagOut := FPU.D 758 csBundle(0).fpu.fromInt := true.B 759 csBundle(0).fpu.wflags := false.B 760 csBundle(0).fpu.fpWen := true.B 761 csBundle(0).fpu.div := false.B 762 csBundle(0).fpu.sqrt := false.B 763 csBundle(0).fpu.fcvt := false.B 764 // LMUL 765 for(i <- 0 until MAX_VLMUL) 766 for(j <- (0 to i).reverse){ 767 when(i.U < lmul){ 768 val old_vd = if (j==0) {dest + lmul -1.U - i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 769 val vd = if (j==i) {dest + lmul - 1.U - i.U} else (VECTOR_TMP_REG_LMUL+j).U 770 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).srcType(0) := SrcType.fp 771 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).lsrc(0) := FP_TMP_REG_MV.U 772 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).lsrc(1) := src2 + lmul - 1.U - j.U 773 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).lsrc(2) := old_vd 774 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ldest := vd 775 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).uopIdx := numOfUop-(i*(i+1)/2+i-j+2).U 776 } 777 } 778 } 779 780 is(UopDivType.VEC_ISLIDEDOWN) { 781 // LMUL 782 for(i <- 0 until MAX_VLMUL) 783 for(j <- (0 to i).reverse){ 784 when(i.U < lmul){ 785 val old_vd = if (j==0) {dest + lmul -1.U - i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 786 val vd = if (j==i) {dest + lmul - 1.U - i.U} else (VECTOR_TMP_REG_LMUL+j).U 787 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).lsrc(1) := src2 + lmul - 1.U - j.U 788 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).lsrc(2) := old_vd 789 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ldest := vd 790 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).uopIdx := numOfUop-(i*(i+1)/2+i-j+1).U 791 } 792 } 793 } 794 795 is(UopDivType.VEC_M0X) { 796 // LMUL 797 for (i <- 0 until MAX_VLMUL) { 798 val srcType0 = if (i==0) SrcType.DC else SrcType.vp 799 val ldest = (VECTOR_TMP_REG_LMUL + i).U 800 csBundle(i).srcType(0) := srcType0 801 csBundle(i).srcType(1) := SrcType.vp 802 csBundle(i).rfWen := false.B 803 csBundle(i).vecWen := true.B 804 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 805 csBundle(i).lsrc(1) := src2 806 // csBundle(i).lsrc(2) := dest + i.U DontCare 807 csBundle(i).ldest := ldest 808 csBundle(i).uopIdx := i.U 809 } 810 csBundle(lmul-1.U).vecWen := false.B 811 csBundle(lmul-1.U).fpWen := true.B 812 csBundle(lmul-1.U).ldest := FP_TMP_REG_MV.U 813 // FMV_X_D 814 csBundle(lmul).srcType(0) := SrcType.fp 815 csBundle(lmul).srcType(1) := SrcType.imm 816 csBundle(lmul).lsrc(0) := FP_TMP_REG_MV.U 817 csBundle(lmul).lsrc(1) := 0.U 818 csBundle(lmul).ldest := dest 819 csBundle(lmul).fuType := FuType.fmisc.U 820 csBundle(lmul).rfWen := true.B 821 csBundle(lmul).fpWen := false.B 822 csBundle(lmul).vecWen := false.B 823 csBundle(lmul).fpu.isAddSub := false.B 824 csBundle(lmul).fpu.typeTagIn := FPU.D 825 csBundle(lmul).fpu.typeTagOut := FPU.D 826 csBundle(lmul).fpu.fromInt := false.B 827 csBundle(lmul).fpu.wflags := false.B 828 csBundle(lmul).fpu.fpWen := false.B 829 csBundle(lmul).fpu.div := false.B 830 csBundle(lmul).fpu.sqrt := false.B 831 csBundle(lmul).fpu.fcvt := false.B 832 } 833 834 is(UopDivType.VEC_MVV) { 835 // LMUL 836 for (i <- 0 until MAX_VLMUL) { 837 val srcType0 = if (i==0) SrcType.DC else SrcType.vp 838 csBundle(i*2+0).srcType(0) := srcType0 839 csBundle(i*2+0).srcType(1) := SrcType.vp 840 csBundle(i*2+0).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 841 csBundle(i*2+0).lsrc(1) := src2 842 csBundle(i*2+0).lsrc(2) := dest + i.U 843 csBundle(i*2+0).ldest := dest + i.U 844 csBundle(i*2+0).uopIdx := (i*2+0).U 845 846 csBundle(i*2+1).srcType(0) := srcType0 847 csBundle(i*2+1).srcType(1) := SrcType.vp 848 csBundle(i*2+1).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 849 csBundle(i*2+1).lsrc(1) := src2 850 // csBundle(i).lsrc(2) := dest + i.U DontCare 851 csBundle(i*2+1).ldest := (VECTOR_TMP_REG_LMUL + i).U 852 csBundle(i*2+1).uopIdx := (i*2+1).U 853 } 854 } 855 856 is(UopDivType.VEC_M0X_VFIRST) { 857 // LMUL 858 csBundle(0).rfWen := false.B 859 csBundle(0).fpWen := true.B 860 csBundle(0).ldest := FP_TMP_REG_MV.U 861 // FMV_X_D 862 csBundle(1).srcType(0) := SrcType.fp 863 csBundle(1).srcType(1) := SrcType.imm 864 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 865 csBundle(1).lsrc(1) := 0.U 866 csBundle(1).ldest := dest 867 csBundle(1).fuType := FuType.fmisc.U 868 csBundle(1).rfWen := true.B 869 csBundle(1).fpWen := false.B 870 csBundle(1).vecWen := false.B 871 csBundle(1).fpu.isAddSub := false.B 872 csBundle(1).fpu.typeTagIn := FPU.D 873 csBundle(1).fpu.typeTagOut := FPU.D 874 csBundle(1).fpu.fromInt := false.B 875 csBundle(1).fpu.wflags := false.B 876 csBundle(1).fpu.fpWen := false.B 877 csBundle(1).fpu.div := false.B 878 csBundle(1).fpu.sqrt := false.B 879 csBundle(1).fpu.fcvt := false.B 880 } 881 } 882 883 //uops dispatch 884 val normal :: ext :: Nil = Enum(2) 885 val stateReg = RegInit(normal) 886 val uopRes = RegInit(0.U) 887 888 //readyFromRename Counter 889 val readyCounter = PriorityMuxDefault(io.readyFromRename.map(x => !x).zip((0 to (RenameWidth - 1)).map(_.U)), RenameWidth.U) 890 891 switch(stateReg) { 892 is(normal) { 893 stateReg := Mux(io.validFromIBuf(0) && (numOfUop > readyCounter) && (readyCounter =/= 0.U), ext, normal) 894 } 895 is(ext) { 896 stateReg := Mux(io.validFromIBuf(0) && (uopRes > readyCounter), ext, normal) 897 } 898 } 899 900 val uopRes0 = Mux(stateReg === normal, numOfUop, uopRes) 901 val uopResJudge = Mux(stateReg === normal, 902 io.validFromIBuf(0) && (readyCounter =/= 0.U) && (uopRes0 > readyCounter), 903 io.validFromIBuf(0) && (uopRes0 > readyCounter)) 904 uopRes := Mux(uopResJudge, uopRes0 - readyCounter, 0.U) 905 906 for(i <- 0 until RenameWidth) { 907 decodedInsts(i) := MuxCase(csBundle(i), Seq( 908 (stateReg === normal) -> csBundle(i), 909 (stateReg === ext) -> Mux((i.U + numOfUop -uopRes) < maxUopSize.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxUopSize - 1)) 910 )) 911 } 912 913 914 val validSimple = Wire(Vec(DecodeWidth - 1, Bool())) 915 validSimple.zip(io.validFromIBuf.drop(1).zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 916 val notInf = Wire(Vec(DecodeWidth - 1, Bool())) 917 notInf.zip(io.validFromIBuf.drop(1).zip(validSimple)).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 918 val notInfVec = Wire(Vec(DecodeWidth, Bool())) 919 notInfVec.drop(1).zip(0 until DecodeWidth - 1).map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 920 notInfVec(0) := true.B 921 922 complexNum := Mux(io.validFromIBuf(0) && readyCounter.orR , 923 Mux(uopRes0 > readyCounter, readyCounter, uopRes0), 924 1.U) 925 validToRename.zipWithIndex.foreach{ 926 case(dst, i) => 927 dst := MuxCase(false.B, Seq( 928 (io.validFromIBuf(0) && uopRes0 > readyCounter ) -> Mux(readyCounter > i.U, true.B, false.B), 929 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)), 930 )) 931 } 932 933 readyToIBuf.zipWithIndex.foreach { 934 case (dst, i) => 935 dst := MuxCase(true.B, Seq( 936 (io.validFromIBuf(0) && uopRes0 > readyCounter) -> false.B, 937 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> (if (i==0) true.B else Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B)), 938 )) 939 } 940 941 io.deq.decodedInsts := decodedInsts 942 io.deq.isVset := isVset_u 943 io.deq.complexNum := complexNum 944 io.deq.validToRename := validToRename 945 io.deq.readyToIBuf := readyToIBuf 946 947} 948 949