1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util.BitPat.bitPatToUInt 6import chisel3.util._ 7import utils.BundleUtils.makeValid 8import utils.OptionWrapper 9import xiangshan._ 10import xiangshan.backend.datapath.DataConfig._ 11import xiangshan.backend.datapath.DataSource 12import xiangshan.backend.datapath.WbConfig.PregWB 13import xiangshan.backend.decode.{ImmUnion, XDecode} 14import xiangshan.backend.exu.ExeUnitParams 15import xiangshan.backend.fu.FuType 16import xiangshan.backend.fu.fpu.Bundles.Frm 17import xiangshan.backend.fu.vector.Bundles._ 18import xiangshan.backend.issue.{IssueBlockParams, IssueQueueJumpBundle, SchedulerType, StatusArrayDeqRespBundle} 19import xiangshan.backend.regfile.{RfReadPortWithConfig, RfWritePortWithConfig} 20import xiangshan.backend.rob.RobPtr 21import xiangshan.frontend._ 22import xiangshan.mem.{LqPtr, SqPtr} 23 24object Bundles { 25 26 // frontend -> backend 27 class StaticInst(implicit p: Parameters) extends XSBundle { 28 val instr = UInt(32.W) 29 val pc = UInt(VAddrBits.W) 30 val foldpc = UInt(MemPredPCWidth.W) 31 val exceptionVec = ExceptionVec() 32 val trigger = new TriggerCf 33 val preDecodeInfo = new PreDecodeInfo 34 val pred_taken = Bool() 35 val crossPageIPFFix = Bool() 36 val ftqPtr = new FtqPtr 37 val ftqOffset = UInt(log2Up(PredictWidth).W) 38 39 def connectCtrlFlow(source: CtrlFlow): Unit = { 40 this.instr := source.instr 41 this.pc := source.pc 42 this.foldpc := source.foldpc 43 this.exceptionVec := source.exceptionVec 44 this.trigger := source.trigger 45 this.preDecodeInfo := source.pd 46 this.pred_taken := source.pred_taken 47 this.crossPageIPFFix := source.crossPageIPFFix 48 this.ftqPtr := source.ftqPtr 49 this.ftqOffset := source.ftqOffset 50 } 51 } 52 53 // StaticInst --[Decode]--> DecodedInst 54 class DecodedInst(implicit p: Parameters) extends XSBundle { 55 def numSrc = backendParams.numSrc 56 // passed from StaticInst 57 val instr = UInt(32.W) 58 val pc = UInt(VAddrBits.W) 59 val foldpc = UInt(MemPredPCWidth.W) 60 val exceptionVec = ExceptionVec() 61 val trigger = new TriggerCf 62 val preDecodeInfo = new PreDecodeInfo 63 val pred_taken = Bool() 64 val crossPageIPFFix = Bool() 65 val ftqPtr = new FtqPtr 66 val ftqOffset = UInt(log2Up(PredictWidth).W) 67 // decoded 68 val srcType = Vec(numSrc, SrcType()) 69 val lsrc = Vec(numSrc, UInt(6.W)) 70 val ldest = UInt(6.W) 71 val fuType = FuType() 72 val fuOpType = FuOpType() 73 val rfWen = Bool() 74 val fpWen = Bool() 75 val vecWen = Bool() 76 val isXSTrap = Bool() 77 val waitForward = Bool() // no speculate execution 78 val blockBackward = Bool() 79 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 80 val selImm = SelImm() 81 val imm = UInt(ImmUnion.maxLen.W) 82 val fpu = new FPUCtrlSignals 83 val vpu = new VPUCtrlSignals 84 val isMove = Bool() 85 val uopIdx = UInt(5.W) 86 val uopSplitType = UopSplitType() 87 val isVset = Bool() 88 val firstUop = Bool() 89 val lastUop = Bool() 90 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 91 val commitType = CommitType() // Todo: remove it 92 93 private def allSignals = srcType.take(3) ++ Seq(fuType, fuOpType, rfWen, fpWen, vecWen, 94 isXSTrap, waitForward, blockBackward, flushPipe, uopSplitType, selImm) 95 96 def decode(inst: UInt, table: Iterable[(BitPat, List[BitPat])]): DecodedInst = { 97 val decoder: Seq[UInt] = ListLookup( 98 inst, XDecode.decodeDefault.map(bitPatToUInt), 99 table.map{ case (pat, pats) => (pat, pats.map(bitPatToUInt)) }.toArray 100 ) 101 allSignals zip decoder foreach { case (s, d) => s := d } 102 this 103 } 104 105 def isSoftPrefetch: Bool = { 106 fuType === FuType.alu.U && fuOpType === ALUOpType.or && selImm === SelImm.IMM_I && ldest === 0.U 107 } 108 109 def connectStaticInst(source: StaticInst): Unit = { 110 for ((name, data) <- this.elements) { 111 if (source.elements.contains(name)) { 112 data := source.elements(name) 113 } 114 } 115 } 116 } 117 118 // DecodedInst --[Rename]--> DynInst 119 class DynInst(implicit p: Parameters) extends XSBundle { 120 def numSrc = backendParams.numSrc 121 // passed from StaticInst 122 val instr = UInt(32.W) 123 val pc = UInt(VAddrBits.W) 124 val foldpc = UInt(MemPredPCWidth.W) 125 val exceptionVec = ExceptionVec() 126 val trigger = new TriggerCf 127 val preDecodeInfo = new PreDecodeInfo 128 val pred_taken = Bool() 129 val crossPageIPFFix = Bool() 130 val ftqPtr = new FtqPtr 131 val ftqOffset = UInt(log2Up(PredictWidth).W) 132 // passed from DecodedInst 133 val srcType = Vec(numSrc, SrcType()) 134 val lsrc = Vec(numSrc, UInt(6.W)) 135 val ldest = UInt(6.W) 136 val fuType = FuType() 137 val fuOpType = FuOpType() 138 val rfWen = Bool() 139 val fpWen = Bool() 140 val vecWen = Bool() 141 val isXSTrap = Bool() 142 val waitForward = Bool() // no speculate execution 143 val blockBackward = Bool() 144 val flushPipe = Bool() // This inst will flush all the pipe when commit, like exception but can commit 145 val selImm = SelImm() 146 val imm = UInt(XLEN.W) // Todo: check if it need minimized 147 val fpu = new FPUCtrlSignals 148 val vpu = new VPUCtrlSignals 149 val isMove = Bool() 150 val uopIdx = UInt(5.W) 151 val isVset = Bool() 152 val firstUop = Bool() 153 val lastUop = Bool() 154 val numUops = UInt(log2Up(MaxUopSize).W) // rob need this 155 val commitType = CommitType() 156 // rename 157 val srcState = Vec(numSrc, SrcState()) 158 val psrc = Vec(numSrc, UInt(PhyRegIdxWidth.W)) 159 val pdest = UInt(PhyRegIdxWidth.W) 160 val oldPdest = UInt(PhyRegIdxWidth.W) 161 val robIdx = new RobPtr 162 163 val eliminatedMove = Bool() 164 val debugInfo = new PerfDebugInfo 165 val storeSetHit = Bool() // inst has been allocated an store set 166 val waitForRobIdx = new RobPtr // store set predicted previous store robIdx 167 // Load wait is needed 168 // load inst will not be executed until former store (predicted by mdp) addr calcuated 169 val loadWaitBit = Bool() 170 // If (loadWaitBit && loadWaitStrict), strict load wait is needed 171 // load inst will not be executed until ALL former store addr calcuated 172 val loadWaitStrict = Bool() 173 val ssid = UInt(SSIDWidth.W) 174 // Todo 175 val lqIdx = new LqPtr 176 val sqIdx = new SqPtr 177 // debug module 178 val singleStep = Bool() 179 // schedule 180 val replayInst = Bool() 181 182 def isLUI: Bool = this.fuType === FuType.alu.U && this.selImm === SelImm.IMM_U 183 def isWFI: Bool = this.fuType === FuType.csr.U && fuOpType === CSROpType.wfi 184 185 def isSvinvalBegin(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && !flush 186 def isSvinval(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.sfence && !flush 187 def isSvinvalEnd(flush: Bool) = FuType.isFence(fuType) && fuOpType === FenceOpType.nofence && flush 188 189 def srcIsReady: Vec[Bool] = { 190 VecInit(this.srcType.zip(this.srcState).map { 191 case (t, s) => SrcType.isNotReg(t) || SrcState.isReady(s) 192 }) 193 } 194 195 def clearExceptions( 196 exceptionBits: Seq[Int] = Seq(), 197 flushPipe : Boolean = false, 198 replayInst : Boolean = false 199 ): DynInst = { 200 this.exceptionVec.zipWithIndex.filterNot(x => exceptionBits.contains(x._2)).foreach(_._1 := false.B) 201 if (!flushPipe) { this.flushPipe := false.B } 202 if (!replayInst) { this.replayInst := false.B } 203 this 204 } 205 206 def needWriteRf: Bool = (rfWen && ldest =/= 0.U) || fpWen || vecWen 207 } 208 209 trait BundleSource { 210 var wakeupSource = "undefined" 211 var idx = 0 212 } 213 214 /** 215 * 216 * @param pregIdxWidth index width of preg 217 * @param exuIndices exu indices of wakeup bundle 218 */ 219 sealed abstract class IssueQueueWakeUpBaseBundle(pregIdxWidth: Int, val exuIndices: Seq[Int]) extends Bundle { 220 val rfWen = Bool() 221 val fpWen = Bool() 222 val vecWen = Bool() 223 val pdest = UInt(pregIdxWidth.W) 224 225 /** 226 * @param successor Seq[(psrc, srcType)] 227 * @return Seq[if wakeup psrc] 228 */ 229 def wakeUp(successor: Seq[(UInt, UInt)], valid: Bool): Seq[Bool] = { 230 successor.map { case (thatPsrc, srcType) => 231 val pdestMatch = pdest === thatPsrc 232 pdestMatch && ( 233 SrcType.isFp(srcType) && this.fpWen || 234 SrcType.isXp(srcType) && this.rfWen || 235 SrcType.isVp(srcType) && this.vecWen 236 ) && valid 237 } 238 } 239 240 def hasOnlyOneSource: Boolean = exuIndices.size == 1 241 242 def hasMultiSources: Boolean = exuIndices.size > 1 243 244 def isWBWakeUp = this.isInstanceOf[IssueQueueWBWakeUpBundle] 245 246 def isIQWakeUp = this.isInstanceOf[IssueQueueIQWakeUpBundle] 247 248 def exuIdx: Int = { 249 require(hasOnlyOneSource) 250 this.exuIndices.head 251 } 252 } 253 254 class IssueQueueWBWakeUpBundle(exuIndices: Seq[Int], backendParams: BackendParams) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, exuIndices) { 255 256 } 257 258 class IssueQueueIQWakeUpBundle(exuIdx: Int, backendParams: BackendParams) extends IssueQueueWakeUpBaseBundle(backendParams.pregIdxWidth, Seq(exuIdx)) { 259 def fromExuInput(exuInput: ExuInput, l2ExuVecs: Vec[Vec[Bool]]): Unit = { 260 this.rfWen := exuInput.rfWen.getOrElse(false.B) 261 this.fpWen := exuInput.fpWen.getOrElse(false.B) 262 this.vecWen := exuInput.vecWen.getOrElse(false.B) 263 this.pdest := exuInput.pdest 264 } 265 266 def fromExuInput(exuInput: ExuInput): Unit = { 267 this.rfWen := exuInput.rfWen.getOrElse(false.B) 268 this.fpWen := exuInput.fpWen.getOrElse(false.B) 269 this.vecWen := exuInput.vecWen.getOrElse(false.B) 270 this.pdest := exuInput.pdest 271 } 272 } 273 274 class VPUCtrlSignals(implicit p: Parameters) extends XSBundle { 275 // vtype 276 val vill = Bool() 277 val vma = Bool() // 1: agnostic, 0: undisturbed 278 val vta = Bool() // 1: agnostic, 0: undisturbed 279 val vsew = VSew() 280 val vlmul = VLmul() // 1/8~8 --> -3~3 281 282 val vm = Bool() // 0: need v0.t 283 val vstart = Vl() 284 285 // float rounding mode 286 val frm = Frm() 287 // vector fix int rounding mode 288 val vxrm = Vxrm() 289 // vector uop index, exclude other non-vector uop 290 val vuopIdx = UopIdx() 291 // maybe used if data dependancy 292 val vmask = UInt(MaskSrcData().dataWidth.W) 293 val vl = Vl() 294 295 // vector load/store 296 val nf = Nf() 297 298 val needScalaSrc = Bool() 299 val permImmTruncate = Bool() // opivi 300 301 val isReverse = Bool() // vrsub, vrdiv 302 val isExt = Bool() 303 val isNarrow = Bool() 304 val isDstMask = Bool() // vvm, vvvm, mmm 305 val isMove = Bool() // vmv.s.x, vmv.v.v, vmv.v.x, vmv.v.i 306 307 def vtype: VType = { 308 val res = Wire(VType()) 309 res.illegal := this.vill 310 res.vma := this.vma 311 res.vta := this.vta 312 res.vsew := this.vsew 313 res.vlmul := this.vlmul 314 res 315 } 316 317 def vconfig: VConfig = { 318 val res = Wire(VConfig()) 319 res.vtype := this.vtype 320 res.vl := this.vl 321 res 322 } 323 } 324 325 // DynInst --[IssueQueue]--> DataPath 326 class IssueQueueIssueBundle( 327 iqParams: IssueBlockParams, 328 val exuParams: ExeUnitParams, 329 )(implicit 330 p: Parameters 331 ) extends Bundle { 332 private val rfReadDataCfgSet: Seq[Set[DataConfig]] = exuParams.getRfReadDataCfgSet 333 334 val rf: MixedVec[MixedVec[RfReadPortWithConfig]] = Flipped(MixedVec( 335 rfReadDataCfgSet.map((set: Set[DataConfig]) => 336 MixedVec(set.map((x: DataConfig) => new RfReadPortWithConfig(x, exuParams.rdPregIdxWidth)).toSeq) 337 ) 338 )) 339 340 val srcType = Vec(exuParams.numRegSrc, SrcType()) // used to select imm or reg data 341 val immType = SelImm() // used to select imm extractor 342 val common = new ExuInput(exuParams) 343 val jmp = if (exuParams.needPc) Some(Flipped(new IssueQueueJumpBundle)) else None 344 val addrOH = UInt(iqParams.numEntries.W) 345 346 def exuIdx = exuParams.exuIdx 347 def getSource: SchedulerType = exuParams.getWBSource 348 def getIntWbBusyBundle = common.rfWen.toSeq 349 def getVfWbBusyBundle = common.getVfWen.toSeq 350 def getIntRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readInt) 351 def getVfRfReadBundle: Seq[RfReadPortWithConfig] = rf.flatten.filter(_.readVf) 352 353 def getIntRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 354 getIntRfReadBundle.zip(srcType).map { 355 case (rfRd: RfReadPortWithConfig, t: UInt) => 356 makeValid(issueValid && SrcType.isXp(t), rfRd) 357 } 358 } 359 360 def getVfRfReadValidBundle(issueValid: Bool): Seq[ValidIO[RfReadPortWithConfig]] = { 361 getVfRfReadBundle.zip(srcType).map { 362 case (rfRd: RfReadPortWithConfig, t: UInt) => 363 makeValid(issueValid && SrcType.isVfp(t), rfRd) 364 } 365 } 366 367 def getIntRfWriteValidBundle(issueValid: Bool) = { 368 369 } 370 } 371 372 class OGRespBundle(implicit p:Parameters, params: IssueBlockParams) extends XSBundle { 373 val issueQueueParams = this.params 374 val og0resp = Valid(new StatusArrayDeqRespBundle) 375 val og1resp = Valid(new StatusArrayDeqRespBundle) 376 } 377 378 class fuBusyRespBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { 379 val respType = RSFeedbackType() // update credit if needs replay 380 val rfWen = Bool() // TODO: use params to identify IntWB/VfWB 381 val fuType = FuType() 382 } 383 384 class WbFuBusyTableWriteBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 385 private val intCertainLat = params.intLatencyCertain 386 private val vfCertainLat = params.vfLatencyCertain 387 private val intLat = params.intLatencyValMax 388 private val vfLat = params.vfLatencyValMax 389 390 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 391 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 392 val intDeqRespSet = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 393 val vfDeqRespSet = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 394 } 395 396 class WbFuBusyTableReadBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 397 private val intCertainLat = params.intLatencyCertain 398 private val vfCertainLat = params.vfLatencyCertain 399 private val intLat = params.intLatencyValMax 400 private val vfLat = params.vfLatencyValMax 401 402 val intWbBusyTable = OptionWrapper(intCertainLat, UInt((intLat + 1).W)) 403 val vfWbBusyTable = OptionWrapper(vfCertainLat, UInt((vfLat + 1).W)) 404 } 405 406 class WbConflictBundle(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 407 private val intCertainLat = params.intLatencyCertain 408 private val vfCertainLat = params.vfLatencyCertain 409 410 val intConflict = OptionWrapper(intCertainLat, Bool()) 411 val vfConflict = OptionWrapper(vfCertainLat, Bool()) 412 } 413 414 // DataPath --[ExuInput]--> Exu 415 class ExuInput(val params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 416 val fuType = FuType() 417 val fuOpType = FuOpType() 418 val src = Vec(params.numRegSrc, UInt(params.dataBitsMax.W)) 419 val imm = UInt(XLEN.W) 420 val robIdx = new RobPtr 421 val iqIdx = UInt(log2Up(MemIQSizeMax).W)// Only used by store yet 422 val isFirstIssue = Bool() // Only used by store yet 423 val pdest = UInt(params.wbPregIdxWidth.W) 424 val rfWen = if (params.writeIntRf) Some(Bool()) else None 425 val fpWen = if (params.writeFpRf) Some(Bool()) else None 426 val vecWen = if (params.writeVecRf) Some(Bool()) else None 427 val fpu = if (params.needFPUCtrl) Some(new FPUCtrlSignals) else None 428 val vpu = if (params.needVPUCtrl) Some(new VPUCtrlSignals) else None 429 val flushPipe = if (params.flushPipe) Some(Bool()) else None 430 val pc = if (params.needPc) Some(UInt(VAddrData().dataWidth.W)) else None 431 val jalrTarget = if (params.hasJmpFu) Some(UInt(VAddrData().dataWidth.W)) else None 432 val preDecode = if (params.hasPredecode) Some(new PreDecodeInfo) else None 433 val ftqIdx = if (params.needPc || params.replayInst) 434 Some(new FtqPtr) else None 435 val ftqOffset = if (params.needPc || params.replayInst) 436 Some(UInt(log2Up(PredictWidth).W)) else None 437 val predictInfo = if (params.hasPredecode) Some(new Bundle { 438 val target = UInt(VAddrData().dataWidth.W) 439 val taken = Bool() 440 }) else None 441 val sqIdx = if (params.hasMemAddrFu || params.hasStdFu) Some(new SqPtr) else None 442 val lqIdx = if (params.hasMemAddrFu) Some(new LqPtr) else None 443 val dataSources = Vec(params.numRegSrc, DataSource()) 444 val l1ExuVec = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, ExuVec())) 445 val srcTimer = OptionWrapper(params.isIQWakeUpSink, Vec(params.numRegSrc, UInt(3.W))) 446 447 def exuIdx = this.params.exuIdx 448 449 def needCancel(og0CancelVec: Vec[Bool], og1CancelVec: Vec[Bool]) : Bool = { 450 if (params.isIQWakeUpSink) { 451 require( 452 og0CancelVec.size == l1ExuVec.get.head.size, 453 s"cancelVecSize: {og0: ${og0CancelVec.size}, og1: ${og1CancelVec.size}}" 454 ) 455 val l1Cancel: Bool = l1ExuVec.get.zip(srcTimer.get).map { 456 case(exuOH: Vec[Bool], srcTimer: UInt) => 457 (exuOH.asUInt & og0CancelVec.asUInt).orR && srcTimer === 1.U 458 }.reduce(_ | _) 459 l1Cancel 460 } else { 461 false.B 462 } 463 } 464 465 def getVfWen = { 466 if (params.writeFpRf) this.fpWen 467 else if(params.writeVecRf) this.vecWen 468 else None 469 } 470 471 def fromIssueBundle(source: IssueQueueIssueBundle): Unit = { 472 // src is assigned to rfReadData 473 this.fuType := source.common.fuType 474 this.fuOpType := source.common.fuOpType 475 this.imm := source.common.imm 476 this.robIdx := source.common.robIdx 477 this.pdest := source.common.pdest 478 this.isFirstIssue := source.common.isFirstIssue // Only used by mem debug log 479 this.iqIdx := source.common.iqIdx // Only used by mem feedback 480 this.dataSources := source.common.dataSources 481 this.rfWen .foreach(_ := source.common.rfWen.get) 482 this.fpWen .foreach(_ := source.common.fpWen.get) 483 this.vecWen .foreach(_ := source.common.vecWen.get) 484 this.fpu .foreach(_ := source.common.fpu.get) 485 this.vpu .foreach(_ := source.common.vpu.get) 486 this.flushPipe .foreach(_ := source.common.flushPipe.get) 487 this.pc .foreach(_ := source.jmp.get.pc) 488 this.jalrTarget .foreach(_ := source.jmp.get.target) 489 this.preDecode .foreach(_ := source.common.preDecode.get) 490 this.ftqIdx .foreach(_ := source.common.ftqIdx.get) 491 this.ftqOffset .foreach(_ := source.common.ftqOffset.get) 492 this.predictInfo .foreach(_ := source.common.predictInfo.get) 493 this.lqIdx .foreach(_ := source.common.lqIdx.get) 494 this.sqIdx .foreach(_ := source.common.sqIdx.get) 495 this.l1ExuVec .foreach(_ := source.common.l1ExuVec.get) 496 this.srcTimer .foreach(_ := source.common.srcTimer.get) 497 } 498 } 499 500 // ExuInput --[FuncUnit]--> ExuOutput 501 class ExuOutput( 502 val params: ExeUnitParams, 503 )(implicit 504 val p: Parameters 505 ) extends Bundle with BundleSource with HasXSParameter { 506 val data = UInt(params.dataBitsMax.W) 507 val pdest = UInt(params.wbPregIdxWidth.W) 508 val robIdx = new RobPtr 509 val intWen = if (params.writeIntRf) Some(Bool()) else None 510 val fpWen = if (params.writeFpRf) Some(Bool()) else None 511 val vecWen = if (params.writeVecRf) Some(Bool()) else None 512 val redirect = if (params.hasRedirect) Some(ValidIO(new Redirect)) else None 513 val fflags = if (params.writeFflags) Some(UInt(5.W)) else None 514 val vxsat = if (params.writeVxsat) Some(Bool()) else None 515 val exceptionVec = if (params.exceptionOut.nonEmpty) Some(ExceptionVec()) else None 516 val flushPipe = if (params.flushPipe) Some(Bool()) else None 517 val replay = if (params.replayInst) Some(Bool()) else None 518 val lqIdx = if (params.hasLoadFu) Some(new LqPtr()) else None 519 val sqIdx = if (params.hasStoreAddrFu || params.hasStdFu) 520 Some(new SqPtr()) else None 521 val ftqIdx = if (params.needPc || params.replayInst) 522 Some(new FtqPtr) else None 523 val ftqOffset = if (params.needPc || params.replayInst) 524 Some(UInt(log2Up(PredictWidth).W)) else None 525 // uop info 526 val predecodeInfo = if(params.hasPredecode) Some(new PreDecodeInfo) else None 527 val debug = new DebugBundle 528 val debugInfo = new PerfDebugInfo 529 } 530 531 // ExuOutput + DynInst --> WriteBackBundle 532 class WriteBackBundle(val params: PregWB, backendParams: BackendParams)(implicit p: Parameters) extends Bundle with BundleSource { 533 val rfWen = Bool() 534 val fpWen = Bool() 535 val vecWen = Bool() 536 val pdest = UInt(params.pregIdxWidth(backendParams).W) 537 val data = UInt(params.dataWidth.W) 538 val robIdx = new RobPtr()(p) 539 val flushPipe = Bool() 540 val replayInst = Bool() 541 val redirect = ValidIO(new Redirect) 542 val fflags = UInt(5.W) 543 val vxsat = Bool() 544 val exceptionVec = ExceptionVec() 545 val debug = new DebugBundle 546 val debugInfo = new PerfDebugInfo 547 548 this.wakeupSource = s"WB(${params.toString})" 549 550 def fromExuOutput(source: ExuOutput) = { 551 this.rfWen := source.intWen.getOrElse(false.B) 552 this.fpWen := source.fpWen.getOrElse(false.B) 553 this.vecWen := source.vecWen.getOrElse(false.B) 554 this.pdest := source.pdest 555 this.data := source.data 556 this.robIdx := source.robIdx 557 this.flushPipe := source.flushPipe.getOrElse(false.B) 558 this.replayInst := source.replay.getOrElse(false.B) 559 this.redirect := source.redirect.getOrElse(0.U.asTypeOf(this.redirect)) 560 this.fflags := source.fflags.getOrElse(0.U.asTypeOf(this.fflags)) 561 this.vxsat := source.vxsat.getOrElse(0.U.asTypeOf(this.vxsat)) 562 this.exceptionVec := source.exceptionVec.getOrElse(0.U.asTypeOf(this.exceptionVec)) 563 this.debug := source.debug 564 this.debugInfo := source.debugInfo 565 } 566 567 def asIntRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 568 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(IntData()).addrWidth))) 569 rfWrite.wen := this.rfWen && fire 570 rfWrite.addr := this.pdest 571 rfWrite.data := this.data 572 rfWrite.intWen := this.rfWen 573 rfWrite.fpWen := false.B 574 rfWrite.vecWen := false.B 575 rfWrite 576 } 577 578 def asVfRfWriteBundle(fire: Bool): RfWritePortWithConfig = { 579 val rfWrite = Wire(Output(new RfWritePortWithConfig(this.params.dataCfg, backendParams.getPregParams(VecData()).addrWidth))) 580 rfWrite.wen := (this.fpWen || this.vecWen) && fire 581 rfWrite.addr := this.pdest 582 rfWrite.data := this.data 583 rfWrite.intWen := false.B 584 rfWrite.fpWen := this.fpWen 585 rfWrite.vecWen := this.vecWen 586 rfWrite 587 } 588 } 589 590 // ExuOutput --> ExuBypassBundle --[DataPath]-->ExuInput 591 // / 592 // [IssueQueue]--> ExuInput -- 593 class ExuBypassBundle( 594 val params: ExeUnitParams, 595 )(implicit 596 val p: Parameters 597 ) extends Bundle { 598 val data = UInt(params.dataBitsMax.W) 599 val pdest = UInt(params.wbPregIdxWidth.W) 600 } 601 602 class ExceptionInfo extends Bundle { 603 val pc = UInt(VAddrData().dataWidth.W) 604 val instr = UInt(32.W) 605 val commitType = CommitType() 606 val exceptionVec = ExceptionVec() 607 val singleStep = Bool() 608 val crossPageIPFFix = Bool() 609 val isInterrupt = Bool() 610 } 611 612 object UopIdx { 613 def apply()(implicit p: Parameters): UInt = UInt(log2Up(p(XSCoreParamsKey).MaxUopSize + 1).W) 614 } 615 616 object FuLatency { 617 def apply(): UInt = UInt(width.W) 618 619 def width = 4 // 0~15 // Todo: assosiate it with FuConfig 620 } 621 622 object ExuVec { 623 def apply(exuNum: Int): Vec[Bool] = Vec(exuNum, Bool()) 624 625 def apply()(implicit p: Parameters): Vec[Bool] = Vec(width, Bool()) 626 627 def width(implicit p: Parameters): Int = p(XSCoreParamsKey).backendParams.numExu 628 } 629 630 class MemExuInput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 631 val uop = new DynInst 632 val src = if (isVector) Vec(5, UInt(VLEN.W)) else Vec(3, UInt(XLEN.W)) 633 val iqIdx = UInt(log2Up(MemIQSizeMax).W) 634 val isFirstIssue = Bool() 635 } 636 637 class MemExuOutput(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { 638 val uop = new DynInst 639 val data = if (isVector) UInt(VLEN.W) else UInt(XLEN.W) 640 val debug = new DebugBundle 641 } 642 643 class MemMicroOpRbExt(implicit p: Parameters) extends XSBundle { 644 val uop = new DynInst 645 val flag = UInt(1.W) 646 } 647} 648