1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 34import xiangshan.frontend._ 35import xiangshan.frontend.icache.ICacheParameters 36 37import freechips.rocketchip.diplomacy.AddressSet 38import system.SoCParamsKey 39import huancun._ 40import huancun.debug._ 41import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 42 43import scala.math.min 44 45case object XSTileKey extends Field[Seq[XSCoreParameters]] 46 47case object XSCoreParamsKey extends Field[XSCoreParameters] 48 49case class XSCoreParameters 50( 51 HasPrefetch: Boolean = false, 52 HartId: Int = 0, 53 XLEN: Int = 64, 54 VLEN: Int = 128, 55 HasMExtension: Boolean = true, 56 HasCExtension: Boolean = true, 57 HasDiv: Boolean = true, 58 HasICache: Boolean = true, 59 HasDCache: Boolean = true, 60 AddrBits: Int = 64, 61 VAddrBits: Int = 39, 62 HasFPU: Boolean = true, 63 HasVPU: Boolean = true, 64 HasCustomCSRCacheOp: Boolean = true, 65 FetchWidth: Int = 8, 66 AsidLength: Int = 16, 67 EnableBPU: Boolean = true, 68 EnableBPD: Boolean = true, 69 EnableRAS: Boolean = true, 70 EnableLB: Boolean = false, 71 EnableLoop: Boolean = true, 72 EnableSC: Boolean = true, 73 EnbaleTlbDebug: Boolean = false, 74 EnableJal: Boolean = false, 75 EnableFauFTB: Boolean = true, 76 UbtbGHRLength: Int = 4, 77 // HistoryLength: Int = 512, 78 EnableGHistDiff: Boolean = true, 79 UbtbSize: Int = 256, 80 FtbSize: Int = 2048, 81 RasSize: Int = 32, 82 CacheLineSize: Int = 512, 83 FtbWays: Int = 4, 84 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 85 // Sets Hist Tag 86 // Seq(( 2048, 2, 8), 87 // ( 2048, 9, 8), 88 // ( 2048, 13, 8), 89 // ( 2048, 20, 8), 90 // ( 2048, 26, 8), 91 // ( 2048, 44, 8), 92 // ( 2048, 73, 8), 93 // ( 2048, 256, 8)), 94 Seq(( 4096, 8, 8), 95 ( 4096, 13, 8), 96 ( 4096, 32, 8), 97 ( 4096, 119, 8)), 98 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 99 // Sets Hist Tag 100 Seq(( 256, 4, 9), 101 ( 256, 8, 9), 102 ( 512, 13, 9), 103 ( 512, 16, 9), 104 ( 512, 32, 9)), 105 SCNRows: Int = 512, 106 SCNTables: Int = 4, 107 SCCtrBits: Int = 6, 108 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 109 numBr: Int = 2, 110 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 111 ((resp_in: BranchPredictionResp, p: Parameters) => { 112 val ftb = Module(new FTB()(p)) 113 val ubtb =Module(new FauFTB()(p)) 114 // val bim = Module(new BIM()(p)) 115 val tage = Module(new Tage_SC()(p)) 116 val ras = Module(new RAS()(p)) 117 val ittage = Module(new ITTage()(p)) 118 val preds = Seq(ubtb, tage, ftb, ittage, ras) 119 preds.map(_.io := DontCare) 120 121 // ubtb.io.resp_in(0) := resp_in 122 // bim.io.resp_in(0) := ubtb.io.resp 123 // btb.io.resp_in(0) := bim.io.resp 124 // tage.io.resp_in(0) := btb.io.resp 125 // loop.io.resp_in(0) := tage.io.resp 126 ubtb.io.in.bits.resp_in(0) := resp_in 127 tage.io.in.bits.resp_in(0) := ubtb.io.out 128 ftb.io.in.bits.resp_in(0) := tage.io.out 129 ittage.io.in.bits.resp_in(0) := ftb.io.out 130 ras.io.in.bits.resp_in(0) := ittage.io.out 131 132 (preds, ras.io.out) 133 }), 134 IBufSize: Int = 48, 135 DecodeWidth: Int = 6, 136 RenameWidth: Int = 6, 137 CommitWidth: Int = 6, 138 MaxUopSize: Int = 37, 139 FtqSize: Int = 64, 140 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 141 IntLogicRegs: Int = 33, 142 FpLogicRegs: Int = 33, 143 VecLogicRegs: Int = 40, 144 NRPhyRegs: Int = 192, 145 IntPhyRegs: Int = 192, 146 VfPhyRegs: Int = 192, 147 LoadQueueSize: Int = 80, 148 LoadQueueNWriteBanks: Int = 8, 149 StoreQueueSize: Int = 64, 150 StoreQueueNWriteBanks: Int = 8, 151 VlsQueueSize: Int = 8, 152 RobSize: Int = 256, 153 dpParams: DispatchParameters = DispatchParameters( 154 IntDqSize = 16, 155 FpDqSize = 16, 156 LsDqSize = 16, 157 IntDqDeqWidth = 6, 158 FpDqDeqWidth = 6, 159 LsDqDeqWidth = 6, 160 ), 161 intPreg: PregParams = IntPregParams( 162 numEntries = 64, 163 numRead = 14, 164 numWrite = 8, 165 ), 166 vfPreg: VfPregParams = VfPregParams( 167 numEntries = 64, 168 numRead = 14, 169 numWrite = 8, 170 ), 171 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 172 LoadPipelineWidth: Int = 2, 173 StorePipelineWidth: Int = 2, 174 VecMemSrcInWidth: Int = 2, 175 VecMemInstWbWidth: Int = 1, 176 VecMemDispatchWidth: Int = 1, 177 StoreBufferSize: Int = 16, 178 StoreBufferThreshold: Int = 7, 179 EnsbufferWidth: Int = 2, 180 UncacheBufferSize: Int = 4, 181 EnableLoadToLoadForward: Boolean = true, 182 EnableFastForward: Boolean = false, 183 EnableLdVioCheckAfterReset: Boolean = true, 184 EnableSoftPrefetchAfterReset: Boolean = true, 185 EnableCacheErrorAfterReset: Boolean = true, 186 EnableDCacheWPU: Boolean = false, 187 EnableAccurateLoadError: Boolean = true, 188 EnableUncacheWriteOutstanding: Boolean = false, 189 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 190 ReSelectLen: Int = 7, // load replay queue replay select counter len 191 itlbParameters: TLBParameters = TLBParameters( 192 name = "itlb", 193 fetchi = true, 194 useDmode = false, 195 normalNWays = 32, 196 normalReplacer = Some("plru"), 197 superNWays = 4, 198 superReplacer = Some("plru") 199 ), 200 ldtlbParameters: TLBParameters = TLBParameters( 201 name = "ldtlb", 202 normalNSets = 64, 203 normalNWays = 1, 204 normalAssociative = "sa", 205 normalReplacer = Some("setplru"), 206 superNWays = 16, 207 normalAsVictim = true, 208 outReplace = false, 209 partialStaticPMP = true, 210 outsideRecvFlush = true, 211 saveLevel = true 212 ), 213 sttlbParameters: TLBParameters = TLBParameters( 214 name = "sttlb", 215 normalNSets = 64, 216 normalNWays = 1, 217 normalAssociative = "sa", 218 normalReplacer = Some("setplru"), 219 superNWays = 16, 220 normalAsVictim = true, 221 outReplace = false, 222 partialStaticPMP = true, 223 outsideRecvFlush = true, 224 saveLevel = true 225 ), 226 pftlbParameters: TLBParameters = TLBParameters( 227 name = "pftlb", 228 normalNSets = 64, 229 normalNWays = 1, 230 normalAssociative = "sa", 231 normalReplacer = Some("setplru"), 232 superNWays = 16, 233 normalAsVictim = true, 234 outReplace = false, 235 partialStaticPMP = true, 236 outsideRecvFlush = true, 237 saveLevel = true 238 ), 239 refillBothTlb: Boolean = false, 240 btlbParameters: TLBParameters = TLBParameters( 241 name = "btlb", 242 normalNSets = 1, 243 normalNWays = 64, 244 superNWays = 4, 245 ), 246 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 247 NumPerfCounters: Int = 16, 248 icacheParameters: ICacheParameters = ICacheParameters( 249 tagECC = Some("parity"), 250 dataECC = Some("parity"), 251 replacer = Some("setplru"), 252 nMissEntries = 2, 253 nProbeEntries = 2, 254 nPrefetchEntries = 2, 255 hasPrefetch = true, 256 ), 257 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 258 tagECC = Some("secded"), 259 dataECC = Some("secded"), 260 replacer = Some("setplru"), 261 nMissEntries = 16, 262 nProbeEntries = 8, 263 nReleaseEntries = 18 264 )), 265 L2CacheParamsOpt: Option[HCCacheParameters] = Some(HCCacheParameters( 266 name = "l2", 267 level = 2, 268 ways = 8, 269 sets = 1024, // default 512KB L2 270 prefetch = Some(huancun.prefetch.PrefetchReceiverParams()) 271 )), 272 L2NBanks: Int = 1, 273 usePTWRepeater: Boolean = false, 274 softTLB: Boolean = false, // dpi-c l1tlb debug only 275 softPTW: Boolean = false, // dpi-c l2tlb debug only 276 softPTWDelay: Int = 1 277){ 278 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 279 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 280 281 def intSchdParams = { 282 implicit val schdType: SchedulerType = IntScheduler() 283 val pregBits = intPreg.addrWidth 284 val numRfRead = intPreg.numRead 285 val numRfWrite = intPreg.numWrite 286 SchdBlockParams(Seq( 287 IssueBlockParams(Seq( 288 ExeUnitParams(Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 2)), Seq(IntRD(1, 2)))), 289 ExeUnitParams(Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(0, 1)), Seq(IntRD(1, 1)))), 290 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 291 IssueBlockParams(Seq( 292 ExeUnitParams(Seq(DivCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0)))), 293 ExeUnitParams(Seq(DivCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 294 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 295 IssueBlockParams(Seq( 296 ExeUnitParams(Seq(BrhCfg, JmpCfg, CsrCfg, FenceCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 297 ExeUnitParams(Seq(BrhCfg), Seq(), Seq(Seq(IntRD(6, 1)), Seq(IntRD(4, 1)))), 298 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2), 299 IssueBlockParams(Seq( 300 ExeUnitParams(Seq(I2fCfg, VSetIVLCfg, VSetIVConfigCfg), Seq(VecWB(port = 6, Int.MaxValue), IntWB(port = 7, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 301 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 2) 302 ), 303 numPregs = intPreg.numEntries, 304 numRfReadWrite = Some((numRfRead, numRfWrite)), 305 numDeqOutside = 0, 306 schdType = schdType, 307 rfDataWidth = intPreg.dataCfg.dataWidth, 308 numUopIn = dpParams.IntDqDeqWidth, 309 ) 310 } 311 def vfSchdParams = { 312 implicit val schdType: SchedulerType = VfScheduler() 313 val pregBits = vfPreg.addrWidth 314 val numRfRead = vfPreg.numRead 315 val numRfWrite = vfPreg.numWrite 316 SchdBlockParams(Seq( 317 IssueBlockParams(Seq( 318 ExeUnitParams(Seq(FmacCfg), Seq(VecWB(port = 0, 0)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)))), 319 ExeUnitParams(Seq(FmacCfg), Seq(VecWB(port = 1, 0)), Seq(Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 320 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 4), 321 IssueBlockParams(Seq( 322 ExeUnitParams(Seq(F2fCfg, F2iCfg, FDivSqrtCfg, VSetFVConfigCfg), Seq(VecWB(port = 2, 0), IntWB(port = 7, 0)), Seq(Seq(VfRD(6, 0)), Seq(VfRD(7, 0)))), 323 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = numRfWrite, numEnq = 4), 324 325 ), 326 numPregs = vfPreg.numEntries, 327 numRfReadWrite = Some((numRfRead, numRfWrite)), 328 numDeqOutside = 0, 329 schdType = schdType, 330 rfDataWidth = vfPreg.dataCfg.dataWidth, 331 numUopIn = dpParams.FpDqDeqWidth, 332 ) 333 } 334 def memSchdParams = { 335 implicit val schdType: SchedulerType = MemScheduler() 336 val pregBits = vfPreg.addrWidth max intPreg.addrWidth 337 val rfDataWidth = 64 338 339 SchdBlockParams(Seq( 340 IssueBlockParams(Seq( 341 ExeUnitParams(Seq(LduCfg), Seq(IntWB(5, 0), VecWB(4, 0)), Seq(Seq(IntRD(8, 0)))), 342 ExeUnitParams(Seq(LduCfg), Seq(IntWB(6, 0), VecWB(5, 0)), Seq(Seq(IntRD(9, 0)))), 343 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 344 IssueBlockParams(Seq( 345 ExeUnitParams(Seq(StaCfg, MouCfg), Seq(IntWB(5, 1)), Seq(Seq(IntRD(10, 0)))), 346 ExeUnitParams(Seq(StaCfg, MouCfg), Seq(IntWB(6, 1)), Seq(Seq(IntRD(11, 0)))), 347 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 348 IssueBlockParams(Seq( 349 ExeUnitParams(Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(12, 0), VfRD(12, 0)))), 350 ExeUnitParams(Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(13, 0), VfRD(13, 0)))), 351 ), numEntries = 8, pregBits = pregBits, numWakeupFromWB = 16, numEnq = 2), 352 ), 353 numPregs = intPreg.numEntries max vfPreg.numEntries, 354 numRfReadWrite = None, 355 numDeqOutside = 0, 356 schdType = schdType, 357 rfDataWidth = rfDataWidth, 358 numUopIn = dpParams.LsDqDeqWidth, 359 ) 360 } 361 362 def backendParams: BackendParams = backend.BackendParams(Map( 363 IntScheduler() -> intSchdParams, 364 VfScheduler() -> vfSchdParams, 365 MemScheduler() -> memSchdParams, 366 ), Seq( 367 intPreg, 368 vfPreg, 369 )) 370} 371 372case object DebugOptionsKey extends Field[DebugOptions] 373 374case class DebugOptions 375( 376 FPGAPlatform: Boolean = false, 377 EnableDifftest: Boolean = false, 378 AlwaysBasicDiff: Boolean = true, 379 EnableDebug: Boolean = false, 380 EnablePerfDebug: Boolean = true, 381 UseDRAMSim: Boolean = false, 382 EnableTopDown: Boolean = false 383) 384 385trait HasXSParameter { 386 387 implicit val p: Parameters 388 389 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 390 391 val coreParams = p(XSCoreParamsKey) 392 val env = p(DebugOptionsKey) 393 394 val XLEN = coreParams.XLEN 395 val VLEN = coreParams.VLEN 396 val minFLen = 32 397 val fLen = 64 398 def xLen = XLEN 399 400 val HasMExtension = coreParams.HasMExtension 401 val HasCExtension = coreParams.HasCExtension 402 val HasDiv = coreParams.HasDiv 403 val HasIcache = coreParams.HasICache 404 val HasDcache = coreParams.HasDCache 405 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 406 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 407 val AsidLength = coreParams.AsidLength 408 val ReSelectLen = coreParams.ReSelectLen 409 val AddrBytes = AddrBits / 8 // unused 410 val DataBits = XLEN 411 val DataBytes = DataBits / 8 412 val HasFPU = coreParams.HasFPU 413 val HasVPU = coreParams.HasVPU 414 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 415 val FetchWidth = coreParams.FetchWidth 416 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 417 val EnableBPU = coreParams.EnableBPU 418 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 419 val EnableRAS = coreParams.EnableRAS 420 val EnableLB = coreParams.EnableLB 421 val EnableLoop = coreParams.EnableLoop 422 val EnableSC = coreParams.EnableSC 423 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 424 val HistoryLength = coreParams.HistoryLength 425 val EnableGHistDiff = coreParams.EnableGHistDiff 426 val UbtbGHRLength = coreParams.UbtbGHRLength 427 val UbtbSize = coreParams.UbtbSize 428 val EnableFauFTB = coreParams.EnableFauFTB 429 val FtbSize = coreParams.FtbSize 430 val FtbWays = coreParams.FtbWays 431 val RasSize = coreParams.RasSize 432 433 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 434 coreParams.branchPredictor(resp_in, p) 435 } 436 val numBr = coreParams.numBr 437 val TageTableInfos = coreParams.TageTableInfos 438 val TageBanks = coreParams.numBr 439 val SCNRows = coreParams.SCNRows 440 val SCCtrBits = coreParams.SCCtrBits 441 val SCHistLens = coreParams.SCHistLens 442 val SCNTables = coreParams.SCNTables 443 444 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 445 case ((n, cb), h) => (n, cb, h) 446 } 447 val ITTageTableInfos = coreParams.ITTageTableInfos 448 type FoldedHistoryInfo = Tuple2[Int, Int] 449 val foldedGHistInfos = 450 (TageTableInfos.map{ case (nRows, h, t) => 451 if (h > 0) 452 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 453 else 454 Set[FoldedHistoryInfo]() 455 }.reduce(_++_).toSet ++ 456 SCTableInfos.map{ case (nRows, _, h) => 457 if (h > 0) 458 Set((h, min(log2Ceil(nRows/TageBanks), h))) 459 else 460 Set[FoldedHistoryInfo]() 461 }.reduce(_++_).toSet ++ 462 ITTageTableInfos.map{ case (nRows, h, t) => 463 if (h > 0) 464 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 465 else 466 Set[FoldedHistoryInfo]() 467 }.reduce(_++_) ++ 468 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 469 ).toList 470 471 472 473 val CacheLineSize = coreParams.CacheLineSize 474 val CacheLineHalfWord = CacheLineSize / 16 475 val ExtHistoryLength = HistoryLength + 64 476 val IBufSize = coreParams.IBufSize 477 val DecodeWidth = coreParams.DecodeWidth 478 val RenameWidth = coreParams.RenameWidth 479 val CommitWidth = coreParams.CommitWidth 480 val MaxUopSize = coreParams.MaxUopSize 481 val FtqSize = coreParams.FtqSize 482 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 483 val IntLogicRegs = coreParams.IntLogicRegs 484 val FpLogicRegs = coreParams.FpLogicRegs 485 val VecLogicRegs = coreParams.VecLogicRegs 486 val NRPhyRegs = coreParams.NRPhyRegs 487 val PhyRegIdxWidth = log2Up(NRPhyRegs) 488 val IntPhyRegs = coreParams.IntPhyRegs 489 val VfPhyRegs = coreParams.VfPhyRegs 490 val IntPregIdxWidth = log2Up(IntPhyRegs) 491 val VfPregIdxWidth = log2Up(VfPhyRegs) 492 val RobSize = coreParams.RobSize 493 val IntRefCounterWidth = log2Ceil(RobSize) 494 val LoadQueueSize = coreParams.LoadQueueSize 495 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 496 val StoreQueueSize = coreParams.StoreQueueSize 497 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 498 val VlsQueueSize = coreParams.VlsQueueSize 499 val dpParams = coreParams.dpParams 500 501 def backendParams: BackendParams = coreParams.backendParams 502 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 503 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 504 val LoadPipelineWidth = coreParams.LoadPipelineWidth 505 val StorePipelineWidth = coreParams.StorePipelineWidth 506 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 507 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 508 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 509 val StoreBufferSize = coreParams.StoreBufferSize 510 val StoreBufferThreshold = coreParams.StoreBufferThreshold 511 val EnsbufferWidth = coreParams.EnsbufferWidth 512 val UncacheBufferSize = coreParams.UncacheBufferSize 513 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 514 val EnableFastForward = coreParams.EnableFastForward 515 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 516 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 517 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 518 val EnableDCacheWPU = coreParams.EnableDCacheWPU 519 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 520 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 521 val asidLen = coreParams.MMUAsidLen 522 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 523 val refillBothTlb = coreParams.refillBothTlb 524 val itlbParams = coreParams.itlbParameters 525 val ldtlbParams = coreParams.ldtlbParameters 526 val sttlbParams = coreParams.sttlbParameters 527 val pftlbParams = coreParams.pftlbParameters 528 val btlbParams = coreParams.btlbParameters 529 val l2tlbParams = coreParams.l2tlbParameters 530 val NumPerfCounters = coreParams.NumPerfCounters 531 532 val instBytes = if (HasCExtension) 2 else 4 533 val instOffsetBits = log2Ceil(instBytes) 534 535 val icacheParameters = coreParams.icacheParameters 536 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 537 538 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 539 // for constrained LR/SC loop 540 val LRSCCycles = 64 541 // for lr storm 542 val LRSCBackOff = 8 543 544 // cache hierarchy configurations 545 val l1BusDataWidth = 256 546 547 // load violation predict 548 val ResetTimeMax2Pow = 20 //1078576 549 val ResetTimeMin2Pow = 10 //1024 550 // wait table parameters 551 val WaitTableSize = 1024 552 val MemPredPCWidth = log2Up(WaitTableSize) 553 val LWTUse2BitCounter = true 554 // store set parameters 555 val SSITSize = WaitTableSize 556 val LFSTSize = 32 557 val SSIDWidth = log2Up(LFSTSize) 558 val LFSTWidth = 4 559 val StoreSetEnable = true // LWT will be disabled if SS is enabled 560 561 val PCntIncrStep: Int = 6 562 val numPCntHc: Int = 25 563 val numPCntPtw: Int = 19 564 565 val numCSRPCntFrontend = 8 566 val numCSRPCntCtrl = 8 567 val numCSRPCntLsu = 8 568 val numCSRPCntHc = 5 569} 570