1package xiangshan.backend 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.ZeroExt 8import xiangshan._ 9import xiangshan.backend.Bundles.{DynInst, IssueQueueIQWakeUpBundle, MemExuInput, MemExuOutput} 10import xiangshan.backend.ctrlblock.CtrlBlock 11import xiangshan.backend.datapath.DataConfig.{IntData, VecData} 12import xiangshan.backend.datapath.RdConfig.{IntRD, VfRD} 13import xiangshan.backend.datapath.WbConfig._ 14import xiangshan.backend.datapath._ 15import xiangshan.backend.exu.ExuBlock 16import xiangshan.backend.fu.vector.Bundles.{VConfig, VType} 17import xiangshan.backend.fu.{FenceIO, FenceToSbuffer, FuConfig, PerfCounterIO} 18import xiangshan.backend.issue.{CancelNetwork, Scheduler} 19import xiangshan.backend.rob.RobLsqIO 20import xiangshan.frontend.{FtqPtr, FtqRead} 21import xiangshan.mem.{LqPtr, LsqEnqIO, SqPtr} 22 23class Backend(val params: BackendParams)(implicit p: Parameters) extends LazyModule 24 with HasXSParameter { 25 26 /* Only update the idx in mem-scheduler here 27 * Idx in other schedulers can be updated the same way if needed 28 * 29 * Also note that we filter out the 'stData issue-queues' when counting 30 */ 31 for ((ibp, idx) <- params.memSchdParams.get.issueBlockParams.filter(iq => iq.StdCnt == 0).zipWithIndex) { 32 ibp.updateIdx(idx) 33 } 34 35 println(params.iqWakeUpParams) 36 37 for ((schdCfg, i) <- params.allSchdParams.zipWithIndex) { 38 schdCfg.bindBackendParam(params) 39 } 40 41 for ((iqCfg, i) <- params.allIssueParams.zipWithIndex) { 42 iqCfg.bindBackendParam(params) 43 } 44 45 for ((exuCfg, i) <- params.allExuParams.zipWithIndex) { 46 exuCfg.updateIQWakeUpConfigs(params.iqWakeUpParams) 47 exuCfg.updateExuIdx(i) 48 exuCfg.bindBackendParam(params) 49 } 50 51 println("[Backend] ExuConfigs:") 52 for (exuCfg <- params.allExuParams) { 53 val fuConfigs = exuCfg.fuConfigs 54 val wbPortConfigs = exuCfg.wbPortConfigs 55 val immType = exuCfg.immType 56 57 println("[Backend] " + 58 s"${exuCfg.name}: " + 59 s"${fuConfigs.map(_.name).mkString("fu(s): {", ",", "}")}, " + 60 s"${wbPortConfigs.mkString("wb: {", ",", "}")}, " + 61 s"${immType.map(SelImm.mkString(_)).mkString("imm: {", ",", "}")}, " + 62 s"latMax(${exuCfg.latencyValMax}), ${exuCfg.fuLatancySet.mkString("lat: {", ",", "}")}, " 63 ) 64 require( 65 wbPortConfigs.collectFirst { case x: IntWB => x }.nonEmpty == 66 fuConfigs.map(_.writeIntRf).reduce(_ || _), 67 "int wb port has no priority" 68 ) 69 require( 70 wbPortConfigs.collectFirst { case x: VfWB => x }.nonEmpty == 71 fuConfigs.map(x => x.writeFpRf || x.writeVecRf).reduce(_ || _), 72 "vec wb port has no priority" 73 ) 74 } 75 76 println(s"[Backend] all fu configs") 77 for (cfg <- FuConfig.allConfigs) { 78 println(s"[Backend] $cfg") 79 } 80 81 println(s"[Backend] Int RdConfigs: ExuName(Priority)") 82 for ((port, seq) <- params.getRdPortParams(IntData())) { 83 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 84 } 85 86 println(s"[Backend] Int WbConfigs: ExuName(Priority)") 87 for ((port, seq) <- params.getWbPortParams(IntData())) { 88 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 89 } 90 91 println(s"[Backend] Vf RdConfigs: ExuName(Priority)") 92 for ((port, seq) <- params.getRdPortParams(VecData())) { 93 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 94 } 95 96 println(s"[Backend] Vf WbConfigs: ExuName(Priority)") 97 for ((port, seq) <- params.getWbPortParams(VecData())) { 98 println(s"[Backend] port($port): ${seq.map(x => params.getExuName(x._1) + "(" + x._2.toString + ")").mkString(",")}") 99 } 100 101 val ctrlBlock = LazyModule(new CtrlBlock(params)) 102 val intScheduler = params.intSchdParams.map(x => LazyModule(new Scheduler(x))) 103 val vfScheduler = params.vfSchdParams.map(x => LazyModule(new Scheduler(x))) 104 val memScheduler = params.memSchdParams.map(x => LazyModule(new Scheduler(x))) 105 val cancelNetwork = LazyModule(new CancelNetwork(params)) 106 val dataPath = LazyModule(new DataPath(params)) 107 val intExuBlock = params.intSchdParams.map(x => LazyModule(new ExuBlock(x))) 108 val vfExuBlock = params.vfSchdParams.map(x => LazyModule(new ExuBlock(x))) 109 val wbFuBusyTable = LazyModule(new WbFuBusyTable(params)) 110 111 lazy val module = new BackendImp(this) 112} 113 114class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends LazyModuleImp(wrapper) 115 with HasXSParameter { 116 implicit private val params = wrapper.params 117 val io = IO(new BackendIO()(p, wrapper.params)) 118 119 private val ctrlBlock = wrapper.ctrlBlock.module 120 private val intScheduler = wrapper.intScheduler.get.module 121 private val vfScheduler = wrapper.vfScheduler.get.module 122 private val memScheduler = wrapper.memScheduler.get.module 123 private val cancelNetwork = wrapper.cancelNetwork.module 124 private val dataPath = wrapper.dataPath.module 125 private val intExuBlock = wrapper.intExuBlock.get.module 126 private val vfExuBlock = wrapper.vfExuBlock.get.module 127 private val bypassNetwork = Module(new BypassNetwork) 128 private val wbDataPath = Module(new WbDataPath(params)) 129 private val wbFuBusyTable = wrapper.wbFuBusyTable.module 130 131 private val iqWakeUpMappedBundle: Map[Int, ValidIO[IssueQueueIQWakeUpBundle]] = ( 132 intScheduler.io.toSchedulers.wakeupVec ++ 133 vfScheduler.io.toSchedulers.wakeupVec ++ 134 memScheduler.io.toSchedulers.wakeupVec 135 ).map(x => (x.bits.exuIdx, x)).toMap 136 137 println(s"[Backend] iq wake up keys: ${iqWakeUpMappedBundle.keys}") 138 139 wbFuBusyTable.io.in.intSchdBusyTable := intScheduler.io.wbFuBusyTable 140 wbFuBusyTable.io.in.vfSchdBusyTable := vfScheduler.io.wbFuBusyTable 141 wbFuBusyTable.io.in.memSchdBusyTable := memScheduler.io.wbFuBusyTable 142 intScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.intRespRead 143 vfScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.vfRespRead 144 memScheduler.io.fromWbFuBusyTable.fuBusyTableRead := wbFuBusyTable.io.out.memRespRead 145 dataPath.io.wbConfictRead := wbFuBusyTable.io.out.wbConflictRead 146 147 wbDataPath.io.fromIntExu.flatten.filter(x => x.bits.params.writeIntRf) 148 149 private val vconfig = dataPath.io.vconfigReadPort.data 150 private val og1CancelVec: Vec[Bool] = dataPath.io.og1CancelVec 151 private val og0CancelVecFromDataPath: Vec[Bool] = dataPath.io.og0CancelVec 152 private val og0CancelVecFromCancelNet: Vec[Bool] = cancelNetwork.io.out.og0CancelVec 153 private val og0CancelVec: Vec[Bool] = VecInit(og0CancelVecFromDataPath.zip(og0CancelVecFromCancelNet).map(x => x._1 | x._2)) 154 155 ctrlBlock.io.fromTop.hartId := io.fromTop.hartId 156 ctrlBlock.io.frontend <> io.frontend 157 ctrlBlock.io.fromWB.wbData <> wbDataPath.io.toCtrlBlock.writeback 158 ctrlBlock.io.fromMem.stIn <> io.mem.stIn 159 ctrlBlock.io.fromMem.violation <> io.mem.memoryViolation 160 ctrlBlock.io.csrCtrl <> intExuBlock.io.csrio.get.customCtrl 161 ctrlBlock.io.robio.csr.intrBitSet := intExuBlock.io.csrio.get.interrupt 162 ctrlBlock.io.robio.csr.trapTarget := intExuBlock.io.csrio.get.trapTarget 163 ctrlBlock.io.robio.csr.isXRet := intExuBlock.io.csrio.get.isXRet 164 ctrlBlock.io.robio.csr.wfiEvent := intExuBlock.io.csrio.get.wfi_event 165 ctrlBlock.io.robio.lsq <> io.mem.robLsqIO 166 ctrlBlock.io.fromDataPath.vtype := vconfig(7, 0).asTypeOf(new VType) 167 168 intScheduler.io.fromTop.hartId := io.fromTop.hartId 169 intScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 170 intScheduler.io.fromCtrlBlock.pcVec := ctrlBlock.io.toIssueBlock.pcVec 171 intScheduler.io.fromCtrlBlock.targetVec := ctrlBlock.io.toIssueBlock.targetVec 172 intScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 173 intScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.intUops 174 intScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 175 intScheduler.io.vfWriteBack := 0.U.asTypeOf(intScheduler.io.vfWriteBack) 176 intScheduler.io.fromDataPath.resp := dataPath.io.toIntIQ 177 intScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 178 intScheduler.io.fromDataPath.og0Cancel := og0CancelVec 179 intScheduler.io.fromDataPath.og1Cancel := og1CancelVec 180 181 memScheduler.io.fromTop.hartId := io.fromTop.hartId 182 memScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 183 memScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 184 memScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.memUops 185 memScheduler.io.intWriteBack := wbDataPath.io.toIntPreg 186 memScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 187 memScheduler.io.fromMem.get.scommit := io.mem.sqDeq 188 memScheduler.io.fromMem.get.lcommit := io.mem.lqDeq 189 memScheduler.io.fromMem.get.sqCancelCnt := io.mem.sqCancelCnt 190 memScheduler.io.fromMem.get.lqCancelCnt := io.mem.lqCancelCnt 191 memScheduler.io.fromMem.get.stIssuePtr := io.mem.stIssuePtr 192 memScheduler.io.fromMem.get.memWaitUpdateReq.staIssue.zip(io.mem.stIn).foreach { case (sink, source) => 193 sink.valid := source.valid 194 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 195 sink.bits.uop.robIdx := source.bits.robIdx 196 } 197 memScheduler.io.fromDataPath.resp := dataPath.io.toMemIQ 198 memScheduler.io.fromMem.get.ldaFeedback := io.mem.ldaIqFeedback 199 memScheduler.io.fromMem.get.staFeedback := io.mem.staIqFeedback 200 memScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 201 memScheduler.io.fromDataPath.og0Cancel := og0CancelVec 202 memScheduler.io.fromDataPath.og1Cancel := og1CancelVec 203 204 vfScheduler.io.fromTop.hartId := io.fromTop.hartId 205 vfScheduler.io.fromCtrlBlock.flush := ctrlBlock.io.toIssueBlock.flush 206 vfScheduler.io.fromDispatch.allocPregs <> ctrlBlock.io.toIssueBlock.allocPregs 207 vfScheduler.io.fromDispatch.uops <> ctrlBlock.io.toIssueBlock.vfUops 208 vfScheduler.io.intWriteBack := 0.U.asTypeOf(vfScheduler.io.intWriteBack) 209 vfScheduler.io.vfWriteBack := wbDataPath.io.toVfPreg 210 vfScheduler.io.fromDataPath.resp := dataPath.io.toVfIQ 211 vfScheduler.io.fromSchedulers.wakeupVec.foreach { wakeup => wakeup := iqWakeUpMappedBundle(wakeup.bits.exuIdx) } 212 vfScheduler.io.fromDataPath.og0Cancel := og0CancelVec 213 vfScheduler.io.fromDataPath.og1Cancel := og1CancelVec 214 215 cancelNetwork.io.in.int <> intScheduler.io.toDataPath 216 cancelNetwork.io.in.vf <> vfScheduler.io.toDataPath 217 cancelNetwork.io.in.mem <> memScheduler.io.toDataPath 218 cancelNetwork.io.in.og0CancelVec := og0CancelVecFromDataPath 219 cancelNetwork.io.in.og1CancelVec := og1CancelVec 220 intScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.int 221 vfScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.vf 222 memScheduler.io.fromCancelNetwork <> cancelNetwork.io.out.mem 223 224 dataPath.io.flush := ctrlBlock.io.toDataPath.flush 225 dataPath.io.vconfigReadPort.addr := ctrlBlock.io.toDataPath.vtypeAddr 226 227 dataPath.io.fromIntIQ <> intScheduler.io.toDataPathAfterDelay 228 dataPath.io.fromVfIQ <> vfScheduler.io.toDataPathAfterDelay 229 dataPath.io.fromMemIQ <> memScheduler.io.toDataPathAfterDelay 230 231 println(s"[Backend] wbDataPath.io.toIntPreg: ${wbDataPath.io.toIntPreg.size}, dataPath.io.fromIntWb: ${dataPath.io.fromIntWb.size}") 232 println(s"[Backend] wbDataPath.io.toVfPreg: ${wbDataPath.io.toVfPreg.size}, dataPath.io.fromFpWb: ${dataPath.io.fromVfWb.size}") 233 dataPath.io.fromIntWb := wbDataPath.io.toIntPreg 234 dataPath.io.fromVfWb := wbDataPath.io.toVfPreg 235 dataPath.io.debugIntRat := ctrlBlock.io.debug_int_rat 236 dataPath.io.debugFpRat := ctrlBlock.io.debug_fp_rat 237 dataPath.io.debugVecRat := ctrlBlock.io.debug_vec_rat 238 dataPath.io.debugVconfigRat := ctrlBlock.io.debug_vconfig_rat 239 240 bypassNetwork.io.fromDataPath.int <> dataPath.io.toIntExu 241 bypassNetwork.io.fromDataPath.vf <> dataPath.io.toFpExu 242 bypassNetwork.io.fromDataPath.mem <> dataPath.io.toMemExu 243 bypassNetwork.io.fromExus.connectExuOutput(_.int)(intExuBlock.io.out) 244 bypassNetwork.io.fromExus.connectExuOutput(_.vf)(vfExuBlock.io.out) 245 bypassNetwork.io.fromExus.mem.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 246 sink.valid := source.valid 247 sink.bits.pdest := source.bits.uop.pdest 248 sink.bits.data := source.bits.data 249 } 250 251 intExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 252 for (i <- 0 until intExuBlock.io.in.length) { 253 for (j <- 0 until intExuBlock.io.in(i).length) { 254 NewPipelineConnect( 255 bypassNetwork.io.toExus.int(i)(j), intExuBlock.io.in(i)(j), intExuBlock.io.in(i)(j).fire, 256 Mux( 257 bypassNetwork.io.toExus.int(i)(j).fire, 258 bypassNetwork.io.toExus.int(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 259 intExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 260 ) 261 ) 262 } 263 } 264 265 private val csrio = intExuBlock.io.csrio.get 266 csrio.hartId := io.fromTop.hartId 267 csrio.perf.retiredInstr <> ctrlBlock.io.robio.csr.perfinfo.retiredInstr 268 csrio.perf.ctrlInfo <> ctrlBlock.io.perfInfo.ctrlInfo 269 csrio.perf.perfEventsCtrl <> ctrlBlock.getPerf 270 csrio.fpu.fflags := ctrlBlock.io.robio.csr.fflags 271 csrio.fpu.isIllegal := false.B // Todo: remove it 272 csrio.fpu.dirty_fs := ctrlBlock.io.robio.csr.dirty_fs 273 csrio.vpu <> 0.U.asTypeOf(csrio.vpu) // Todo 274 275 val debugVconfig = dataPath.io.debugVconfig.asTypeOf(new VConfig) 276 val debugVtype = VType.toVtypeStruct(debugVconfig.vtype).asUInt 277 val debugVl = debugVconfig.vl 278 csrio.vpu.set_vxsat := ctrlBlock.io.robio.csr.vxsat 279 csrio.vpu.set_vstart.valid := ctrlBlock.io.robio.csr.vcsrFlag 280 csrio.vpu.set_vstart.bits := 0.U 281 csrio.vpu.set_vtype.valid := ctrlBlock.io.robio.csr.vcsrFlag 282 csrio.vpu.set_vtype.bits := ZeroExt(debugVtype, XLEN) 283 csrio.vpu.set_vl.valid := ctrlBlock.io.robio.csr.vcsrFlag 284 csrio.vpu.set_vl.bits := ZeroExt(debugVl, XLEN) 285 csrio.exception := ctrlBlock.io.robio.exception 286 csrio.memExceptionVAddr := io.mem.exceptionVAddr 287 csrio.externalInterrupt := io.fromTop.externalInterrupt 288 csrio.distributedUpdate(0) := io.mem.csrDistributedUpdate 289 csrio.distributedUpdate(1) := io.frontendCsrDistributedUpdate 290 csrio.perf <> io.perf 291 private val fenceio = intExuBlock.io.fenceio.get 292 fenceio.disableSfence := csrio.disableSfence 293 io.fenceio <> fenceio 294 295 vfExuBlock.io.flush := ctrlBlock.io.toExuBlock.flush 296 for (i <- 0 until vfExuBlock.io.in.size) { 297 for (j <- 0 until vfExuBlock.io.in(i).size) { 298 NewPipelineConnect( 299 bypassNetwork.io.toExus.vf(i)(j), vfExuBlock.io.in(i)(j), vfExuBlock.io.in(i)(j).fire, 300 Mux( 301 bypassNetwork.io.toExus.vf(i)(j).fire, 302 bypassNetwork.io.toExus.vf(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 303 vfExuBlock.io.in(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 304 ) 305 ) 306 } 307 } 308 vfExuBlock.io.frm.foreach(_ := csrio.fpu.frm) 309 310 wbDataPath.io.flush := ctrlBlock.io.redirect 311 wbDataPath.io.fromTop.hartId := io.fromTop.hartId 312 wbDataPath.io.fromIntExu <> intExuBlock.io.out 313 wbDataPath.io.fromVfExu <> vfExuBlock.io.out 314 wbDataPath.io.fromMemExu.flatten.zip(io.mem.writeBack).foreach { case (sink, source) => 315 sink.valid := source.valid 316 source.ready := sink.ready 317 sink.bits.data := source.bits.data 318 sink.bits.pdest := source.bits.uop.pdest 319 sink.bits.robIdx := source.bits.uop.robIdx 320 sink.bits.intWen.foreach(_ := source.bits.uop.rfWen) 321 sink.bits.fpWen.foreach(_ := source.bits.uop.fpWen) 322 sink.bits.vecWen.foreach(_ := source.bits.uop.vecWen) 323 sink.bits.exceptionVec.foreach(_ := source.bits.uop.exceptionVec) 324 sink.bits.flushPipe.foreach(_ := source.bits.uop.flushPipe) 325 sink.bits.replay.foreach(_ := source.bits.uop.replayInst) 326 sink.bits.debug := source.bits.debug 327 sink.bits.debugInfo := 0.U.asTypeOf(sink.bits.debugInfo) 328 sink.bits.lqIdx.foreach(_ := source.bits.uop.lqIdx) 329 sink.bits.sqIdx.foreach(_ := source.bits.uop.sqIdx) 330 sink.bits.ftqIdx.foreach(_ := source.bits.uop.ftqPtr) 331 sink.bits.ftqOffset.foreach(_ := source.bits.uop.ftqOffset) 332 } 333 334 // to mem 335 private val toMem = Wire(bypassNetwork.io.toExus.mem.cloneType) 336 for (i <- toMem.indices) { 337 for (j <- toMem(i).indices) { 338 NewPipelineConnect( 339 bypassNetwork.io.toExus.mem(i)(j), toMem(i)(j), toMem(i)(j).fire, 340 Mux( 341 bypassNetwork.io.toExus.mem(i)(j).fire, 342 bypassNetwork.io.toExus.mem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush), 343 toMem(i)(j).bits.robIdx.needFlush(ctrlBlock.io.toExuBlock.flush) 344 ) 345 ) 346 } 347 } 348 349 io.mem.redirect := ctrlBlock.io.redirect 350 io.mem.issueUops.zip(toMem.flatten).foreach { case (sink, source) => 351 sink.valid := source.valid 352 source.ready := sink.ready 353 sink.bits.iqIdx := source.bits.iqIdx 354 sink.bits.isFirstIssue := source.bits.isFirstIssue 355 sink.bits.uop := 0.U.asTypeOf(sink.bits.uop) 356 sink.bits.src := 0.U.asTypeOf(sink.bits.src) 357 sink.bits.src.zip(source.bits.src).foreach { case (l, r) => l := r} 358 sink.bits.uop.fuType := source.bits.fuType 359 sink.bits.uop.fuOpType := source.bits.fuOpType 360 sink.bits.uop.imm := source.bits.imm 361 sink.bits.uop.robIdx := source.bits.robIdx 362 sink.bits.uop.pdest := source.bits.pdest 363 sink.bits.uop.rfWen := source.bits.rfWen.getOrElse(false.B) 364 sink.bits.uop.fpWen := source.bits.fpWen.getOrElse(false.B) 365 sink.bits.uop.vecWen := source.bits.vecWen.getOrElse(false.B) 366 sink.bits.uop.flushPipe := source.bits.flushPipe.getOrElse(false.B) 367 sink.bits.uop.pc := source.bits.pc.getOrElse(0.U) 368 sink.bits.uop.lqIdx := source.bits.lqIdx.getOrElse(0.U.asTypeOf(new LqPtr)) 369 sink.bits.uop.sqIdx := source.bits.sqIdx.getOrElse(0.U.asTypeOf(new SqPtr)) 370 sink.bits.uop.ftqPtr := source.bits.ftqIdx.getOrElse(0.U.asTypeOf(new FtqPtr)) 371 sink.bits.uop.ftqOffset := source.bits.ftqOffset.getOrElse(0.U) 372 } 373 io.mem.loadFastMatch := memScheduler.io.toMem.get.loadFastMatch.map(_.fastMatch) 374 io.mem.loadFastImm := memScheduler.io.toMem.get.loadFastMatch.map(_.fastImm) 375 io.mem.tlbCsr := csrio.tlb 376 io.mem.csrCtrl := csrio.customCtrl 377 io.mem.sfence := fenceio.sfence 378 io.mem.isStoreException := CommitType.lsInstIsStore(ctrlBlock.io.robio.exception.bits.commitType) 379 require(io.mem.loadPcRead.size == params.LduCnt) 380 io.mem.loadPcRead.zipWithIndex.foreach { case (loadPcRead, i) => 381 loadPcRead.data := ctrlBlock.io.memLdPcRead(i).data 382 ctrlBlock.io.memLdPcRead(i).ptr := loadPcRead.ptr 383 ctrlBlock.io.memLdPcRead(i).offset := loadPcRead.offset 384 } 385 // mem io 386 io.mem.lsqEnqIO <> memScheduler.io.memIO.get.lsqEnqIO 387 io.mem.robLsqIO <> ctrlBlock.io.robio.lsq 388 io.mem.toSbuffer <> fenceio.sbuffer 389 390 io.frontendSfence := fenceio.sfence 391 io.frontendTlbCsr := csrio.tlb 392 io.frontendCsrCtrl := csrio.customCtrl 393 394 io.tlb <> csrio.tlb 395 396 io.csrCustomCtrl := csrio.customCtrl 397 398 dontTouch(memScheduler.io) 399 dontTouch(io.mem) 400 dontTouch(dataPath.io.toMemExu) 401 dontTouch(wbDataPath.io.fromMemExu) 402} 403 404class BackendMemIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 405 // params alias 406 private val LoadQueueSize = VirtualLoadQueueSize 407 // In/Out // Todo: split it into one-direction bundle 408 val lsqEnqIO = Flipped(new LsqEnqIO) 409 val robLsqIO = new RobLsqIO 410 val toSbuffer = new FenceToSbuffer 411 val ldaIqFeedback = Vec(params.LduCnt, Flipped(new MemRSFeedbackIO)) 412 val staIqFeedback = Vec(params.StaCnt, Flipped(new MemRSFeedbackIO)) 413 val loadPcRead = Vec(params.LduCnt, Flipped(new FtqRead(UInt(VAddrBits.W)))) 414 415 // Input 416 val writeBack = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(Flipped(DecoupledIO(new MemExuOutput()))) ++ Seq.fill(params.VlduCnt)(Flipped(DecoupledIO(new MemExuOutput(true))))) 417 418 val s3_delayed_load_error = Input(Vec(LoadPipelineWidth, Bool())) 419 val stIn = Input(Vec(params.StaCnt, ValidIO(new DynInst()))) 420 val memoryViolation = Flipped(ValidIO(new Redirect)) 421 val exceptionVAddr = Input(UInt(VAddrBits.W)) 422 val sqDeq = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 423 val lqDeq = Input(UInt(log2Up(CommitWidth + 1).W)) 424 425 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 426 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 427 428 val otherFastWakeup = Flipped(Vec(params.LduCnt + 2 * params.StaCnt, ValidIO(new DynInst))) 429 val stIssuePtr = Input(new SqPtr()) 430 431 val csrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 432 433 // Output 434 val redirect = ValidIO(new Redirect) // rob flush MemBlock 435 val issueUops = MixedVec(Seq.fill(params.LduCnt + params.StaCnt * 2)(DecoupledIO(new MemExuInput())) ++ Seq.fill(params.VlduCnt)(DecoupledIO(new MemExuInput(true)))) 436 val loadFastMatch = Vec(params.LduCnt, Output(UInt(params.LduCnt.W))) 437 val loadFastImm = Vec(params.LduCnt, Output(UInt(12.W))) // Imm_I 438 439 val tlbCsr = Output(new TlbCsrBundle) 440 val csrCtrl = Output(new CustomCSRCtrlIO) 441 val sfence = Output(new SfenceBundle) 442 val isStoreException = Output(Bool()) 443} 444 445class BackendIO(implicit p: Parameters, params: BackendParams) extends XSBundle { 446 val fromTop = new Bundle { 447 val hartId = Input(UInt(8.W)) 448 val externalInterrupt = new ExternalInterruptIO 449 } 450 451 val toTop = new Bundle { 452 val cpuHalted = Output(Bool()) 453 } 454 455 val fenceio = new FenceIO 456 // Todo: merge these bundles into BackendFrontendIO 457 val frontend = Flipped(new FrontendToCtrlIO) 458 val frontendSfence = Output(new SfenceBundle) 459 val frontendCsrCtrl = Output(new CustomCSRCtrlIO) 460 val frontendTlbCsr = Output(new TlbCsrBundle) 461 // distributed csr write 462 val frontendCsrDistributedUpdate = Flipped(new DistributedCSRUpdateReq) 463 464 val mem = new BackendMemIO 465 466 val perf = Input(new PerfCounterIO) 467 468 val tlb = Output(new TlbCsrBundle) 469 470 val csrCustomCtrl = Output(new CustomCSRCtrlIO) 471} 472