1package xiangshan.backend.exu 2 3import chipsalliance.rocketchip.config.Parameters 4import chisel3._ 5import chisel3.util._ 6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp} 7import utility.DelayN 8import utils._ 9import xiangshan.backend.fu.{CSRFileIO, FenceIO, FuncUnitInput} 10import xiangshan.backend.Bundles.{ExuInput, ExuOutput, MemExuInput, MemExuOutput} 11import xiangshan.{Redirect, XSBundle, XSModule} 12 13class ExeUnitIO(params: ExeUnitParams)(implicit p: Parameters) extends XSBundle { 14 val flush = Flipped(ValidIO(new Redirect())) 15 val in = Flipped(DecoupledIO(new ExuInput(params))) 16 val out = DecoupledIO(new ExuOutput(params)) 17 val csrio = if (params.hasCSR) Some(new CSRFileIO) else None 18 val fenceio = if (params.hasFence) Some(new FenceIO) else None 19 val frm = if (params.needSrcFrm) Some(Input(UInt(3.W))) else None 20} 21 22class ExeUnit(exuParams: ExeUnitParams)(implicit p: Parameters) extends LazyModule { 23 lazy val module = new ExeUnitImp(this)(p, exuParams) 24} 25 26class ExeUnitImp( 27 override val wrapper: ExeUnit 28)(implicit 29 p: Parameters, exuParams: ExeUnitParams 30) extends LazyModuleImp(wrapper) { 31 private val fuCfgs = exuParams.fuConfigs 32 33 val io = IO(new ExeUnitIO(exuParams)) 34 35 val funcUnits = fuCfgs.map(cfg => { 36 assert(cfg.fuGen != null, cfg.name + "Cfg'fuGen is null !!!") 37 val module = cfg.fuGen(p, cfg) 38 module 39 }) 40 41 val busy = RegInit(false.B) 42 val robIdx = RegEnable(io.in.bits.robIdx, io.in.fire) 43 when (io.in.fire && io.in.bits.robIdx.needFlush(io.flush)) { 44 busy := false.B 45 }.elsewhen(busy && robIdx.needFlush(io.flush)){ 46 busy := false.B 47 }.elsewhen(io.out.fire) { 48 busy := false.B 49 }.elsewhen(io.in.fire) { 50 busy := true.B 51 } 52 if(exuParams.latencyValMax.nonEmpty){ 53 busy := false.B 54 } 55 56 // rob flush --> funcUnits 57 funcUnits.zipWithIndex.foreach { case (fu, i) => 58 fu.io.flush <> io.flush 59 } 60 61 def acceptCond(input: ExuInput): Seq[Bool] = { 62 input.params.fuConfigs.map(_.fuSel(input)) 63 } 64 65 val in1ToN = Module(new Dispatcher(new ExuInput(exuParams), funcUnits.length, acceptCond)) 66 67 // ExeUnit.in <---> Dispatcher.in 68 in1ToN.io.in.valid := io.in.fire() 69 in1ToN.io.in.bits := io.in.bits 70 io.in.ready := !busy 71 72 // Dispatcher.out <---> FunctionUnits 73 in1ToN.io.out.zip(funcUnits.map(_.io.in)).foreach { 74 case (source: DecoupledIO[ExuInput], sink: DecoupledIO[FuncUnitInput]) => 75 sink.valid := source.valid 76 source.ready := sink.ready 77 78 sink.bits.src.zip(source.bits.src).foreach { case(fuSrc, exuSrc) => fuSrc := exuSrc } 79 sink.bits.fuOpType := source.bits.fuOpType 80 sink.bits.imm := source.bits.imm 81 sink.bits.robIdx := source.bits.robIdx 82 sink.bits.pdest := source.bits.pdest 83 sink.bits.rfWen .foreach(x => x := source.bits.rfWen.get) 84 sink.bits.fpWen .foreach(x => x := source.bits.fpWen.get) 85 sink.bits.vecWen .foreach(x => x := source.bits.vecWen.get) 86 sink.bits.fpu .foreach(x => x := source.bits.fpu.get) 87 sink.bits.flushPipe .foreach(x => x := source.bits.flushPipe.get) 88 sink.bits.pc .foreach(x => x := source.bits.pc.get) 89 sink.bits.preDecode .foreach(x => x := source.bits.preDecode.get) 90 sink.bits.ftqIdx .foreach(x => x := source.bits.ftqIdx.get) 91 sink.bits.ftqOffset .foreach(x => x := source.bits.ftqOffset.get) 92 sink.bits.predictInfo .foreach(x => x := source.bits.predictInfo.get) 93 } 94 95 private val fuOutValidOH = funcUnits.map(_.io.out.valid) 96 XSError(PopCount(fuOutValidOH) > 1.U, p"fuOutValidOH ${Binary(VecInit(fuOutValidOH).asUInt)} should be one-hot)\n") 97 private val fuOutBitsVec = funcUnits.map(_.io.out.bits) 98 private val fuRedirectVec: Seq[Option[ValidIO[Redirect]]] = funcUnits.map(_.io.out.bits.redirect) 99 100 // Assume that one fu can only write int or fp or vec, 101 // otherwise, wenVec should be assigned to wen in fu. 102 private val fuIntWenVec = funcUnits.map(_.cfg.writeIntRf.B) 103 private val fuFpWenVec = funcUnits.map(_.cfg.writeFpRf.B) 104 private val fuVecWenVec = funcUnits.map(_.cfg.writeVecRf.B) 105 // FunctionUnits <---> ExeUnit.out 106 io.out.valid := Cat(fuOutValidOH).orR 107 funcUnits.foreach(fu => fu.io.out.ready := io.out.ready) 108 109 // select one fu's result 110 io.out.bits.data := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.data)) 111 io.out.bits.robIdx := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.robIdx)) 112 io.out.bits.pdest := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.pdest)) 113 io.out.bits.intWen.foreach(x => x := Mux1H(fuOutValidOH, fuIntWenVec)) 114 io.out.bits.fpWen.foreach(x => x := Mux1H(fuOutValidOH, fuFpWenVec)) 115 io.out.bits.vecWen.foreach(x => x := Mux1H(fuOutValidOH, fuVecWenVec)) 116 io.out.bits.redirect.foreach(x => x := Mux1H((fuOutValidOH zip fuRedirectVec).filter(_._2.isDefined).map(x => (x._1, x._2.get)))) 117 io.out.bits.fflags.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.fflags.getOrElse(0.U.asTypeOf(io.out.bits.fflags.get))))) 118 io.out.bits.exceptionVec.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.exceptionVec.getOrElse(0.U.asTypeOf(io.out.bits.exceptionVec.get))))) 119 io.out.bits.flushPipe.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.flushPipe.getOrElse(0.U.asTypeOf(io.out.bits.flushPipe.get))))) 120 io.out.bits.replay.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.replay.getOrElse(0.U.asTypeOf(io.out.bits.replay.get))))) 121 io.out.bits.predecodeInfo.foreach(x => x := Mux1H(fuOutValidOH, fuOutBitsVec.map(_.preDecode.getOrElse(0.U.asTypeOf(io.out.bits.predecodeInfo.get))))) 122 123 io.csrio.foreach(exuio => funcUnits.foreach(fu => fu.io.csrio.foreach{ 124 fuio => 125 exuio <> fuio 126 fuio.exception := DelayN(exuio.exception, 2) 127 })) 128 io.fenceio.foreach(exuio => funcUnits.foreach(fu => fu.io.fenceio.foreach(fuio => fuio <> exuio))) 129 io.frm.foreach(exuio => funcUnits.foreach(fu => fu.io.frm.foreach(fuio => fuio <> exuio))) 130 131 // debug info 132 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 133 io.out.bits.debugInfo := 0.U.asTypeOf(io.out.bits.debugInfo) 134} 135 136class DispatcherIO[T <: Data](private val gen: T, n: Int) extends Bundle { 137 val in = Flipped(DecoupledIO(gen)) 138 139 val out = Vec(n, DecoupledIO(gen)) 140} 141 142class Dispatcher[T <: Data](private val gen: T, n: Int, acceptCond: T => Seq[Bool]) 143 (implicit p: Parameters) 144 extends Module { 145 146 val io = IO(new DispatcherIO(gen, n)) 147 148 private val acceptVec: Vec[Bool] = VecInit(acceptCond(io.in.bits)) 149 150 XSError(io.in.valid && PopCount(acceptVec) > 1.U, s"s[ExeUnit] accept vec should no more than 1, ${Binary(acceptVec.asUInt)} ") 151 XSError(io.in.valid && PopCount(acceptVec) === 0.U, "[ExeUnit] there is a inst not dispatched to any fu") 152 153 io.out.zipWithIndex.foreach { case (out, i) => 154 out.valid := acceptVec(i) && io.in.valid && out.ready 155 out.bits := io.in.bits 156 } 157 158 io.in.ready := Cat(io.out.map(_.ready)).orR 159} 160 161class MemExeUnitIO (implicit p: Parameters) extends XSBundle { 162 val flush = Flipped(ValidIO(new Redirect())) 163 val in = Flipped(DecoupledIO(new MemExuInput())) 164 val out = DecoupledIO(new MemExuOutput()) 165} 166 167class MemExeUnit(exuParams: ExeUnitParams)(implicit p: Parameters) extends XSModule { 168 val io = IO(new MemExeUnitIO) 169 val fu = exuParams.fuConfigs.head.fuGen(p, exuParams.fuConfigs.head) 170 fu.io.flush := io.flush 171 fu.io.in.valid := io.in.valid 172 io.in.ready := fu.io.in.ready 173 174 fu.io.in.bits.robIdx := io.in.bits.uop.robIdx 175 fu.io.in.bits.pdest := io.in.bits.uop.pdest 176 fu.io.in.bits.fuOpType := io.in.bits.uop.fuOpType 177 fu.io.in.bits.imm := io.in.bits.uop.imm 178 fu.io.in.bits.src.zip(io.in.bits.src).foreach(x => x._1 := x._2) 179 180 io.out.valid := fu.io.out.valid 181 fu.io.out.ready := io.out.ready 182 183 io.out.bits := 0.U.asTypeOf(io.out.bits) // dontCare other fields 184 io.out.bits.data := fu.io.out.bits.data 185 io.out.bits.uop.robIdx := fu.io.out.bits.robIdx 186 io.out.bits.uop.pdest := fu.io.out.bits.pdest 187 io.out.bits.uop.fuType := io.in.bits.uop.fuType 188 io.out.bits.uop.fuOpType:= io.in.bits.uop.fuOpType 189 io.out.bits.uop.sqIdx := io.in.bits.uop.sqIdx 190 191 io.out.bits.debug := 0.U.asTypeOf(io.out.bits.debug) 192} 193