xref: /XiangShan/src/main/scala/xiangshan/XSTile.scala (revision d2b20d1a96e238e36a849bd253f65ec7b6a5db38) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan
18
19import chisel3._
20import chipsalliance.rocketchip.config.{Config, Parameters}
21import chisel3.util.{Valid, ValidIO}
22import freechips.rocketchip.diplomacy._
23import freechips.rocketchip.interrupts._
24import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors}
25import freechips.rocketchip.tilelink._
26import huancun.debug.TLLogger
27import coupledL2.{L2ParamKey, CoupledL2}
28import system.HasSoCParameter
29import top.BusPerfMonitor
30import utility.{DelayN, ResetGen, TLClientsMerger, TLEdgeBuffer}
31
32class L1BusErrorUnitInfo(implicit val p: Parameters) extends Bundle with HasSoCParameter {
33  val ecc_error = Valid(UInt(soc.PAddrBits.W))
34}
35
36class XSL1BusErrors()(implicit val p: Parameters) extends BusErrors {
37  val icache = new L1BusErrorUnitInfo
38  val dcache = new L1BusErrorUnitInfo
39  val l2 = new L1BusErrorUnitInfo
40
41  override def toErrorList: List[Option[(ValidIO[UInt], String, String)]] =
42    List(
43      Some(icache.ecc_error, "I_ECC", "Icache ecc error"),
44      Some(dcache.ecc_error, "D_ECC", "Dcache ecc error"),
45      Some(l2.ecc_error, "L2_ECC", "L2Cache ecc error")
46    )
47}
48
49/**
50  *   XSTileMisc contains every module except Core and L2 Cache
51  */
52class XSTileMisc()(implicit p: Parameters) extends LazyModule
53  with HasXSParameter
54  with HasSoCParameter
55{
56  val l1_xbar = TLXbar()
57  val mmio_xbar = TLXbar()
58  val mmio_port = TLIdentityNode() // to L3
59  val memory_port = TLIdentityNode()
60  val beu = LazyModule(new BusErrorUnit(
61    new XSL1BusErrors(), BusErrorUnitParams(0x38010000)
62  ))
63  val misc_l2_pmu = BusPerfMonitor(name = "Misc_L2", enable = !debugOpts.FPGAPlatform)
64  val l2_l3_pmu = BusPerfMonitor(name = "L2_L3", enable = !debugOpts.FPGAPlatform, stat_latency = true)
65  val l1d_logger = TLLogger(s"L2_L1D_${coreParams.HartId}", !debugOpts.FPGAPlatform)
66  val l2_binder = coreParams.L2CacheParamsOpt.map(_ => BankBinder(coreParams.L2NBanks, 64))
67
68  val i_mmio_port = TLTempNode()
69  val d_mmio_port = TLTempNode()
70
71  misc_l2_pmu := l1d_logger
72  l1_xbar :=* misc_l2_pmu
73
74  l2_binder match {
75    case Some(binder) =>
76      memory_port := TLBuffer.chainNode(2) := l2_l3_pmu := TLClientsMerger() := TLXbar() :=* binder
77    case None =>
78      memory_port := l1_xbar
79  }
80
81  mmio_xbar := TLBuffer.chainNode(2) := i_mmio_port
82  mmio_xbar := TLBuffer.chainNode(2) := d_mmio_port
83  beu.node := TLBuffer.chainNode(1) := mmio_xbar
84  mmio_port := TLBuffer() := mmio_xbar
85
86  lazy val module = new LazyModuleImp(this){
87    val beu_errors = IO(Input(chiselTypeOf(beu.module.io.errors)))
88    beu.module.io.errors <> beu_errors
89  }
90}
91
92class XSTile()(implicit p: Parameters) extends LazyModule
93  with HasXSParameter
94  with HasSoCParameter
95{
96  private val core = LazyModule(new XSCore())
97  private val misc = LazyModule(new XSTileMisc())
98  private val l2cache = coreParams.L2CacheParamsOpt.map(l2param =>
99    LazyModule(new CoupledL2()(new Config((_, _, _) => {
100      case L2ParamKey => l2param.copy(hartIds = Seq(p(XSCoreParamsKey).HartId))
101    })))
102  )
103
104  // public ports
105  val memory_port = misc.memory_port
106  val uncache = misc.mmio_port
107  val clint_int_sink = core.clint_int_sink
108  val plic_int_sink = core.plic_int_sink
109  val debug_int_sink = core.debug_int_sink
110  val beu_int_source = misc.beu.intNode
111  val core_reset_sink = BundleBridgeSink(Some(() => Reset()))
112  val l1d_l2_pmu = BusPerfMonitor(name = "L1d_L2", enable = !debugOpts.FPGAPlatform, stat_latency = true)
113
114  val l1d_to_l2_bufferOpt = coreParams.dcacheParametersOpt.map { _ =>
115    val buffer = LazyModule(new TLBuffer)
116    misc.l1d_logger := buffer.node := l1d_l2_pmu := core.memBlock.dcache.clientNode
117    buffer
118  }
119
120  def chainBuffer(depth: Int, n: String): (Seq[LazyModule], TLNode) = {
121    val buffers = Seq.fill(depth){ LazyModule(new TLBuffer()) }
122    buffers.zipWithIndex.foreach{ case (b, i) => {
123      b.suggestName(s"${n}_${i}")
124    }}
125    val node = buffers.map(_.node.asInstanceOf[TLNode]).reduce(_ :*=* _)
126    (buffers, node)
127  }
128
129  misc.misc_l2_pmu := TLLogger(s"L2_L1I_${coreParams.HartId}", !debugOpts.FPGAPlatform) := core.frontend.icache.clientNode
130  if (!coreParams.softPTW) {
131    misc.misc_l2_pmu := TLLogger(s"L2_PTW_${coreParams.HartId}", !debugOpts.FPGAPlatform) := core.ptw_to_l2_buffer.node
132  }
133
134  l2cache match {
135    case Some(l2) =>
136      misc.l2_binder.get :*= l2.node :*= misc.l1_xbar
137      l2.pf_recv_node.map(recv => {
138        println("Connecting L1 prefetcher to L2!")
139        recv := core.memBlock.pf_sender_opt.get
140      })
141    case None =>
142      val dummyMatch = WireDefault(false.B)
143      ExcitingUtils.addSource(dummyMatch, s"L2MissMatch_${p(XSCoreParamsKey).HartId}", ExcitingUtils.Perf, true)
144  }
145
146  misc.i_mmio_port := core.frontend.instrUncache.clientNode
147  misc.d_mmio_port := core.memBlock.uncache.clientNode
148
149  lazy val module = new LazyModuleImp(this){
150    val io = IO(new Bundle {
151      val hartId = Input(UInt(64.W))
152      val reset_vector = Input(UInt(PAddrBits.W))
153      val cpu_halt = Output(Bool())
154    })
155
156    dontTouch(io.hartId)
157
158    val core_soft_rst = core_reset_sink.in.head._1
159
160    core.module.io.hartId := io.hartId
161    core.module.io.reset_vector := DelayN(io.reset_vector, 5)
162    io.cpu_halt := core.module.io.cpu_halt
163    if (l2cache.isDefined) {
164      // TODO: add perfEvents of L2
165      // core.module.io.perfEvents.zip(l2cache.get.module.io.perfEvents.flatten).foreach(x => x._1.value := x._2)
166    }
167    else {
168      core.module.io.perfEvents <> DontCare
169    }
170
171    misc.module.beu_errors.icache <> core.module.io.beu_errors.icache
172    misc.module.beu_errors.dcache <> core.module.io.beu_errors.dcache
173    if (l2cache.isDefined) {
174      // TODO: add ECC interface of L2
175      // misc.module.beu_errors.l2.ecc_error.valid := l2cache.get.module.io.ecc_error.valid
176      // misc.module.beu_errors.l2.ecc_error.bits := l2cache.get.module.io.ecc_error.bits
177      misc.module.beu_errors.l2 <> 0.U.asTypeOf(misc.module.beu_errors.l2)
178      core.module.io.l2Hint.bits.sourceId := l2cache.get.module.io.l2_hint.bits
179      core.module.io.l2Hint.valid := l2cache.get.module.io.l2_hint.valid
180    } else {
181      misc.module.beu_errors.l2 <> 0.U.asTypeOf(misc.module.beu_errors.l2)
182      core.module.io.l2Hint.bits.sourceId := DontCare
183      core.module.io.l2Hint.valid := false.B
184    }
185
186    // Modules are reset one by one
187    // io_reset ----
188    //             |
189    //             v
190    // reset ----> OR_SYNC --> {Misc, L2 Cache, Cores}
191    val resetChain = Seq(
192      Seq(misc.module, core.module) ++
193        l1d_to_l2_bufferOpt.map(_.module) ++
194        l2cache.map(_.module)
195    )
196    ResetGen(resetChain, reset, !debugOpts.FPGAPlatform)
197  }
198}
199