1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import huancun._ 23import system.SoCParamsKey 24import xiangshan.backend.datapath.RdConfig._ 25import xiangshan.backend.datapath.WbConfig._ 26import xiangshan.backend.dispatch.DispatchParameters 27import xiangshan.backend.exu.ExeUnitParams 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.issue.{IntScheduler, IssueBlockParams, MemScheduler, SchdBlockParams, SchedulerType, VfScheduler} 30import xiangshan.backend.regfile.{IntPregParams, PregParams, VfPregParams} 31import xiangshan.backend.BackendParams 32import xiangshan.cache.DCacheParameters 33import xiangshan.cache.prefetch._ 34import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 35import xiangshan.frontend.icache.ICacheParameters 36import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 37import xiangshan.frontend._ 38import xiangshan.frontend.icache.ICacheParameters 39 40import freechips.rocketchip.diplomacy.AddressSet 41import system.SoCParamsKey 42import huancun._ 43import huancun.debug._ 44import coupledL2._ 45import xiangshan.backend.datapath.WakeUpConfig 46import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 47 48import scala.math.min 49 50case object XSTileKey extends Field[Seq[XSCoreParameters]] 51 52case object XSCoreParamsKey extends Field[XSCoreParameters] 53 54case class XSCoreParameters 55( 56 HasPrefetch: Boolean = false, 57 HartId: Int = 0, 58 XLEN: Int = 64, 59 VLEN: Int = 128, 60 ELEN: Int = 64, 61 HasMExtension: Boolean = true, 62 HasCExtension: Boolean = true, 63 HasDiv: Boolean = true, 64 HasICache: Boolean = true, 65 HasDCache: Boolean = true, 66 AddrBits: Int = 64, 67 VAddrBits: Int = 39, 68 HasFPU: Boolean = true, 69 HasVPU: Boolean = true, 70 HasCustomCSRCacheOp: Boolean = true, 71 FetchWidth: Int = 8, 72 AsidLength: Int = 16, 73 EnableBPU: Boolean = true, 74 EnableBPD: Boolean = true, 75 EnableRAS: Boolean = true, 76 EnableLB: Boolean = false, 77 EnableLoop: Boolean = true, 78 EnableSC: Boolean = true, 79 EnbaleTlbDebug: Boolean = false, 80 EnableJal: Boolean = false, 81 EnableFauFTB: Boolean = true, 82 UbtbGHRLength: Int = 4, 83 // HistoryLength: Int = 512, 84 EnableGHistDiff: Boolean = true, 85 EnableCommitGHistDiff: Boolean = true, 86 UbtbSize: Int = 256, 87 FtbSize: Int = 2048, 88 RasSize: Int = 32, 89 CacheLineSize: Int = 512, 90 FtbWays: Int = 4, 91 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 92 // Sets Hist Tag 93 // Seq(( 2048, 2, 8), 94 // ( 2048, 9, 8), 95 // ( 2048, 13, 8), 96 // ( 2048, 20, 8), 97 // ( 2048, 26, 8), 98 // ( 2048, 44, 8), 99 // ( 2048, 73, 8), 100 // ( 2048, 256, 8)), 101 Seq(( 4096, 8, 8), 102 ( 4096, 13, 8), 103 ( 4096, 32, 8), 104 ( 4096, 119, 8)), 105 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 106 // Sets Hist Tag 107 Seq(( 256, 4, 9), 108 ( 256, 8, 9), 109 ( 512, 13, 9), 110 ( 512, 16, 9), 111 ( 512, 32, 9)), 112 SCNRows: Int = 512, 113 SCNTables: Int = 4, 114 SCCtrBits: Int = 6, 115 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 116 numBr: Int = 2, 117 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 118 ((resp_in: BranchPredictionResp, p: Parameters) => { 119 val ftb = Module(new FTB()(p)) 120 val ubtb =Module(new FauFTB()(p)) 121 // val bim = Module(new BIM()(p)) 122 val tage = Module(new Tage_SC()(p)) 123 val ras = Module(new RAS()(p)) 124 val ittage = Module(new ITTage()(p)) 125 val preds = Seq(ubtb, tage, ftb, ittage, ras) 126 preds.map(_.io := DontCare) 127 128 // ubtb.io.resp_in(0) := resp_in 129 // bim.io.resp_in(0) := ubtb.io.resp 130 // btb.io.resp_in(0) := bim.io.resp 131 // tage.io.resp_in(0) := btb.io.resp 132 // loop.io.resp_in(0) := tage.io.resp 133 ubtb.io.in.bits.resp_in(0) := resp_in 134 tage.io.in.bits.resp_in(0) := ubtb.io.out 135 ftb.io.in.bits.resp_in(0) := tage.io.out 136 ittage.io.in.bits.resp_in(0) := ftb.io.out 137 ras.io.in.bits.resp_in(0) := ittage.io.out 138 139 (preds, ras.io.out) 140 }), 141 IBufSize: Int = 48, 142 DecodeWidth: Int = 6, 143 RenameWidth: Int = 6, 144 CommitWidth: Int = 6, 145 MaxUopSize: Int = 65, 146 FtqSize: Int = 64, 147 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 148 IntLogicRegs: Int = 32, 149 FpLogicRegs: Int = 33, 150 VecLogicRegs: Int = 32 + 1 + 15, // 15: tmp, 1: vconfig 151 VCONFIG_IDX: Int = 32, 152 NRPhyRegs: Int = 192, 153 VirtualLoadQueueSize: Int = 80, 154 LoadQueueRARSize: Int = 80, 155 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 156 RollbackGroupSize: Int = 8, 157 LoadQueueReplaySize: Int = 80, 158 LoadUncacheBufferSize: Int = 20, 159 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 160 StoreQueueSize: Int = 64, 161 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 162 StoreQueueForwardWithMask: Boolean = true, 163 VlsQueueSize: Int = 8, 164 RobSize: Int = 256, 165 RabSize: Int = 256, 166 dpParams: DispatchParameters = DispatchParameters( 167 IntDqSize = 16, 168 FpDqSize = 16, 169 LsDqSize = 16, 170 IntDqDeqWidth = 6, 171 FpDqDeqWidth = 6, 172 LsDqDeqWidth = 6, 173 ), 174 intPreg: PregParams = IntPregParams( 175 numEntries = 192, 176 numRead = None, 177 numWrite = None, 178 ), 179 vfPreg: VfPregParams = VfPregParams( 180 numEntries = 192, 181 numRead = None, 182 numWrite = None, 183 ), 184 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 185 LoadPipelineWidth: Int = 2, 186 StorePipelineWidth: Int = 2, 187 VecMemSrcInWidth: Int = 2, 188 VecMemInstWbWidth: Int = 1, 189 VecMemDispatchWidth: Int = 1, 190 StoreBufferSize: Int = 16, 191 StoreBufferThreshold: Int = 7, 192 EnsbufferWidth: Int = 2, 193 UncacheBufferSize: Int = 4, 194 EnableLoadToLoadForward: Boolean = true, 195 EnableFastForward: Boolean = false, 196 EnableLdVioCheckAfterReset: Boolean = true, 197 EnableSoftPrefetchAfterReset: Boolean = true, 198 EnableCacheErrorAfterReset: Boolean = true, 199 EnableDCacheWPU: Boolean = false, 200 EnableAccurateLoadError: Boolean = true, 201 EnableUncacheWriteOutstanding: Boolean = false, 202 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 203 ReSelectLen: Int = 7, // load replay queue replay select counter len 204 itlbParameters: TLBParameters = TLBParameters( 205 name = "itlb", 206 fetchi = true, 207 useDmode = false, 208 normalNWays = 32, 209 normalReplacer = Some("plru"), 210 superNWays = 4, 211 superReplacer = Some("plru") 212 ), 213 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 214 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 215 ldtlbParameters: TLBParameters = TLBParameters( 216 name = "ldtlb", 217 normalNSets = 64, 218 normalNWays = 1, 219 normalAssociative = "sa", 220 normalReplacer = Some("setplru"), 221 superNWays = 16, 222 normalAsVictim = true, 223 outReplace = false, 224 partialStaticPMP = true, 225 outsideRecvFlush = true, 226 saveLevel = true 227 ), 228 sttlbParameters: TLBParameters = TLBParameters( 229 name = "sttlb", 230 normalNSets = 64, 231 normalNWays = 1, 232 normalAssociative = "sa", 233 normalReplacer = Some("setplru"), 234 superNWays = 16, 235 normalAsVictim = true, 236 outReplace = false, 237 partialStaticPMP = true, 238 outsideRecvFlush = true, 239 saveLevel = true 240 ), 241 pftlbParameters: TLBParameters = TLBParameters( 242 name = "pftlb", 243 normalNSets = 64, 244 normalNWays = 1, 245 normalAssociative = "sa", 246 normalReplacer = Some("setplru"), 247 superNWays = 16, 248 normalAsVictim = true, 249 outReplace = false, 250 partialStaticPMP = true, 251 outsideRecvFlush = true, 252 saveLevel = true 253 ), 254 refillBothTlb: Boolean = false, 255 btlbParameters: TLBParameters = TLBParameters( 256 name = "btlb", 257 normalNSets = 1, 258 normalNWays = 64, 259 superNWays = 4, 260 ), 261 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 262 NumPerfCounters: Int = 16, 263 icacheParameters: ICacheParameters = ICacheParameters( 264 tagECC = Some("parity"), 265 dataECC = Some("parity"), 266 replacer = Some("setplru"), 267 nMissEntries = 2, 268 nProbeEntries = 2, 269 nPrefetchEntries = 12, 270 nPrefBufferEntries = 64, 271 hasPrefetch = true, 272 ), 273 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 274 tagECC = Some("secded"), 275 dataECC = Some("secded"), 276 replacer = Some("setplru"), 277 nMissEntries = 16, 278 nProbeEntries = 8, 279 nReleaseEntries = 18 280 )), 281 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 282 name = "l2", 283 ways = 8, 284 sets = 1024, // default 512KB L2 285 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 286 )), 287 L2NBanks: Int = 1, 288 usePTWRepeater: Boolean = false, 289 softTLB: Boolean = false, // dpi-c l1tlb debug only 290 softPTW: Boolean = false, // dpi-c l2tlb debug only 291 softPTWDelay: Int = 1 292){ 293 def vlWidth = log2Up(VLEN) + 1 294 295 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 296 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 297 298 val intSchdParams = { 299 implicit val schdType: SchedulerType = IntScheduler() 300 SchdBlockParams(Seq( 301 IssueBlockParams(Seq( 302 ExeUnitParams("IEX0", Seq(AluCfg), Seq(IntWB(port = 0, 0)), Seq(Seq(IntRD(0, 0)), Seq(IntRD(1, 0)))), 303 ExeUnitParams("IEX1", Seq(AluCfg), Seq(IntWB(port = 1, 0)), Seq(Seq(IntRD(2, 0)), Seq(IntRD(3, 0)))), 304 ), numEntries = 8, numEnq = 2), 305 IssueBlockParams(Seq( 306 ExeUnitParams("IEX2", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 2, 0)), Seq(Seq(IntRD(4, 0)), Seq(IntRD(5, 0)))), 307 ExeUnitParams("IEX3", Seq(AluCfg, MulCfg, BkuCfg), Seq(IntWB(port = 3, 0)), Seq(Seq(IntRD(6, 0)), Seq(IntRD(7, 0)))), 308 ), numEntries = 8, numEnq = 2), 309 IssueBlockParams(Seq( 310 ExeUnitParams("BJU0", Seq(BrhCfg, JmpCfg, CsrCfg, FenceCfg), Seq(IntWB(port = 4, 0)), Seq(Seq(IntRD(8, 0)), Seq(IntRD(9, 0)))), 311 ExeUnitParams("BJU1", Seq(BrhCfg), Seq(), Seq(Seq(IntRD(2, 1)), Seq(IntRD(3, 1)))), 312 ), numEntries = 8, numEnq = 2), 313 IssueBlockParams(Seq( 314 ExeUnitParams("IMISC0", Seq(VSetRiWiCfg, I2fCfg, VSetRiWvfCfg), Seq(IntWB(port = 4, 1), VfWB(4, 0)), Seq(Seq(IntRD(8, 1)), Seq(IntRD(9, 1)))), 315 ), numEntries = 8, numEnq = 2), 316 IssueBlockParams(Seq( 317 ExeUnitParams("IDIV0", Seq(DivCfg), Seq(IntWB(port = 5, 1)), Seq(Seq(IntRD(6, Int.MaxValue)), Seq(IntRD(7, Int.MaxValue)))), 318 ), numEntries = 8, numEnq = 2), 319 ), 320 numPregs = intPreg.numEntries, 321 numDeqOutside = 0, 322 schdType = schdType, 323 rfDataWidth = intPreg.dataCfg.dataWidth, 324 numUopIn = dpParams.IntDqDeqWidth, 325 ) 326 } 327 val vfSchdParams = { 328 implicit val schdType: SchedulerType = VfScheduler() 329 SchdBlockParams(Seq( 330 IssueBlockParams(Seq( 331 ExeUnitParams("VEX0", Seq(VialuCfg), Seq(VfWB(port = 0, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 332 ExeUnitParams("VEX1", Seq(VimacCfg), Seq(VfWB(port = 0, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 333 ), numEntries = 8, numEnq = 2), 334 IssueBlockParams(Seq( 335 ExeUnitParams("FEX0", Seq(FmacCfg), Seq(VfWB(port = 0, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)))), 336 ExeUnitParams("FEX1", Seq(FmacCfg), Seq(VfWB(port = 1, 0)), Seq(Seq(VfRD(4, 0)), Seq(VfRD(5, 0)), Seq(VfRD(6, 0)))), 337 ), numEntries = 8, numEnq = 2), 338 IssueBlockParams(Seq( 339 ExeUnitParams("FEX2", Seq(FDivSqrtCfg), Seq(VfWB(port = 2, 0)), Seq(Seq(VfRD(11, 0)), Seq(VfRD(12, 0)))), 340 ExeUnitParams("FEX3", Seq(F2fCfg, F2iCfg, VSetRvfWvfCfg), Seq(VfWB(port = 2, 0), IntWB(port = 5, 0)), Seq(Seq(VfRD(7, 0)), Seq(VfRD(8, 0)))), 341 ), numEntries = 8, numEnq = 2), 342 IssueBlockParams(Seq( 343 ExeUnitParams("VEX2", Seq(VppuCfg), Seq(VfWB(port = 3, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 344 ExeUnitParams("VEX3", Seq(VipuCfg), Seq(VfWB(port = 3, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 345 ), numEntries = 8, numEnq = 2), 346 IssueBlockParams(Seq( 347 ExeUnitParams("VEX2", Seq(VfaluCfg), Seq(VfWB(port = 4, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 348 ExeUnitParams("VEX3", Seq(VfmaCfg), Seq(VfWB(port = 4, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 349 ), numEntries = 8, numEnq = 2), 350 IssueBlockParams(Seq( 351 ExeUnitParams("VEX4", Seq(VfdivCfg), Seq(VfWB(port = 5, 0)), Seq(Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)), Seq(VfRD(5, 0)))), 352 ), numEntries = 8, numEnq = 2), 353 ), 354 numPregs = vfPreg.numEntries, 355 numDeqOutside = 0, 356 schdType = schdType, 357 rfDataWidth = vfPreg.dataCfg.dataWidth, 358 numUopIn = dpParams.FpDqDeqWidth, 359 ) 360 } 361 362 val memSchdParams = { 363 implicit val schdType: SchedulerType = MemScheduler() 364 val rfDataWidth = 64 365 366 SchdBlockParams(Seq( 367 IssueBlockParams(Seq( 368 ExeUnitParams("LDU0", Seq(LduCfg), Seq(IntWB(6, 0), VfWB(6, 0)), Seq(Seq(IntRD(10, 0)))), 369 ExeUnitParams("LDU1", Seq(LduCfg), Seq(IntWB(7, 0), VfWB(7, 0)), Seq(Seq(IntRD(11, 0)))), 370 ), numEntries = 8, numEnq = 2), 371 IssueBlockParams(Seq( 372 ExeUnitParams("STA0", Seq(StaCfg, MouCfg), Seq(IntWB(6, 1)), Seq(Seq(IntRD(12, 0)))), 373 ExeUnitParams("STA1", Seq(StaCfg, MouCfg), Seq(IntWB(7, 1)), Seq(Seq(IntRD(13, 0)))), 374 ), numEntries = 8, numEnq = 2), 375 IssueBlockParams(Seq( 376 ExeUnitParams("STD0", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(8, Int.MaxValue), VfRD(12, Int.MaxValue)))), 377 ExeUnitParams("STD1", Seq(StdCfg, MoudCfg), Seq(), Seq(Seq(IntRD(9, Int.MaxValue), VfRD(10, Int.MaxValue)))), 378 ), numEntries = 8, numEnq = 2), 379 IssueBlockParams(Seq( 380 ExeUnitParams("VLDU0", Seq(VlduCfg), Seq(VfWB(6, 1)), Seq(Seq(VfRD(0, 0)), Seq(VfRD(1, 0)), Seq(VfRD(2, 0)), Seq(VfRD(3, 0)), Seq(VfRD(4, 0)))), 381 ExeUnitParams("VLDU1", Seq(VlduCfg), Seq(VfWB(7, 1)), Seq(Seq(VfRD(5, 0)), Seq(VfRD(6, 0)), Seq(VfRD(7, 0)), Seq(VfRD(8, 0)), Seq(VfRD(9, 0)))), 382 ), numEntries = 8, numEnq = 2), 383 ), 384 numPregs = intPreg.numEntries max vfPreg.numEntries, 385 numDeqOutside = 0, 386 schdType = schdType, 387 rfDataWidth = rfDataWidth, 388 numUopIn = dpParams.LsDqDeqWidth, 389 ) 390 } 391 392 def PregIdxWidthMax = intPreg.addrWidth max vfPreg.addrWidth 393 394 def iqWakeUpParams = { 395 Seq( 396 WakeUpConfig("IEX0" -> "IEX0"), 397 WakeUpConfig("IEX0" -> "IEX1"), 398 WakeUpConfig("IEX1" -> "IEX0"), 399 WakeUpConfig("IEX1" -> "IEX1"), 400 WakeUpConfig("IEX0" -> "BJU0"), 401 WakeUpConfig("IEX0" -> "BJU1"), 402 WakeUpConfig("IEX1" -> "BJU0"), 403 WakeUpConfig("IEX1" -> "BJU1"), 404 WakeUpConfig("IEX0" -> "LDU0"), 405 WakeUpConfig("IEX0" -> "LDU1"), 406 WakeUpConfig("IEX1" -> "LDU0"), 407 WakeUpConfig("IEX1" -> "LDU1"), 408 WakeUpConfig("IEX0" -> "STA0"), 409 WakeUpConfig("IEX0" -> "STA1"), 410 WakeUpConfig("IEX1" -> "STA0"), 411 WakeUpConfig("IEX1" -> "STA1"), 412 WakeUpConfig("IMISC0" -> "FEX0"), 413 WakeUpConfig("IMISC0" -> "FEX1"), 414 WakeUpConfig("IMISC0" -> "FEX2"), 415 WakeUpConfig("IMISC0" -> "FEX3"), 416 WakeUpConfig("IMISC0" -> "FEX4"), 417 WakeUpConfig("FEX3" -> "FEX0"), 418 WakeUpConfig("FEX3" -> "FEX1"), 419 WakeUpConfig("FEX3" -> "FEX2"), 420 WakeUpConfig("FEX3" -> "FEX3"), 421 ) 422 } 423 424 def backendParams: BackendParams = backend.BackendParams( 425 Map( 426 IntScheduler() -> intSchdParams, 427 VfScheduler() -> vfSchdParams, 428 MemScheduler() -> memSchdParams, 429 ), 430 Seq( 431 intPreg, 432 vfPreg, 433 ), 434 iqWakeUpParams, 435 ) 436} 437 438case object DebugOptionsKey extends Field[DebugOptions] 439 440case class DebugOptions 441( 442 FPGAPlatform: Boolean = false, 443 EnableDifftest: Boolean = false, 444 AlwaysBasicDiff: Boolean = true, 445 EnableDebug: Boolean = false, 446 EnablePerfDebug: Boolean = true, 447 UseDRAMSim: Boolean = false, 448 EnableConstantin: Boolean = false, 449 EnableTopDown: Boolean = false 450) 451 452trait HasXSParameter { 453 454 implicit val p: Parameters 455 456 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 457 458 val coreParams = p(XSCoreParamsKey) 459 val env = p(DebugOptionsKey) 460 461 val XLEN = coreParams.XLEN 462 val VLEN = coreParams.VLEN 463 val ELEN = coreParams.ELEN 464 val minFLen = 32 465 val fLen = 64 466 def xLen = XLEN 467 468 val HasMExtension = coreParams.HasMExtension 469 val HasCExtension = coreParams.HasCExtension 470 val HasDiv = coreParams.HasDiv 471 val HasIcache = coreParams.HasICache 472 val HasDcache = coreParams.HasDCache 473 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 474 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 475 val AsidLength = coreParams.AsidLength 476 val ReSelectLen = coreParams.ReSelectLen 477 val AddrBytes = AddrBits / 8 // unused 478 val DataBits = XLEN 479 val DataBytes = DataBits / 8 480 val HasFPU = coreParams.HasFPU 481 val HasVPU = coreParams.HasVPU 482 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 483 val FetchWidth = coreParams.FetchWidth 484 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 485 val EnableBPU = coreParams.EnableBPU 486 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 487 val EnableRAS = coreParams.EnableRAS 488 val EnableLB = coreParams.EnableLB 489 val EnableLoop = coreParams.EnableLoop 490 val EnableSC = coreParams.EnableSC 491 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 492 val HistoryLength = coreParams.HistoryLength 493 val EnableGHistDiff = coreParams.EnableGHistDiff 494 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 495 val UbtbGHRLength = coreParams.UbtbGHRLength 496 val UbtbSize = coreParams.UbtbSize 497 val EnableFauFTB = coreParams.EnableFauFTB 498 val FtbSize = coreParams.FtbSize 499 val FtbWays = coreParams.FtbWays 500 val RasSize = coreParams.RasSize 501 502 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 503 coreParams.branchPredictor(resp_in, p) 504 } 505 val numBr = coreParams.numBr 506 val TageTableInfos = coreParams.TageTableInfos 507 val TageBanks = coreParams.numBr 508 val SCNRows = coreParams.SCNRows 509 val SCCtrBits = coreParams.SCCtrBits 510 val SCHistLens = coreParams.SCHistLens 511 val SCNTables = coreParams.SCNTables 512 513 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 514 case ((n, cb), h) => (n, cb, h) 515 } 516 val ITTageTableInfos = coreParams.ITTageTableInfos 517 type FoldedHistoryInfo = Tuple2[Int, Int] 518 val foldedGHistInfos = 519 (TageTableInfos.map{ case (nRows, h, t) => 520 if (h > 0) 521 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 522 else 523 Set[FoldedHistoryInfo]() 524 }.reduce(_++_).toSet ++ 525 SCTableInfos.map{ case (nRows, _, h) => 526 if (h > 0) 527 Set((h, min(log2Ceil(nRows/TageBanks), h))) 528 else 529 Set[FoldedHistoryInfo]() 530 }.reduce(_++_).toSet ++ 531 ITTageTableInfos.map{ case (nRows, h, t) => 532 if (h > 0) 533 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 534 else 535 Set[FoldedHistoryInfo]() 536 }.reduce(_++_) ++ 537 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 538 ).toList 539 540 541 542 val CacheLineSize = coreParams.CacheLineSize 543 val CacheLineHalfWord = CacheLineSize / 16 544 val ExtHistoryLength = HistoryLength + 64 545 val IBufSize = coreParams.IBufSize 546 val DecodeWidth = coreParams.DecodeWidth 547 val RenameWidth = coreParams.RenameWidth 548 val CommitWidth = coreParams.CommitWidth 549 val MaxUopSize = coreParams.MaxUopSize 550 val FtqSize = coreParams.FtqSize 551 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 552 val IntLogicRegs = coreParams.IntLogicRegs 553 val FpLogicRegs = coreParams.FpLogicRegs 554 val VecLogicRegs = coreParams.VecLogicRegs 555 val VCONFIG_IDX = coreParams.VCONFIG_IDX 556 val IntPhyRegs = coreParams.intPreg.numEntries 557 val VfPhyRegs = coreParams.vfPreg.numEntries 558 val PhyRegIdxWidth = log2Up(IntPhyRegs) max log2Up(VfPhyRegs) 559 val RobSize = coreParams.RobSize 560 val RabSize = coreParams.RabSize 561 val IntRefCounterWidth = log2Ceil(RobSize) 562 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 563 val LoadQueueRARSize = coreParams.LoadQueueRARSize 564 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 565 val RollbackGroupSize = coreParams.RollbackGroupSize 566 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 567 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 568 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 569 val StoreQueueSize = coreParams.StoreQueueSize 570 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 571 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 572 val VlsQueueSize = coreParams.VlsQueueSize 573 val dpParams = coreParams.dpParams 574 575 def backendParams: BackendParams = coreParams.backendParams 576 def MemIQSizeMax = backendParams.memSchdParams.get.issueBlockParams.map(_.numEntries).max 577 def IQSizeMax = backendParams.allSchdParams.map(_.issueBlockParams.map(_.numEntries).max).max 578 val LoadPipelineWidth = coreParams.LoadPipelineWidth 579 val StorePipelineWidth = coreParams.StorePipelineWidth 580 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 581 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 582 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 583 val StoreBufferSize = coreParams.StoreBufferSize 584 val StoreBufferThreshold = coreParams.StoreBufferThreshold 585 val EnsbufferWidth = coreParams.EnsbufferWidth 586 val UncacheBufferSize = coreParams.UncacheBufferSize 587 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 588 val EnableFastForward = coreParams.EnableFastForward 589 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 590 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 591 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 592 val EnableDCacheWPU = coreParams.EnableDCacheWPU 593 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 594 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 595 val asidLen = coreParams.MMUAsidLen 596 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 597 val refillBothTlb = coreParams.refillBothTlb 598 val itlbParams = coreParams.itlbParameters 599 val ldtlbParams = coreParams.ldtlbParameters 600 val sttlbParams = coreParams.sttlbParameters 601 val pftlbParams = coreParams.pftlbParameters 602 val btlbParams = coreParams.btlbParameters 603 val l2tlbParams = coreParams.l2tlbParameters 604 val NumPerfCounters = coreParams.NumPerfCounters 605 606 val instBytes = if (HasCExtension) 2 else 4 607 val instOffsetBits = log2Ceil(instBytes) 608 609 val icacheParameters = coreParams.icacheParameters 610 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 611 612 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 613 // for constrained LR/SC loop 614 val LRSCCycles = 64 615 // for lr storm 616 val LRSCBackOff = 8 617 618 // cache hierarchy configurations 619 val l1BusDataWidth = 256 620 621 // load violation predict 622 val ResetTimeMax2Pow = 20 //1078576 623 val ResetTimeMin2Pow = 10 //1024 624 // wait table parameters 625 val WaitTableSize = 1024 626 val MemPredPCWidth = log2Up(WaitTableSize) 627 val LWTUse2BitCounter = true 628 // store set parameters 629 val SSITSize = WaitTableSize 630 val LFSTSize = 32 631 val SSIDWidth = log2Up(LFSTSize) 632 val LFSTWidth = 4 633 val StoreSetEnable = true // LWT will be disabled if SS is enabled 634 val LFSTEnable = false 635 636 val PCntIncrStep: Int = 6 637 val numPCntHc: Int = 25 638 val numPCntPtw: Int = 19 639 640 val numCSRPCntFrontend = 8 641 val numCSRPCntCtrl = 8 642 val numCSRPCntLsu = 8 643 val numCSRPCntHc = 5 644 645 // source stages of cancel signal to issue queues 646 val cancelStages = Seq("IS", "OG0", "OG1") 647} 648