1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan._ 25import xiangshan.backend.Bundles.{DynInst, MemExuOutput} 26import xiangshan.cache._ 27import xiangshan.cache.{DCacheLineIO, DCacheWordIO, MemoryOpConstants} 28import xiangshan.cache.mmu.TlbRequestIO 29import xiangshan.mem._ 30import xiangshan.backend.rob.RobLsqIO 31 32class ExceptionAddrIO(implicit p: Parameters) extends XSBundle { 33 val isStore = Input(Bool()) 34 val vaddr = Output(UInt(VAddrBits.W)) 35} 36 37class FwdEntry extends Bundle { 38 val validFast = Bool() // validFast is generated the same cycle with query 39 val valid = Bool() // valid is generated 1 cycle after query request 40 val data = UInt(8.W) // data is generated 1 cycle after query request 41} 42 43// inflight miss block reqs 44class InflightBlockInfo(implicit p: Parameters) extends XSBundle { 45 val block_addr = UInt(PAddrBits.W) 46 val valid = Bool() 47} 48 49class LsqEnqIO(implicit p: Parameters) extends XSBundle { 50 val canAccept = Output(Bool()) 51 val needAlloc = Vec(backendParams.LsExuCnt, Input(UInt(2.W))) 52 val req = Vec(backendParams.LsExuCnt, Flipped(ValidIO(new DynInst))) 53 val resp = Vec(backendParams.LsExuCnt, Output(new LSIdx)) 54} 55 56// Load / Store Queue Wrapper for XiangShan Out of Order LSU 57class LsqWrapper(implicit p: Parameters) extends XSModule with HasDCacheParameters with HasPerfEvents { 58 val io = IO(new Bundle() { 59 val hartId = Input(UInt(8.W)) 60 val brqRedirect = Flipped(ValidIO(new Redirect)) 61 val enq = new LsqEnqIO 62 val ldu = new Bundle() { 63 val stld_nuke_query = Vec(LoadPipelineWidth, Flipped(new LoadNukeQueryIO)) // from load_s2 64 val ldld_nuke_query = Vec(LoadPipelineWidth, Flipped(new LoadNukeQueryIO)) // from load_s2 65 val ldin = Vec(LoadPipelineWidth, Flipped(Decoupled(new LqWriteBundle))) // from load_s3 66 } 67 val sta = new Bundle() { 68 val storeMaskIn = Vec(StorePipelineWidth, Flipped(Valid(new StoreMaskBundle))) // from store_s0, store mask, send to sq from rs 69 val storeAddrIn = Vec(StorePipelineWidth, Flipped(Valid(new LsPipelineBundle))) // from store_s1 70 val storeAddrInRe = Vec(StorePipelineWidth, Input(new LsPipelineBundle())) // from store_s2 71 } 72 val std = new Bundle() { 73 val storeDataIn = Vec(StorePipelineWidth, Flipped(Valid(new MemExuOutput))) // from store_s0, store data, send to sq from rs 74 } 75 val ldout = Vec(LoadPipelineWidth, DecoupledIO(new MemExuOutput)) 76 val ld_raw_data = Vec(LoadPipelineWidth, Output(new LoadDataFromLQBundle)) 77 val replay = Vec(LoadPipelineWidth, Decoupled(new LsPipelineBundle)) 78 val sbuffer = Vec(EnsbufferWidth, Decoupled(new DCacheWordReqWithVaddr)) 79 val forward = Vec(LoadPipelineWidth, Flipped(new PipeLoadForwardQueryIO)) 80 val rob = Flipped(new RobLsqIO) 81 val rollback = Output(Valid(new Redirect)) 82 val release = Flipped(Valid(new Release)) 83 val refill = Flipped(Valid(new Refill)) 84 val tl_d_channel = Input(new DcacheToLduForwardIO) 85 val uncacheOutstanding = Input(Bool()) 86 val uncache = new UncacheWordIO 87 val mmioStout = DecoupledIO(new MemExuOutput) // writeback uncached store 88 val sqEmpty = Output(Bool()) 89 val lq_rep_full = Output(Bool()) 90 val sqFull = Output(Bool()) 91 val lqFull = Output(Bool()) 92 val sqCancelCnt = Output(UInt(log2Up(StoreQueueSize+1).W)) 93 val lqCancelCnt = Output(UInt(log2Up(VirtualLoadQueueSize+1).W)) 94 val lqDeq = Output(UInt(log2Up(CommitWidth + 1).W)) 95 val sqDeq = Output(UInt(log2Ceil(EnsbufferWidth + 1).W)) 96 val lqCanAccept = Output(Bool()) 97 val sqCanAccept = Output(Bool()) 98 val exceptionAddr = new ExceptionAddrIO 99 val trigger = Vec(LoadPipelineWidth, new LqTriggerIO) 100 val issuePtrExt = Output(new SqPtr) 101 val l2_hint = Input(Valid(new L2ToL1Hint())) 102 val force_write = Output(Bool()) 103 }) 104 105 val loadQueue = Module(new LoadQueue) 106 val storeQueue = Module(new StoreQueue) 107 108 storeQueue.io.hartId := io.hartId 109 storeQueue.io.uncacheOutstanding := io.uncacheOutstanding 110 111 112 dontTouch(loadQueue.io.tlbReplayDelayCycleCtrl) 113 // Todo: imm 114 val tlbReplayDelayCycleCtrl = WireInit(VecInit(Seq(14.U(ReSelectLen.W), 0.U(ReSelectLen.W), 125.U(ReSelectLen.W), 0.U(ReSelectLen.W)))) 115 loadQueue.io.tlbReplayDelayCycleCtrl := tlbReplayDelayCycleCtrl 116 117 // io.enq logic 118 // LSQ: send out canAccept when both load queue and store queue are ready 119 // Dispatch: send instructions to LSQ only when they are ready 120 io.enq.canAccept := loadQueue.io.enq.canAccept && storeQueue.io.enq.canAccept 121 io.lqCanAccept := loadQueue.io.enq.canAccept 122 io.sqCanAccept := storeQueue.io.enq.canAccept 123 loadQueue.io.enq.sqCanAccept := storeQueue.io.enq.canAccept 124 storeQueue.io.enq.lqCanAccept := loadQueue.io.enq.canAccept 125 for (i <- io.enq.req.indices) { 126 loadQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i)(0) 127 loadQueue.io.enq.req(i).valid := io.enq.needAlloc(i)(0) && io.enq.req(i).valid 128 loadQueue.io.enq.req(i).bits := io.enq.req(i).bits 129 loadQueue.io.enq.req(i).bits.sqIdx := storeQueue.io.enq.resp(i) 130 131 storeQueue.io.enq.needAlloc(i) := io.enq.needAlloc(i)(1) 132 storeQueue.io.enq.req(i).valid := io.enq.needAlloc(i)(1) && io.enq.req(i).valid 133 storeQueue.io.enq.req(i).bits := io.enq.req(i).bits 134 storeQueue.io.enq.req(i).bits := io.enq.req(i).bits 135 storeQueue.io.enq.req(i).bits.lqIdx := loadQueue.io.enq.resp(i) 136 137 io.enq.resp(i).lqIdx := loadQueue.io.enq.resp(i) 138 io.enq.resp(i).sqIdx := storeQueue.io.enq.resp(i) 139 } 140 141 // store queue wiring 142 storeQueue.io.brqRedirect <> io.brqRedirect 143 storeQueue.io.storeAddrIn <> io.sta.storeAddrIn // from store_s1 144 storeQueue.io.storeAddrInRe <> io.sta.storeAddrInRe // from store_s2 145 storeQueue.io.storeDataIn <> io.std.storeDataIn // from store_s0 146 storeQueue.io.storeMaskIn <> io.sta.storeMaskIn // from store_s0 147 storeQueue.io.sbuffer <> io.sbuffer 148 storeQueue.io.mmioStout <> io.mmioStout 149 storeQueue.io.rob <> io.rob 150 storeQueue.io.exceptionAddr.isStore := DontCare 151 storeQueue.io.sqCancelCnt <> io.sqCancelCnt 152 storeQueue.io.sqDeq <> io.sqDeq 153 storeQueue.io.sqEmpty <> io.sqEmpty 154 storeQueue.io.sqFull <> io.sqFull 155 storeQueue.io.forward <> io.forward // overlap forwardMask & forwardData, DO NOT CHANGE SEQUENCE 156 storeQueue.io.force_write <> io.force_write 157 158 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 159 160 // load queue wiring 161 loadQueue.io.redirect <> io.brqRedirect 162 loadQueue.io.ldu <> io.ldu 163 loadQueue.io.ldout <> io.ldout 164 loadQueue.io.ld_raw_data <> io.ld_raw_data 165 loadQueue.io.rob <> io.rob 166 loadQueue.io.rollback <> io.rollback 167 loadQueue.io.replay <> io.replay 168 loadQueue.io.refill <> io.refill 169 loadQueue.io.tl_d_channel <> io.tl_d_channel 170 loadQueue.io.release <> io.release 171 loadQueue.io.trigger <> io.trigger 172 loadQueue.io.exceptionAddr.isStore := DontCare 173 loadQueue.io.lqCancelCnt <> io.lqCancelCnt 174 loadQueue.io.sq.stAddrReadySqPtr <> storeQueue.io.stAddrReadySqPtr 175 loadQueue.io.sq.stAddrReadyVec <> storeQueue.io.stAddrReadyVec 176 loadQueue.io.sq.stDataReadySqPtr <> storeQueue.io.stDataReadySqPtr 177 loadQueue.io.sq.stDataReadyVec <> storeQueue.io.stDataReadyVec 178 loadQueue.io.sq.stIssuePtr <> storeQueue.io.stIssuePtr 179 loadQueue.io.sq.sqEmpty <> storeQueue.io.sqEmpty 180 loadQueue.io.sta.storeAddrIn <> io.sta.storeAddrIn // store_s1 181 loadQueue.io.std.storeDataIn <> io.std.storeDataIn // store_s0 182 loadQueue.io.lqFull <> io.lqFull 183 loadQueue.io.lq_rep_full <> io.lq_rep_full 184 loadQueue.io.lqDeq <> io.lqDeq 185 loadQueue.io.l2_hint <> io.l2_hint 186 187 // rob commits for lsq is delayed for two cycles, which causes the delayed update for deqPtr in lq/sq 188 // s0: commit 189 // s1: exception find 190 // s2: exception triggered 191 // s3: ptr updated & new address 192 // address will be used at the next cycle after exception is triggered 193 io.exceptionAddr.vaddr := Mux(RegNext(io.exceptionAddr.isStore), storeQueue.io.exceptionAddr.vaddr, loadQueue.io.exceptionAddr.vaddr) 194 io.issuePtrExt := storeQueue.io.stAddrReadySqPtr 195 196 // naive uncache arbiter 197 val s_idle :: s_load :: s_store :: Nil = Enum(3) 198 val pendingstate = RegInit(s_idle) 199 200 switch(pendingstate){ 201 is(s_idle){ 202 when(io.uncache.req.fire() && !io.uncacheOutstanding){ 203 pendingstate := Mux(loadQueue.io.uncache.req.valid, s_load, 204 Mux(io.uncacheOutstanding, s_idle, s_store)) 205 } 206 } 207 is(s_load){ 208 when(io.uncache.resp.fire()){ 209 pendingstate := s_idle 210 } 211 } 212 is(s_store){ 213 when(io.uncache.resp.fire()){ 214 pendingstate := s_idle 215 } 216 } 217 } 218 219 loadQueue.io.uncache := DontCare 220 storeQueue.io.uncache := DontCare 221 loadQueue.io.uncache.resp.valid := false.B 222 storeQueue.io.uncache.resp.valid := false.B 223 when(loadQueue.io.uncache.req.valid){ 224 io.uncache.req <> loadQueue.io.uncache.req 225 }.otherwise{ 226 io.uncache.req <> storeQueue.io.uncache.req 227 } 228 when (io.uncacheOutstanding) { 229 io.uncache.resp <> loadQueue.io.uncache.resp 230 } .otherwise { 231 when(pendingstate === s_load){ 232 io.uncache.resp <> loadQueue.io.uncache.resp 233 }.otherwise{ 234 io.uncache.resp <> storeQueue.io.uncache.resp 235 } 236 } 237 238 239 assert(!(loadQueue.io.uncache.req.valid && storeQueue.io.uncache.req.valid)) 240 assert(!(loadQueue.io.uncache.resp.valid && storeQueue.io.uncache.resp.valid)) 241 when (!io.uncacheOutstanding) { 242 assert(!((loadQueue.io.uncache.resp.valid || storeQueue.io.uncache.resp.valid) && pendingstate === s_idle)) 243 } 244 245 246 val perfEvents = Seq(loadQueue, storeQueue).flatMap(_.getPerfEvents) 247 generatePerfEvent() 248} 249 250class LsqEnqCtrl(implicit p: Parameters) extends XSModule { 251 val io = IO(new Bundle { 252 val redirect = Flipped(ValidIO(new Redirect)) 253 // to dispatch 254 val enq = new LsqEnqIO 255 // from `memBlock.io.lqDeq 256 val lcommit = Input(UInt(log2Up(CommitWidth + 1).W)) 257 // from `memBlock.io.sqDeq` 258 val scommit = Input(UInt(log2Ceil(EnsbufferWidth + 1).W)) 259 // from/tp lsq 260 val lqCancelCnt = Input(UInt(log2Up(VirtualLoadQueueSize + 1).W)) 261 val sqCancelCnt = Input(UInt(log2Up(StoreQueueSize + 1).W)) 262 val enqLsq = Flipped(new LsqEnqIO) 263 }) 264 265 val lqPtr = RegInit(0.U.asTypeOf(new LqPtr)) 266 val sqPtr = RegInit(0.U.asTypeOf(new SqPtr)) 267 val lqCounter = RegInit(VirtualLoadQueueSize.U(log2Up(VirtualLoadQueueSize + 1).W)) 268 val sqCounter = RegInit(StoreQueueSize.U(log2Up(StoreQueueSize + 1).W)) 269 val canAccept = RegInit(false.B) 270 271 val loadEnqNumber = PopCount(io.enq.req.zip(io.enq.needAlloc).map(x => x._1.valid && x._2(0))) 272 val storeEnqNumber = PopCount(io.enq.req.zip(io.enq.needAlloc).map(x => x._1.valid && x._2(1))) 273 274 // How to update ptr and counter: 275 // (1) by default, updated according to enq/commit 276 // (2) when redirect and dispatch queue is empty, update according to lsq 277 val t1_redirect = RegNext(io.redirect.valid) 278 val t2_redirect = RegNext(t1_redirect) 279 val t2_update = t2_redirect && !VecInit(io.enq.needAlloc.map(_.orR)).asUInt.orR 280 val t3_update = RegNext(t2_update) 281 val t3_lqCancelCnt = RegNext(io.lqCancelCnt) 282 val t3_sqCancelCnt = RegNext(io.sqCancelCnt) 283 when (t3_update) { 284 lqPtr := lqPtr - t3_lqCancelCnt 285 lqCounter := lqCounter + io.lcommit + t3_lqCancelCnt 286 sqPtr := sqPtr - t3_sqCancelCnt 287 sqCounter := sqCounter + io.scommit + t3_sqCancelCnt 288 }.elsewhen (!io.redirect.valid && io.enq.canAccept) { 289 lqPtr := lqPtr + loadEnqNumber 290 lqCounter := lqCounter + io.lcommit - loadEnqNumber 291 sqPtr := sqPtr + storeEnqNumber 292 sqCounter := sqCounter + io.scommit - storeEnqNumber 293 }.otherwise { 294 lqCounter := lqCounter + io.lcommit 295 sqCounter := sqCounter + io.scommit 296 } 297 298 299 val maxAllocate = Seq(backendParams.LduCnt, backendParams.StaCnt).max 300 val ldCanAccept = lqCounter >= loadEnqNumber +& maxAllocate.U 301 val sqCanAccept = sqCounter >= storeEnqNumber +& maxAllocate.U 302 // It is possible that t3_update and enq are true at the same clock cycle. 303 // For example, if redirect.valid lasts more than one clock cycle, 304 // after the last redirect, new instructions may enter but previously redirect 305 // has not been resolved (updated according to the cancel count from LSQ). 306 // To solve the issue easily, we block enqueue when t3_update, which is RegNext(t2_update). 307 io.enq.canAccept := RegNext(ldCanAccept && sqCanAccept && !t2_update) 308 val lqOffset = Wire(Vec(io.enq.resp.length, UInt(log2Up(maxAllocate + 1).W))) 309 val sqOffset = Wire(Vec(io.enq.resp.length, UInt(log2Up(maxAllocate + 1).W))) 310 for ((resp, i) <- io.enq.resp.zipWithIndex) { 311 lqOffset(i) := PopCount(io.enq.needAlloc.take(i).map(a => a(0))) 312 resp.lqIdx := lqPtr + lqOffset(i) 313 sqOffset(i) := PopCount(io.enq.needAlloc.take(i).map(a => a(1))) 314 resp.sqIdx := sqPtr + sqOffset(i) 315 } 316 317 io.enqLsq.needAlloc := RegNext(io.enq.needAlloc) 318 io.enqLsq.req.zip(io.enq.req).zip(io.enq.resp).foreach{ case ((toLsq, enq), resp) => 319 val do_enq = enq.valid && !io.redirect.valid && io.enq.canAccept 320 toLsq.valid := RegNext(do_enq) 321 toLsq.bits := RegEnable(enq.bits, do_enq) 322 toLsq.bits.lqIdx := RegEnable(resp.lqIdx, do_enq) 323 toLsq.bits.sqIdx := RegEnable(resp.sqIdx, do_enq) 324 } 325 326}