backend, freelist: remove unused log & assertions

backend, freelist: modify free list allocatePhyReg logic
1) generate ptr and preg in a vec first
2) use renameEnable to replace common parts in allocating logic

core: add timer counters for important stages (#1045)

This commit adds timer counters for some important pipeline stages,
including rename, dispatch, dispatch2, select, issue, execute, commit.
We

core: add timer counters for important stages (#1045)

This commit adds timer counters for some important pipeline stages,
including rename, dispatch, dispatch2, select, issue, execute, commit.
We add performance counters for different types of instructions to see
the latency in different pipeline stages.

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Merge branch 'master' into me-timing

backend, freelist: opt flush process in MEFreeList
1) bug fix: updateArchRefCounter should be related with pdest, not
old_pdest
2) remove complicated logic of headPtr recovery when flushing

backend, rename: elimination psrc directly from intRat

backend, rename: optimize MEFreeList free logic

backend: support instruction fusion cases (#1011)

This commit adds some simple instruction fusion cases in decode stage.
Currently we only implement instruction pairs that can be fused into
RV64GC

backend: support instruction fusion cases (#1011)

This commit adds some simple instruction fusion cases in decode stage.
Currently we only implement instruction pairs that can be fused into
RV64GCB instructions.

Instruction fusions are detected in the decode stage by FusionDecoder.
The decoder checks every two instructions and marks the first
instruction fused if they can be fused into one instruction. The second
instruction is removed by setting the valid field to false.

Simple fusion cases include sh1add, sh2add, sh3add, sexth, zexth, etc.

Currently, ftq in frontend needs every instruction to commit. However,
the second instruction is removed from the pipeline and will not commit.
To solve this issue, we temporarily add more bits to isFused to indicate
the offset diff of the two fused instruction. There are four
possibilities now. This feature may be removed later.

This commit also adds more instruction fusion cases that need changes
in both the decode stage and the funtion units. In this commit, we add
some opcode to the function units and fuse the new instruction pairs
into these new internal uops.

The list of opcodes we add in this commit is shown below:
- szewl1: `slli r1, r0, 32` + `srli r1, r0, 31`
- szewl2: `slli r1, r0, 32` + `srli r1, r0, 30`
- byte2: `srli r1, r0, 8` + `andi r1, r1, 255`
- sh4add: `slli r1, r0, 4` + `add r1, r1, r2`
- sr30add: `srli r1, r0, 30` + `add r1, r1, r2`
- sr31add: `srli r1, r0, 31` + `add r1, r1, r2`
- sr32add: `srli r1, r0, 32` + `add r1, r1, r2`
- oddadd: `andi r1, r0, 1`` + `add r1, r1, r2`
- oddaddw: `andi r1, r0, 1`` + `addw r1, r1, r2`
- orh48: mask off the first 16 bits and or with another operand
(`andi r1, r0, -256`` + `or r1, r1, r2`)

Furthermore, this commit adds some complex instruction fusion cases to
the decode stage and function units. The complex instruction fusion cases
are detected after the instructions are decoded into uop and their
CtrlSignals are used for instruction fusion detection.

We add the following complex instruction fusion cases:
- addwbyte: addw and mask it with 0xff (extract the first byte)
- addwbit: addw and mask it with 0x1 (extract the first bit)
- logiclsb: logic operation and mask it with 0x1 (extract the first bit)
- mulw7: andi 127 and mulw instructions.
Input to mul is AND with 0x7f if mulw7 bit is set to true.

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MEFreeList: use tailPtr instead of tailPtrNext in free reg cnt

backend, rename: support elimination of move instruction whose lsrc is 0 + bug fix (#1008)

* backend, rename: support elimination of mv inst whose lsrc=0
[known bug] instr page fault not properly r

backend, rename: support elimination of move instruction whose lsrc is 0 + bug fix (#1008)

* backend, rename: support elimination of mv inst whose lsrc=0
[known bug] instr page fault not properly raised after sfence.vma

* backend, roq: [bug fix] won't label me with exception as writebacked

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Rename: fix doAllocate logic in refactored version
MEFreeList: remove useless code + give specified
(instead of DontCare) value to phy reg allocated port

Merge branch 'master' into me-opt

MEFreeList: replace "+" with "+&" in reduceTree

rename: handle mv inst with ldest=0 or ldest=lsrc
decode: slightly change def of `isMove`
[TODO] handle mv inst with lsrc=0

Merge branch 'rename-flush-bug-fix' into me-opt

l2, core: add more performance counters (#942)

* Refactor print control transform

* Adda tilelink bus pmu

* Add performance counters for dispatch, issue, execute stages

* Add more counters

l2, core: add more performance counters (#942)

* Refactor print control transform

* Adda tilelink bus pmu

* Add performance counters for dispatch, issue, execute stages

* Add more counters in bus pmu

* Insert BusPMU between L3 and L2

* add some TMA perfcnt



Co-authored-by: LinJiawei <[email protected]>
Co-authored-by: William Wang <[email protected]>
Co-authored-by: wangkaifan <[email protected]>

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AlternativeFreeList: fix flush bug with headPtrNext
(when counting duplicate reg ref, subtracting cmtCnt from archRefCnt is
needed)

rename: [refactoring] remove useless file + comment added

rename/roq/dispatch1: support EnableIntMoveElim=false
(finish refactoring) [TODO] remove useless code

rename: [refactor] move free list into 'freelist' package
"trait" was used to improve code style
parameters: use EnableIntMoveElim to control code generation
[WIP] EnableIntMoveElim=false has

rename: [refactor] move free list into 'freelist' package
"trait" was used to improve code style
parameters: use EnableIntMoveElim to control code generation
[WIP] EnableIntMoveElim=false hasn't been tested

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AlternativeFreeList: parameterize length of FL
FreeList: same as above
Parameters: add 2 core param and 2 derived param
[TODO] use EnableIntMoveElim to control ME function

backend, rename: performance bug fixed in move elimination process (#934)

* Rename: add perf counter for move elimination
[NOTE] There are three reasons why one ME is cancelled:
1. counter reach

backend, rename: performance bug fixed in move elimination process (#934)

* Rename: add perf counter for move elimination
[NOTE] There are three reasons why one ME is cancelled:
1. counter reaching max value
2. RAW dependency with former instruction
3. 2 move instruction with same psrc in 1 cycle

* Rename: add debug log + fix perf bug for move elim cancelation

* AlternativeFreeList: parameterize width of counter

* Rename:[bug fix] RAW conflict in meEnable decision
(suppose former inst=i while latter inst=j, i does
not have to be move instruction)

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backend, rename: support move elimination (#920)

* Bundle, Rename: Add some comments
FreeList, RenameTable: Comment out unused variables

* refcnt: Implement AdderTree for reference counter

*

backend, rename: support move elimination (#920)

* Bundle, Rename: Add some comments
FreeList, RenameTable: Comment out unused variables

* refcnt: Implement AdderTree for reference counter

* build.sc: add testOne method for unit test

* AdderTest: add testbench for Adder (passed)

* AdderTree: Add testbench for AdderTree (passed)

* ReferenceCounter: implement a 2-bit counter

* Rename: remove redundant code

* Rename: prepared for move elimination [WIP]

* Roq: add eliminated move bit in roq entry;
label elim move inst as writebacked
AlternativeFreeList: new impl for int free list
Rename: change io of free list
Dispatch1: (todo) not send move to intDq
Bundle: add eliminatedMove bit in roqCommitInfo, uop and debugio
ReferenceCounter: add debug print msg

* Dispatch1: [BUG FIX] not send move inst to IntDq

* DecodeUnit: [BUG FIX] differentiate li from mv

* Bug fix:
1. Dispatch1: should not label pdest of move as busy in busy table
2. Rename: use psrc0 to index bit vec isMax
3. AlternativeFreeList: fix maxVec calculation logic and ref counter
increment logic
Besides, more debug info and assertions were added.

* AlternativeFreeList Bug Fix:
1. add redirect input - shouldn't allocate reg when redirect is
valid
2. handle duplicate preg in roqCommits in int free list

* AlternativeFreeList: Fix value assignment race condition

* Rename: Fix value assignment race condition too

* RenameTable: refactor spec/arch table write process

* Roq: Fix debug_exuData of move(addi) instruction
(it was trash data before because move needn't enter exu)

* Rename: change intFreeList's redirect process
(by setting headPtr back) and flush process

* ME: microbench & coremark & linux-hello passed
1. DecodeUnit: treat `mv x,x` inst as non-move
2. AlternativeFreeList: handle duplicate walk req correctly
3. Roq: fix debug_exuData bug (make sure writeback that updates
debug_exuData happens before ME instruction in program order)

* AlternativeFreeList: License added
build.sc: remove unused config
Others: comments added

* package rename: remove unused modules

* Roq: Replace debug_prf with a cleaner fix method

* Disp1/AltFL/Rename: del unnecessary white spaces

* build.sc: change stack size
AlternativeFreeList: turn off assertions

* build.sc: change stack size for test

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misc: update PCL information (#899)

XiangShan is jointly released by ICT and PCL.

Add MulanPSL-2.0 License (#824)

In this commit, we add License for XiangShan project.