xref: /XiangShan/src/main/scala/xiangshan/Parameters.scala (revision 0ce36ddedde3c79088e7d9acce6c2bb6056bd901) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan
18
19import chipsalliance.rocketchip.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import xiangshan.backend.exu._
23import xiangshan.backend.fu._
24import xiangshan.backend.fu.fpu._
25import xiangshan.backend.dispatch.DispatchParameters
26import xiangshan.cache.{DCacheParameters, ICacheParameters, L1plusCacheParameters}
27import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters}
28import xiangshan.cache.mmu.{L2TLBParameters}
29import freechips.rocketchip.diplomacy.AddressSet
30
31case object XSCoreParamsKey extends Field[XSCoreParameters]
32
33case class XSCoreParameters
34(
35  HasPrefetch: Boolean = false,
36  HartId: Int = 0,
37  XLEN: Int = 64,
38  HasMExtension: Boolean = true,
39  HasCExtension: Boolean = true,
40  HasDiv: Boolean = true,
41  HasICache: Boolean = true,
42  HasDCache: Boolean = true,
43  AddrBits: Int = 64,
44  VAddrBits: Int = 39,
45  PAddrBits: Int = 40,
46  HasFPU: Boolean = true,
47  FetchWidth: Int = 8,
48  EnableBPU: Boolean = true,
49  EnableBPD: Boolean = true,
50  EnableRAS: Boolean = true,
51  EnableLB: Boolean = false,
52  EnableLoop: Boolean = true,
53  EnableSC: Boolean = true,
54  EnbaleTlbDebug: Boolean = false,
55  EnableJal: Boolean = false,
56  EnableUBTB: Boolean = true,
57  HistoryLength: Int = 64,
58  BtbSize: Int = 2048,
59  JbtacSize: Int = 1024,
60  JbtacBanks: Int = 8,
61  RasSize: Int = 16,
62  CacheLineSize: Int = 512,
63  UBtbWays: Int = 16,
64  BtbWays: Int = 2,
65
66  EnableL1plusPrefetcher: Boolean = true,
67  IBufSize: Int = 48,
68  DecodeWidth: Int = 6,
69  RenameWidth: Int = 6,
70  CommitWidth: Int = 6,
71  BrqSize: Int = 32,
72  FtqSize: Int = 48,
73  EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false
74  IssQueSize: Int = 16,
75  NRPhyRegs: Int = 160,
76  NRIntReadPorts: Int = 14,
77  NRIntWritePorts: Int = 8,
78  NRFpReadPorts: Int = 14,
79  NRFpWritePorts: Int = 8,
80  LoadQueueSize: Int = 64,
81  StoreQueueSize: Int = 48,
82  RoqSize: Int = 192,
83  EnableIntMoveElim: Boolean = true,
84  IntRefCounterWidth: Int = 2,
85  dpParams: DispatchParameters = DispatchParameters(
86    IntDqSize = 16,
87    FpDqSize = 16,
88    LsDqSize = 16,
89    IntDqDeqWidth = 4,
90    FpDqDeqWidth = 4,
91    LsDqDeqWidth = 4
92  ),
93  exuParameters: ExuParameters = ExuParameters(
94    JmpCnt = 1,
95    AluCnt = 4,
96    MulCnt = 0,
97    MduCnt = 2,
98    FmacCnt = 4,
99    FmiscCnt = 2,
100    FmiscDivSqrtCnt = 0,
101    LduCnt = 2,
102    StuCnt = 2
103  ),
104  LoadPipelineWidth: Int = 2,
105  StorePipelineWidth: Int = 2,
106  StoreBufferSize: Int = 16,
107  StoreBufferThreshold: Int = 7,
108  RefillSize: Int = 512,
109  TlbEntrySize: Int = 32,
110  TlbSPEntrySize: Int = 4,
111  l2tlbParameters: L2TLBParameters = L2TLBParameters(),
112  NumPerfCounters: Int = 16,
113  icacheParameters: ICacheParameters = ICacheParameters(
114    tagECC = Some("parity"),
115    dataECC = Some("parity"),
116    replacer = Some("setplru"),
117    nMissEntries = 2
118  ),
119  l1plusCacheParameters: L1plusCacheParameters = L1plusCacheParameters(
120    tagECC = Some("secded"),
121    dataECC = Some("secded"),
122    replacer = Some("setplru"),
123    nMissEntries = 8
124  ),
125  dcacheParameters: DCacheParameters = DCacheParameters(
126    tagECC = Some("secded"),
127    dataECC = Some("secded"),
128    replacer = Some("setplru"),
129    nMissEntries = 16,
130    nProbeEntries = 16,
131    nReleaseEntries = 16,
132    nStoreReplayEntries = 16
133  ),
134  L2Size: Int = 512 * 1024, // 512KB
135  L2NWays: Int = 8,
136  usePTWRepeater: Boolean = false,
137  useFakePTW: Boolean = false,
138  useFakeDCache: Boolean = false,
139  useFakeL1plusCache: Boolean = false,
140  useFakeL2Cache: Boolean = false
141){
142  val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg)
143  val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg)
144
145  val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++
146    Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) ++
147    Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg)
148
149  val fpExuConfigs =
150    Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++
151      Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg)
152
153  val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs
154}
155
156case object DebugOptionsKey extends Field[DebugOptions]
157
158case class DebugOptions
159(
160  FPGAPlatform: Boolean = true,
161  EnableDebug: Boolean = true,
162  EnablePerfDebug: Boolean = true,
163  UseDRAMSim: Boolean = false
164)
165
166trait HasXSParameter {
167
168  implicit val p: Parameters
169
170  val coreParams = p(XSCoreParamsKey)
171  val env = p(DebugOptionsKey)
172
173  val XLEN = coreParams.XLEN
174  val hardId = coreParams.HartId
175  val minFLen = 32
176  val fLen = 64
177  def xLen = XLEN
178
179  val HasMExtension = coreParams.HasMExtension
180  val HasCExtension = coreParams.HasCExtension
181  val HasDiv = coreParams.HasDiv
182  val HasIcache = coreParams.HasICache
183  val HasDcache = coreParams.HasDCache
184  val AddrBits = coreParams.AddrBits // AddrBits is used in some cases
185  val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits
186  val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits
187  val AddrBytes = AddrBits / 8 // unused
188  val DataBits = XLEN
189  val DataBytes = DataBits / 8
190  val HasFPU = coreParams.HasFPU
191  val FetchWidth = coreParams.FetchWidth
192  val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1)
193  val EnableBPU = coreParams.EnableBPU
194  val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3
195  val EnableRAS = coreParams.EnableRAS
196  val EnableLB = coreParams.EnableLB
197  val EnableLoop = coreParams.EnableLoop
198  val EnableSC = coreParams.EnableSC
199  val EnbaleTlbDebug = coreParams.EnbaleTlbDebug
200  val HistoryLength = coreParams.HistoryLength
201  val BtbSize = coreParams.BtbSize
202  // val BtbWays = 4
203  val BtbBanks = PredictWidth
204  // val BtbSets = BtbSize / BtbWays
205  val JbtacSize = coreParams.JbtacSize
206  val JbtacBanks = coreParams.JbtacBanks
207  val RasSize = coreParams.RasSize
208  val CacheLineSize = coreParams.CacheLineSize
209  val CacheLineHalfWord = CacheLineSize / 16
210  val ExtHistoryLength = HistoryLength + 64
211  val UBtbWays = coreParams.UBtbWays
212  val BtbWays = coreParams.BtbWays
213  val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher
214  val IBufSize = coreParams.IBufSize
215  val DecodeWidth = coreParams.DecodeWidth
216  val RenameWidth = coreParams.RenameWidth
217  val CommitWidth = coreParams.CommitWidth
218  val BrqSize = coreParams.BrqSize
219  val FtqSize = coreParams.FtqSize
220  val IssQueSize = coreParams.IssQueSize
221  val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp
222  val BrTagWidth = log2Up(BrqSize)
223  val NRPhyRegs = coreParams.NRPhyRegs
224  val PhyRegIdxWidth = log2Up(NRPhyRegs)
225  val RoqSize = coreParams.RoqSize
226  val EnableIntMoveElim = coreParams.EnableIntMoveElim
227  val IntRefCounterWidth = coreParams.IntRefCounterWidth
228  val StdFreeListSize = NRPhyRegs - 32
229  val MEFreeListSize = NRPhyRegs - { if (IntRefCounterWidth > 0 && IntRefCounterWidth < 5) (32 / Math.pow(2, IntRefCounterWidth)).toInt else 1 }
230  val LoadQueueSize = coreParams.LoadQueueSize
231  val StoreQueueSize = coreParams.StoreQueueSize
232  val dpParams = coreParams.dpParams
233  val exuParameters = coreParams.exuParameters
234  val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt
235  val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts
236  val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt
237  val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt
238  val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt
239  val LoadPipelineWidth = coreParams.LoadPipelineWidth
240  val StorePipelineWidth = coreParams.StorePipelineWidth
241  val StoreBufferSize = coreParams.StoreBufferSize
242  val StoreBufferThreshold = coreParams.StoreBufferThreshold
243  val RefillSize = coreParams.RefillSize
244  val DTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth
245  val TlbEntrySize = coreParams.TlbEntrySize
246  val TlbSPEntrySize = coreParams.TlbSPEntrySize
247  val l2tlbParams = coreParams.l2tlbParameters
248  val NumPerfCounters = coreParams.NumPerfCounters
249
250  val instBytes = if (HasCExtension) 2 else 4
251  val instOffsetBits = log2Ceil(instBytes)
252
253  val icacheParameters = coreParams.icacheParameters
254  val l1plusCacheParameters = coreParams.l1plusCacheParameters
255  val dcacheParameters = coreParams.dcacheParameters
256
257  val LRSCCycles = 100
258
259
260  // cache hierarchy configurations
261  val l1BusDataWidth = 256
262
263  val usePTWRepeater = coreParams.usePTWRepeater
264  val useFakeDCache = coreParams.useFakeDCache
265  val useFakePTW = coreParams.useFakePTW
266  val useFakeL1plusCache = coreParams.useFakeL1plusCache
267  // L2 configurations
268  val useFakeL2Cache = useFakeDCache && useFakePTW && useFakeL1plusCache || coreParams.useFakeL2Cache
269  val L1BusWidth = 256
270  val L2Size = coreParams.L2Size
271  val L2BlockSize = 64
272  val L2NWays = coreParams.L2NWays
273  val L2NSets = L2Size / L2BlockSize / L2NWays
274
275  // L3 configurations
276  val L2BusWidth = 256
277
278  // icache prefetcher
279  val l1plusPrefetcherParameters = L1plusPrefetcherParameters(
280    enable = true,
281    _type = "stream",
282    streamParams = StreamPrefetchParameters(
283      streamCnt = 2,
284      streamSize = 4,
285      ageWidth = 4,
286      blockBytes = l1plusCacheParameters.blockBytes,
287      reallocStreamOnMissInstantly = true,
288      cacheName = "icache"
289    )
290  )
291
292  // dcache prefetcher
293  val l2PrefetcherParameters = L2PrefetcherParameters(
294    enable = true,
295    _type = "bop", // "stream" or "bop"
296    streamParams = StreamPrefetchParameters(
297      streamCnt = 4,
298      streamSize = 4,
299      ageWidth = 4,
300      blockBytes = L2BlockSize,
301      reallocStreamOnMissInstantly = true,
302      cacheName = "dcache"
303    ),
304    bopParams = BOPParameters(
305      rrTableEntries = 256,
306      rrTagBits = 12,
307      scoreBits = 5,
308      roundMax = 50,
309      badScore = 1,
310      blockBytes = L2BlockSize,
311      nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large
312    ),
313  )
314
315  // load violation predict
316  val ResetTimeMax2Pow = 20 //1078576
317  val ResetTimeMin2Pow = 10 //1024
318  // wait table parameters
319  val WaitTableSize = 1024
320  val MemPredPCWidth = log2Up(WaitTableSize)
321  val LWTUse2BitCounter = true
322  // store set parameters
323  val SSITSize = WaitTableSize
324  val LFSTSize = 32
325  val SSIDWidth = log2Up(LFSTSize)
326  val LFSTWidth = 4
327  val StoreSetEnable = true // LWT will be disabled if SS is enabled
328
329  val loadExuConfigs = coreParams.loadExuConfigs
330  val storeExuConfigs = coreParams.storeExuConfigs
331
332  val intExuConfigs = coreParams.intExuConfigs
333
334  val fpExuConfigs = coreParams.fpExuConfigs
335
336  val exuConfigs = coreParams.exuConfigs
337
338}
339