1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.fu._ 24import xiangshan.backend.fu.fpu._ 25import xiangshan.backend.dispatch.DispatchParameters 26import xiangshan.cache.{DCacheParameters, ICacheParameters, L1plusCacheParameters} 27import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters} 28import freechips.rocketchip.diplomacy.AddressSet 29 30case object XSCoreParamsKey extends Field[XSCoreParameters] 31 32case class XSCoreParameters 33( 34 HasPrefetch: Boolean = false, 35 HartId: Int = 0, 36 XLEN: Int = 64, 37 HasMExtension: Boolean = true, 38 HasCExtension: Boolean = true, 39 HasDiv: Boolean = true, 40 HasICache: Boolean = true, 41 HasDCache: Boolean = true, 42 AddrBits: Int = 64, 43 VAddrBits: Int = 39, 44 PAddrBits: Int = 40, 45 HasFPU: Boolean = true, 46 FetchWidth: Int = 8, 47 EnableBPU: Boolean = true, 48 EnableBPD: Boolean = true, 49 EnableRAS: Boolean = true, 50 EnableLB: Boolean = false, 51 EnableLoop: Boolean = true, 52 EnableSC: Boolean = true, 53 EnbaleTlbDebug: Boolean = false, 54 EnableJal: Boolean = false, 55 EnableUBTB: Boolean = true, 56 HistoryLength: Int = 64, 57 BtbSize: Int = 2048, 58 JbtacSize: Int = 1024, 59 JbtacBanks: Int = 8, 60 RasSize: Int = 16, 61 CacheLineSize: Int = 512, 62 UBtbWays: Int = 16, 63 BtbWays: Int = 2, 64 65 EnableL1plusPrefetcher: Boolean = true, 66 IBufSize: Int = 48, 67 DecodeWidth: Int = 6, 68 RenameWidth: Int = 6, 69 CommitWidth: Int = 6, 70 BrqSize: Int = 32, 71 FtqSize: Int = 48, 72 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 73 IssQueSize: Int = 16, 74 NRPhyRegs: Int = 160, 75 NRIntReadPorts: Int = 14, 76 NRIntWritePorts: Int = 8, 77 NRFpReadPorts: Int = 14, 78 NRFpWritePorts: Int = 8, 79 LoadQueueSize: Int = 64, 80 StoreQueueSize: Int = 48, 81 RoqSize: Int = 192, 82 EnableIntMoveElim: Boolean = true, 83 IntRefCounterWidth: Int = 2, 84 dpParams: DispatchParameters = DispatchParameters( 85 IntDqSize = 16, 86 FpDqSize = 16, 87 LsDqSize = 16, 88 IntDqDeqWidth = 4, 89 FpDqDeqWidth = 4, 90 LsDqDeqWidth = 4 91 ), 92 exuParameters: ExuParameters = ExuParameters( 93 JmpCnt = 1, 94 AluCnt = 4, 95 MulCnt = 0, 96 MduCnt = 2, 97 FmacCnt = 4, 98 FmiscCnt = 2, 99 FmiscDivSqrtCnt = 0, 100 LduCnt = 2, 101 StuCnt = 2 102 ), 103 LoadPipelineWidth: Int = 2, 104 StorePipelineWidth: Int = 2, 105 StoreBufferSize: Int = 16, 106 StoreBufferThreshold: Int = 7, 107 RefillSize: Int = 512, 108 TlbEntrySize: Int = 32, 109 TlbSPEntrySize: Int = 4, 110 PtwL3EntrySize: Int = 4096, //(512 * 8) or 512 111 PtwSPEntrySize: Int = 16, 112 PtwL1EntrySize: Int = 16, 113 PtwL2EntrySize: Int = 256, //(256 * 8) 114 PtwMissQueueSize: Int = 8, 115 NumPerfCounters: Int = 16, 116 icacheParameters: ICacheParameters = ICacheParameters( 117 tagECC = Some("parity"), 118 dataECC = Some("parity"), 119 replacer = Some("setplru"), 120 nMissEntries = 2 121 ), 122 l1plusCacheParameters: L1plusCacheParameters = L1plusCacheParameters( 123 tagECC = Some("secded"), 124 dataECC = Some("secded"), 125 replacer = Some("setplru"), 126 nMissEntries = 8 127 ), 128 dcacheParameters: DCacheParameters = DCacheParameters( 129 tagECC = Some("secded"), 130 dataECC = Some("secded"), 131 replacer = Some("setplru"), 132 nMissEntries = 16, 133 nProbeEntries = 16, 134 nReleaseEntries = 16, 135 nStoreReplayEntries = 16 136 ), 137 L2Size: Int = 512 * 1024, // 512KB 138 L2NWays: Int = 8, 139 usePTWRepeater: Boolean = false, 140 useFakePTW: Boolean = false, 141 useFakeDCache: Boolean = false, 142 useFakeL1plusCache: Boolean = false, 143 useFakeL2Cache: Boolean = false 144){ 145 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 146 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) 147 148 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 149 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) ++ 150 Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 151 152 val fpExuConfigs = 153 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 154 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 155 156 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 157} 158 159case object DebugOptionsKey extends Field[DebugOptions] 160 161case class DebugOptions 162( 163 FPGAPlatform: Boolean = true, 164 EnableDebug: Boolean = true, 165 EnablePerfDebug: Boolean = true, 166 UseDRAMSim: Boolean = false 167) 168 169trait HasXSParameter { 170 171 implicit val p: Parameters 172 173 val coreParams = p(XSCoreParamsKey) 174 val env = p(DebugOptionsKey) 175 176 val XLEN = coreParams.XLEN 177 val hardId = coreParams.HartId 178 val minFLen = 32 179 val fLen = 64 180 def xLen = XLEN 181 182 val HasMExtension = coreParams.HasMExtension 183 val HasCExtension = coreParams.HasCExtension 184 val HasDiv = coreParams.HasDiv 185 val HasIcache = coreParams.HasICache 186 val HasDcache = coreParams.HasDCache 187 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 188 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 189 val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits 190 val AddrBytes = AddrBits / 8 // unused 191 val DataBits = XLEN 192 val DataBytes = DataBits / 8 193 val HasFPU = coreParams.HasFPU 194 val FetchWidth = coreParams.FetchWidth 195 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 196 val EnableBPU = coreParams.EnableBPU 197 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 198 val EnableRAS = coreParams.EnableRAS 199 val EnableLB = coreParams.EnableLB 200 val EnableLoop = coreParams.EnableLoop 201 val EnableSC = coreParams.EnableSC 202 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 203 val HistoryLength = coreParams.HistoryLength 204 val BtbSize = coreParams.BtbSize 205 // val BtbWays = 4 206 val BtbBanks = PredictWidth 207 // val BtbSets = BtbSize / BtbWays 208 val JbtacSize = coreParams.JbtacSize 209 val JbtacBanks = coreParams.JbtacBanks 210 val RasSize = coreParams.RasSize 211 val CacheLineSize = coreParams.CacheLineSize 212 val CacheLineHalfWord = CacheLineSize / 16 213 val ExtHistoryLength = HistoryLength + 64 214 val UBtbWays = coreParams.UBtbWays 215 val BtbWays = coreParams.BtbWays 216 val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher 217 val IBufSize = coreParams.IBufSize 218 val DecodeWidth = coreParams.DecodeWidth 219 val RenameWidth = coreParams.RenameWidth 220 val CommitWidth = coreParams.CommitWidth 221 val BrqSize = coreParams.BrqSize 222 val FtqSize = coreParams.FtqSize 223 val IssQueSize = coreParams.IssQueSize 224 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 225 val BrTagWidth = log2Up(BrqSize) 226 val NRPhyRegs = coreParams.NRPhyRegs 227 val PhyRegIdxWidth = log2Up(NRPhyRegs) 228 val RoqSize = coreParams.RoqSize 229 val EnableIntMoveElim = coreParams.EnableIntMoveElim 230 val IntRefCounterWidth = coreParams.IntRefCounterWidth 231 val StdFreeListSize = NRPhyRegs - 32 232 val MEFreeListSize = NRPhyRegs - { if (IntRefCounterWidth > 0 && IntRefCounterWidth < 5) (32 / Math.pow(2, IntRefCounterWidth)).toInt else 1 } 233 val LoadQueueSize = coreParams.LoadQueueSize 234 val StoreQueueSize = coreParams.StoreQueueSize 235 val dpParams = coreParams.dpParams 236 val exuParameters = coreParams.exuParameters 237 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 238 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 239 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 240 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 241 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 242 val LoadPipelineWidth = coreParams.LoadPipelineWidth 243 val StorePipelineWidth = coreParams.StorePipelineWidth 244 val StoreBufferSize = coreParams.StoreBufferSize 245 val StoreBufferThreshold = coreParams.StoreBufferThreshold 246 val RefillSize = coreParams.RefillSize 247 val DTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 248 val TlbEntrySize = coreParams.TlbEntrySize 249 val TlbSPEntrySize = coreParams.TlbSPEntrySize 250 val PtwL3EntrySize = coreParams.PtwL3EntrySize 251 val PtwSPEntrySize = coreParams.PtwSPEntrySize 252 val PtwL1EntrySize = coreParams.PtwL1EntrySize 253 val PtwL2EntrySize = coreParams.PtwL2EntrySize 254 val PtwMissQueueSize = coreParams.PtwMissQueueSize 255 val NumPerfCounters = coreParams.NumPerfCounters 256 257 val instBytes = if (HasCExtension) 2 else 4 258 val instOffsetBits = log2Ceil(instBytes) 259 260 val icacheParameters = coreParams.icacheParameters 261 val l1plusCacheParameters = coreParams.l1plusCacheParameters 262 val dcacheParameters = coreParams.dcacheParameters 263 264 val LRSCCycles = 100 265 266 267 // cache hierarchy configurations 268 val l1BusDataWidth = 256 269 270 val usePTWRepeater = coreParams.usePTWRepeater 271 val useFakeDCache = coreParams.useFakeDCache 272 val useFakePTW = coreParams.useFakePTW 273 val useFakeL1plusCache = coreParams.useFakeL1plusCache 274 // L2 configurations 275 val useFakeL2Cache = useFakeDCache && useFakePTW && useFakeL1plusCache || coreParams.useFakeL2Cache 276 val L1BusWidth = 256 277 val L2Size = coreParams.L2Size 278 val L2BlockSize = 64 279 val L2NWays = coreParams.L2NWays 280 val L2NSets = L2Size / L2BlockSize / L2NWays 281 282 // L3 configurations 283 val L2BusWidth = 256 284 285 // icache prefetcher 286 val l1plusPrefetcherParameters = L1plusPrefetcherParameters( 287 enable = true, 288 _type = "stream", 289 streamParams = StreamPrefetchParameters( 290 streamCnt = 2, 291 streamSize = 4, 292 ageWidth = 4, 293 blockBytes = l1plusCacheParameters.blockBytes, 294 reallocStreamOnMissInstantly = true, 295 cacheName = "icache" 296 ) 297 ) 298 299 // dcache prefetcher 300 val l2PrefetcherParameters = L2PrefetcherParameters( 301 enable = true, 302 _type = "bop", // "stream" or "bop" 303 streamParams = StreamPrefetchParameters( 304 streamCnt = 4, 305 streamSize = 4, 306 ageWidth = 4, 307 blockBytes = L2BlockSize, 308 reallocStreamOnMissInstantly = true, 309 cacheName = "dcache" 310 ), 311 bopParams = BOPParameters( 312 rrTableEntries = 256, 313 rrTagBits = 12, 314 scoreBits = 5, 315 roundMax = 50, 316 badScore = 1, 317 blockBytes = L2BlockSize, 318 nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large 319 ), 320 ) 321 322 // load violation predict 323 val ResetTimeMax2Pow = 20 //1078576 324 val ResetTimeMin2Pow = 10 //1024 325 // wait table parameters 326 val WaitTableSize = 1024 327 val MemPredPCWidth = log2Up(WaitTableSize) 328 val LWTUse2BitCounter = true 329 // store set parameters 330 val SSITSize = WaitTableSize 331 val LFSTSize = 32 332 val SSIDWidth = log2Up(LFSTSize) 333 val LFSTWidth = 4 334 val StoreSetEnable = true // LWT will be disabled if SS is enabled 335 336 val loadExuConfigs = coreParams.loadExuConfigs 337 val storeExuConfigs = coreParams.storeExuConfigs 338 339 val intExuConfigs = coreParams.intExuConfigs 340 341 val fpExuConfigs = coreParams.fpExuConfigs 342 343 val exuConfigs = coreParams.exuConfigs 344 345} 346