1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.rename 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import xiangshan._ 23import utils._ 24import xiangshan.backend.roq.RoqPtr 25import xiangshan.backend.dispatch.PreDispatchInfo 26 27class RenameBypassInfo(implicit p: Parameters) extends XSBundle { 28 val lsrc1_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 29 val lsrc2_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 30 val lsrc3_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 31 val ldest_bypass = MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W))) 32} 33 34class Rename(implicit p: Parameters) extends XSModule { 35 val io = IO(new Bundle() { 36 val redirect = Flipped(ValidIO(new Redirect)) 37 val flush = Input(Bool()) 38 val roqCommits = Flipped(new RoqCommitIO) 39 // from decode buffer 40 val in = Vec(RenameWidth, Flipped(DecoupledIO(new CfCtrl))) 41 // to dispatch1 42 val out = Vec(RenameWidth, DecoupledIO(new MicroOp)) 43 val renameBypass = Output(new RenameBypassInfo) 44 val dispatchInfo = Output(new PreDispatchInfo) 45 // for debug printing 46 val debug_int_rat = Vec(32, Output(UInt(PhyRegIdxWidth.W))) 47 val debug_fp_rat = Vec(32, Output(UInt(PhyRegIdxWidth.W))) 48 }) 49 50 // create free list and rat 51 val intFreeList = Module(if (EnableIntMoveElim) new freelist.MEFreeList else new freelist.StdFreeList) 52 val fpFreeList = Module(new freelist.StdFreeList) 53 54 val intRat = Module(new RenameTable(float = false)) 55 val fpRat = Module(new RenameTable(float = true)) 56 57 // connect flush and redirect ports for rat 58 Seq(intRat, fpRat) foreach { case rat => 59 rat.io.redirect := io.redirect.valid 60 rat.io.flush := io.flush 61 rat.io.walkWen := io.roqCommits.isWalk 62 } 63 64 // decide if given instruction needs allocating a new physical register (CfCtrl: from decode; RoqCommitInfo: from roq) 65 def needDestReg[T <: CfCtrl](fp: Boolean, x: T): Bool = { 66 {if(fp) x.ctrl.fpWen else x.ctrl.rfWen && (x.ctrl.ldest =/= 0.U)} 67 } 68 def needDestRegCommit[T <: RoqCommitInfo](fp: Boolean, x: T): Bool = { 69 {if(fp) x.fpWen else x.rfWen && (x.ldest =/= 0.U)} 70 } 71 72 // connect [flush + redirect + walk] ports for __float point__ & __integer__ free list 73 Seq((fpFreeList, true), (intFreeList, false)).foreach{ case (fl, isFp) => 74 fl.flush := io.flush 75 fl.redirect := io.redirect.valid 76 fl.walk := io.roqCommits.isWalk 77 // when isWalk, use stepBack to restore head pointer of free list 78 // (if ME enabled, stepBack of intFreeList should be useless thus optimized out) 79 fl.stepBack := PopCount(io.roqCommits.valid.zip(io.roqCommits.info).map{case (v, i) => v && needDestRegCommit(isFp, i)}) 80 // walk has higher priority than allocation and thus we don't use isWalk here 81 // only when both fp and int free list and dispatch1 has enough space can we do allocation 82 fl.doAllocate := fl.canAllocate && io.out(0).ready 83 } 84 85 // dispatch1 ready ++ float point free list ready ++ int free list ready ++ not walk 86 val canOut = io.out(0).ready && fpFreeList.canAllocate && intFreeList.canAllocate && !io.roqCommits.isWalk 87 88 89 // speculatively assign the instruction with an roqIdx 90 val validCount = PopCount(io.in.map(_.valid)) // number of instructions waiting to enter roq (from decode) 91 val roqIdxHead = RegInit(0.U.asTypeOf(new RoqPtr)) 92 val lastCycleMisprediction = RegNext(io.redirect.valid && !io.redirect.bits.flushItself()) 93 val roqIdxHeadNext = Mux(io.flush, 0.U.asTypeOf(new RoqPtr), // flush: clear roq 94 Mux(io.redirect.valid, io.redirect.bits.roqIdx, // redirect: move ptr to given roq index (flush itself) 95 Mux(lastCycleMisprediction, roqIdxHead + 1.U, // mis-predict: not flush roqIdx itself 96 Mux(canOut, roqIdxHead + validCount, // instructions successfully entered next stage: increase roqIdx 97 /* default */ roqIdxHead)))) // no instructions passed by this cycle: stick to old value 98 roqIdxHead := roqIdxHeadNext 99 100 101 /** 102 * Rename: allocate free physical register and update rename table 103 */ 104 val uops = Wire(Vec(RenameWidth, new MicroOp)) 105 uops.foreach( uop => { 106 uop.srcState(0) := DontCare 107 uop.srcState(1) := DontCare 108 uop.srcState(2) := DontCare 109 uop.roqIdx := DontCare 110 uop.diffTestDebugLrScValid := DontCare 111 uop.debugInfo := DontCare 112 uop.lqIdx := DontCare 113 uop.sqIdx := DontCare 114 }) 115 116 val needFpDest = Wire(Vec(RenameWidth, Bool())) 117 val needIntDest = Wire(Vec(RenameWidth, Bool())) 118 val hasValid = Cat(io.in.map(_.valid)).orR 119 120 val isMove = io.in.map(_.bits.ctrl.isMove) 121 val isMax = if (EnableIntMoveElim) Some(intFreeList.asInstanceOf[freelist.MEFreeList].maxVec) else None 122 val meEnable = WireInit(VecInit(Seq.fill(RenameWidth)(false.B))) 123 val psrc_cmp = Wire(MixedVec(List.tabulate(RenameWidth-1)(i => UInt((i+1).W)))) 124 125 val intSpecWen = Wire(Vec(RenameWidth, Bool())) 126 val fpSpecWen = Wire(Vec(RenameWidth, Bool())) 127 128 // uop calculation 129 for (i <- 0 until RenameWidth) { 130 uops(i).cf := io.in(i).bits.cf 131 uops(i).ctrl := io.in(i).bits.ctrl 132 133 val inValid = io.in(i).valid 134 135 // alloc a new phy reg 136 needFpDest(i) := inValid && needDestReg(fp = true, io.in(i).bits) 137 needIntDest(i) := inValid && needDestReg(fp = false, io.in(i).bits) 138 fpFreeList.allocateReq(i) := needFpDest(i) 139 intFreeList.allocateReq(i) := needIntDest(i) 140 141 // no valid instruction from decode stage || all resources (dispatch1 + both free lists) ready 142 io.in(i).ready := !hasValid || canOut 143 144 // do checkpoints when a branch inst come 145 // for(fl <- Seq(fpFreeList, intFreeList)){ 146 // fl.cpReqs(i).valid := inValid 147 // fl.cpReqs(i).bits := io.in(i).bits.brTag 148 // } 149 150 151 uops(i).roqIdx := roqIdxHead + i.U 152 153 io.out(i).valid := io.in(i).valid && intFreeList.canAllocate && fpFreeList.canAllocate && !io.roqCommits.isWalk 154 io.out(i).bits := uops(i) 155 156 157 // read rename table 158 def readRat(lsrcList: List[UInt], ldest: UInt, fp: Boolean) = { 159 val rat = if(fp) fpRat else intRat 160 val srcCnt = lsrcList.size 161 val psrcVec = Wire(Vec(srcCnt, UInt(PhyRegIdxWidth.W))) 162 val old_pdest = Wire(UInt(PhyRegIdxWidth.W)) 163 for(k <- 0 until srcCnt+1){ 164 val rportIdx = i * (srcCnt+1) + k 165 if(k != srcCnt){ 166 rat.io.readPorts(rportIdx).addr := lsrcList(k) 167 psrcVec(k) := rat.io.readPorts(rportIdx).rdata 168 } else { 169 rat.io.readPorts(rportIdx).addr := ldest 170 old_pdest := rat.io.readPorts(rportIdx).rdata 171 } 172 } 173 (psrcVec, old_pdest) 174 } 175 val lsrcList = List(uops(i).ctrl.lsrc(0), uops(i).ctrl.lsrc(1), uops(i).ctrl.lsrc(2)) 176 val ldest = uops(i).ctrl.ldest 177 val (intPhySrcVec, intOldPdest) = readRat(lsrcList.take(2), ldest, fp = false) 178 val (fpPhySrcVec, fpOldPdest) = readRat(lsrcList, ldest, fp = true) 179 uops(i).psrc(0) := Mux(uops(i).ctrl.srcType(0) === SrcType.reg, intPhySrcVec(0), fpPhySrcVec(0)) 180 uops(i).psrc(1) := Mux(uops(i).ctrl.srcType(1) === SrcType.reg, intPhySrcVec(1), fpPhySrcVec(1)) 181 uops(i).psrc(2) := fpPhySrcVec(2) 182 uops(i).old_pdest := Mux(uops(i).ctrl.rfWen, intOldPdest, fpOldPdest) 183 184 if (EnableIntMoveElim) { 185 186 if (i == 0) { 187 // calculate meEnable 188 meEnable(i) := isMove(i) && !isMax.get(uops(i).psrc(0)) 189 } else { 190 // compare psrc0 191 psrc_cmp(i-1) := Cat((0 until i).map(j => { 192 uops(i).psrc(0) === uops(j).psrc(0) && io.in(i).bits.ctrl.isMove && io.in(j).bits.ctrl.isMove 193 }) /* reverse is not necessary here */) 194 195 // calculate meEnable 196 meEnable(i) := isMove(i) && !(io.renameBypass.lsrc1_bypass(i-1).orR | psrc_cmp(i-1).orR | isMax.get(uops(i).psrc(0))) 197 } 198 uops(i).eliminatedMove := meEnable(i) 199 200 // send psrc of eliminated move instructions to free list and label them as eliminated 201 when (meEnable(i)) { 202 intFreeList.asInstanceOf[freelist.MEFreeList].psrcOfMove(i).valid := true.B 203 intFreeList.asInstanceOf[freelist.MEFreeList].psrcOfMove(i).bits := uops(i).psrc(0) 204 XSInfo(io.in(i).valid && io.out(i).valid, p"Move instruction ${Hexadecimal(io.in(i).bits.cf.pc)} eliminated successfully! psrc:${uops(i).psrc(0)}\n") 205 } .otherwise { 206 intFreeList.asInstanceOf[freelist.MEFreeList].psrcOfMove(i).valid := false.B 207 intFreeList.asInstanceOf[freelist.MEFreeList].psrcOfMove(i).bits := DontCare 208 XSInfo(io.in(i).valid && io.out(i).valid && isMove(i), p"Move instruction ${Hexadecimal(io.in(i).bits.cf.pc)} failed to be eliminated! psrc:${uops(i).psrc(0)}\n") 209 } 210 211 // update pdest 212 uops(i).pdest := Mux(meEnable(i), uops(i).psrc(0), // move eliminated 213 Mux(needIntDest(i), intFreeList.allocatePhyReg(i), // normal int inst 214 Mux(uops(i).ctrl.ldest===0.U && uops(i).ctrl.rfWen, 0.U // int inst with dst=r0 215 /* default */, fpFreeList.allocatePhyReg(i)))) // normal fp inst 216 } else { 217 uops(i).eliminatedMove := DontCare 218 psrc_cmp.foreach(_ := DontCare) 219 // update pdest 220 uops(i).pdest := Mux(needIntDest(i), intFreeList.allocatePhyReg(i), // normal int inst 221 Mux(uops(i).ctrl.ldest===0.U && uops(i).ctrl.rfWen, 0.U // int inst with dst=r0 222 /* default */, fpFreeList.allocatePhyReg(i))) // normal fp inst 223 } 224 225 // write speculative rename table 226 // we update rat later inside commit code 227 intSpecWen(i) := intFreeList.allocateReq(i) && intFreeList.canAllocate && intFreeList.doAllocate && !io.roqCommits.isWalk 228 fpSpecWen(i) := fpFreeList.allocateReq(i) && fpFreeList.canAllocate && fpFreeList.doAllocate && !io.roqCommits.isWalk 229 } 230 231 // We don't bypass the old_pdest from valid instructions with the same ldest currently in rename stage. 232 // Instead, we determine whether there're some dependencies between the valid instructions. 233 for (i <- 1 until RenameWidth) { 234 io.renameBypass.lsrc1_bypass(i-1) := Cat((0 until i).map(j => { 235 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.srcType(0) === SrcType.fp 236 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.srcType(0) === SrcType.reg 237 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc(0) 238 }).reverse) 239 io.renameBypass.lsrc2_bypass(i-1) := Cat((0 until i).map(j => { 240 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.srcType(1) === SrcType.fp 241 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.srcType(1) === SrcType.reg 242 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc(1) 243 }).reverse) 244 io.renameBypass.lsrc3_bypass(i-1) := Cat((0 until i).map(j => { 245 val fpMatch = needFpDest(j) && io.in(i).bits.ctrl.srcType(2) === SrcType.fp 246 val intMatch = needIntDest(j) && io.in(i).bits.ctrl.srcType(2) === SrcType.reg 247 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.lsrc(2) 248 }).reverse) 249 io.renameBypass.ldest_bypass(i-1) := Cat((0 until i).map(j => { 250 val fpMatch = needFpDest(j) && needFpDest(i) 251 val intMatch = needIntDest(j) && needIntDest(i) 252 (fpMatch || intMatch) && io.in(j).bits.ctrl.ldest === io.in(i).bits.ctrl.ldest 253 }).reverse) 254 } 255 256 // calculate lsq space requirement 257 val isLs = VecInit(uops.map(uop => FuType.isLoadStore(uop.ctrl.fuType))) 258 val isStore = VecInit(uops.map(uop => FuType.isStoreExu(uop.ctrl.fuType))) 259 val isAMO = VecInit(uops.map(uop => FuType.isAMO(uop.ctrl.fuType))) 260 io.dispatchInfo.lsqNeedAlloc := VecInit((0 until RenameWidth).map(i => 261 Mux(isLs(i), Mux(isStore(i) && !isAMO(i), 2.U, 1.U), 0.U))) 262 263 /** 264 * Instructions commit: update freelist and rename table 265 */ 266 for (i <- 0 until CommitWidth) { 267 // when RenameWidth <= CommitWidth, there will be more write ports than read ports, which must be initialized 268 // normally, they are initialized in 'normal write' section 269 if (i >= RenameWidth) { 270 Seq(intRat, fpRat) foreach { case rat => 271 rat.io.specWritePorts(i).wen := false.B 272 rat.io.specWritePorts(i).addr := DontCare 273 rat.io.specWritePorts(i).wdata := DontCare 274 } 275 } 276 277 Seq((intRat, false), (fpRat, true)) foreach { case (rat, fp) => 278 // is valid commit req and given instruction has destination register 279 val commitDestValid = io.roqCommits.valid(i) && needDestRegCommit(fp, io.roqCommits.info(i)) 280 XSDebug(p"isFp[${fp}]index[$i]-commitDestValid:$commitDestValid,isWalk:${io.roqCommits.isWalk}\n") 281 282 /* 283 I. RAT Update 284 */ 285 286 // walk back write - restore spec state : ldest => old_pdest 287 if (fp && i < RenameWidth) { 288 rat.io.specWritePorts(i).wen := (commitDestValid && io.roqCommits.isWalk) || fpSpecWen(i) 289 rat.io.specWritePorts(i).addr := Mux(fpSpecWen(i), uops(i).ctrl.ldest, io.roqCommits.info(i).ldest) 290 rat.io.specWritePorts(i).wdata := Mux(fpSpecWen(i), fpFreeList.allocatePhyReg(i), io.roqCommits.info(i).old_pdest) 291 } else if (!fp && i < RenameWidth) { 292 rat.io.specWritePorts(i).wen := (commitDestValid && io.roqCommits.isWalk) || intSpecWen(i) 293 rat.io.specWritePorts(i).addr := Mux(intSpecWen(i), uops(i).ctrl.ldest, io.roqCommits.info(i).ldest) 294 if (EnableIntMoveElim) { 295 rat.io.specWritePorts(i).wdata := 296 Mux(intSpecWen(i), Mux(meEnable(i), uops(i).psrc(0), intFreeList.allocatePhyReg(i)), io.roqCommits.info(i).old_pdest) 297 } else { 298 rat.io.specWritePorts(i).wdata := 299 Mux(intSpecWen(i), intFreeList.allocatePhyReg(i), io.roqCommits.info(i).old_pdest) 300 } 301 // when i >= RenameWidth, this write must happens during WALK process 302 } else if (i >= RenameWidth) { 303 rat.io.specWritePorts(i).wen := commitDestValid && io.roqCommits.isWalk 304 rat.io.specWritePorts(i).addr := io.roqCommits.info(i).ldest 305 rat.io.specWritePorts(i).wdata := io.roqCommits.info(i).old_pdest 306 } 307 308 when (commitDestValid && io.roqCommits.isWalk) { 309 XSInfo({if(fp) p"[fp" else p"[int"} + p" walk] " + 310 p"ldest:${rat.io.specWritePorts(i).addr} -> old_pdest:${rat.io.specWritePorts(i).wdata}\n") 311 } 312 313 // normal write - update arch state (serve as initialization) 314 rat.io.archWritePorts(i).wen := commitDestValid && !io.roqCommits.isWalk 315 rat.io.archWritePorts(i).addr := io.roqCommits.info(i).ldest 316 rat.io.archWritePorts(i).wdata := io.roqCommits.info(i).pdest 317 318 XSInfo(rat.io.archWritePorts(i).wen, 319 {if(fp) p"[fp" else p"[int"} + p" arch rat update] ldest:${rat.io.archWritePorts(i).addr} ->" + 320 p" pdest:${rat.io.archWritePorts(i).wdata}\n" 321 ) 322 323 324 /* 325 II. Free List Update 326 */ 327 328 if (fp) { // Float Point free list 329 fpFreeList.freeReq(i) := commitDestValid && !io.roqCommits.isWalk 330 fpFreeList.freePhyReg(i) := io.roqCommits.info(i).old_pdest 331 } else if (EnableIntMoveElim) { // Integer free list 332 333 // during walk process: 334 // 1. for normal inst, free pdest + revert rat from ldest->pdest to ldest->old_pdest 335 // 2. for ME inst, free pdest(commit counter++) + revert rat 336 337 // conclusion: 338 // a. rat recovery has nothing to do with ME or not 339 // b. treat walk as normal commit except replace old_pdests with pdests and set io.walk to true 340 // c. ignore pdests port when walking 341 342 intFreeList.freeReq(i) := commitDestValid // walk or not walk 343 intFreeList.freePhyReg(i) := Mux(io.roqCommits.isWalk, io.roqCommits.info(i).pdest, io.roqCommits.info(i).old_pdest) 344 intFreeList.asInstanceOf[freelist.MEFreeList].eliminatedMove(i) := io.roqCommits.info(i).eliminatedMove 345 intFreeList.asInstanceOf[freelist.MEFreeList].multiRefPhyReg(i) := io.roqCommits.info(i).pdest 346 } else { 347 intFreeList.freeReq(i) := commitDestValid && !io.roqCommits.isWalk 348 intFreeList.freePhyReg(i) := io.roqCommits.info(i).old_pdest 349 } 350 } 351 } 352 353 354 /* 355 Debug and performance counter 356 */ 357 358 def printRenameInfo(in: DecoupledIO[CfCtrl], out: DecoupledIO[MicroOp]) = { 359 XSInfo( 360 in.valid && in.ready, 361 p"pc:${Hexadecimal(in.bits.cf.pc)} in v:${in.valid} in rdy:${in.ready} " + 362 p"lsrc(0):${in.bits.ctrl.lsrc(0)} -> psrc(0):${out.bits.psrc(0)} " + 363 p"lsrc(1):${in.bits.ctrl.lsrc(1)} -> psrc(1):${out.bits.psrc(1)} " + 364 p"lsrc(2):${in.bits.ctrl.lsrc(2)} -> psrc(2):${out.bits.psrc(2)} " + 365 p"ldest:${in.bits.ctrl.ldest} -> pdest:${out.bits.pdest} " + 366 p"old_pdest:${out.bits.old_pdest} " + 367 p"out v:${out.valid} r:${out.ready}\n" 368 ) 369 } 370 371 for((x,y) <- io.in.zip(io.out)){ 372 printRenameInfo(x, y) 373 } 374 375 XSDebug(io.roqCommits.isWalk, p"Walk Recovery Enabled\n") 376 XSDebug(io.roqCommits.isWalk, p"validVec:${Binary(io.roqCommits.valid.asUInt)}\n") 377 for (i <- 0 until CommitWidth) { 378 val info = io.roqCommits.info(i) 379 XSDebug(io.roqCommits.isWalk && io.roqCommits.valid(i), p"[#$i walk info] pc:${Hexadecimal(info.pc)} " + 380 p"ldest:${info.ldest} rfWen:${info.rfWen} fpWen:${info.fpWen} " + { if (EnableIntMoveElim) p"eliminatedMove:${info.eliminatedMove} " else p"" } + 381 p"pdest:${info.pdest} old_pdest:${info.old_pdest}\n") 382 } 383 384 XSDebug(p"inValidVec: ${Binary(Cat(io.in.map(_.valid)))}\n") 385 XSInfo(!canOut, p"stall at rename, hasValid:${hasValid}, fpCanAlloc:${fpFreeList.canAllocate}, intCanAlloc:${intFreeList.canAllocate} dispatch1ready:${io.out(0).ready}, isWalk:${io.roqCommits.isWalk}\n") 386 387 intRat.io.debug_rdata <> io.debug_int_rat 388 fpRat.io.debug_rdata <> io.debug_fp_rat 389 390 XSDebug(p"Arch Int RAT:" + io.debug_int_rat.zipWithIndex.map{ case (r, i) => p"#$i:$r " }.reduceLeft(_ + _) + p"\n") 391 392 XSPerfAccumulate("in", Mux(RegNext(io.in(0).ready), PopCount(io.in.map(_.valid)), 0.U)) 393 XSPerfAccumulate("utilization", PopCount(io.in.map(_.valid))) 394 XSPerfAccumulate("waitInstr", PopCount((0 until RenameWidth).map(i => io.in(i).valid && !io.in(i).ready))) 395 XSPerfAccumulate("stall_cycle_dispatch", hasValid && !io.out(0).ready && fpFreeList.canAllocate && intFreeList.canAllocate && !io.roqCommits.isWalk) 396 XSPerfAccumulate("stall_cycle_fp", hasValid && io.out(0).ready && !fpFreeList.canAllocate && intFreeList.canAllocate && !io.roqCommits.isWalk) 397 XSPerfAccumulate("stall_cycle_int", hasValid && io.out(0).ready && fpFreeList.canAllocate && !intFreeList.canAllocate && !io.roqCommits.isWalk) 398 XSPerfAccumulate("stall_cycle_walk", hasValid && io.out(0).ready && fpFreeList.canAllocate && intFreeList.canAllocate && io.roqCommits.isWalk) 399 400 401 if (EnableIntMoveElim) { 402 XSPerfAccumulate("move_instr_count", PopCount(Seq.tabulate(RenameWidth)(i => io.out(i).fire() && io.in(i).bits.ctrl.isMove))) 403 XSPerfAccumulate("move_elim_enabled", PopCount(Seq.tabulate(RenameWidth)(i => io.out(i).fire() && meEnable(i)))) 404 XSPerfAccumulate("move_elim_cancelled", PopCount(Seq.tabulate(RenameWidth)(i => io.out(i).fire() && io.in(i).bits.ctrl.isMove && !meEnable(i)))) 405 XSPerfAccumulate("move_elim_cancelled_psrc_bypass", PopCount(Seq.tabulate(RenameWidth)(i => io.out(i).fire() && io.in(i).bits.ctrl.isMove && !meEnable(i) && { if (i == 0) false.B else io.renameBypass.lsrc1_bypass(i-1).orR }))) 406 XSPerfAccumulate("move_elim_cancelled_cnt_limit", PopCount(Seq.tabulate(RenameWidth)(i => io.out(i).fire() && io.in(i).bits.ctrl.isMove && !meEnable(i) && isMax.get(io.out(i).bits.psrc(0))))) 407 XSPerfAccumulate("move_elim_cancelled_inc_more_than_one", PopCount(Seq.tabulate(RenameWidth)(i => io.out(i).fire() && io.in(i).bits.ctrl.isMove && !meEnable(i) && { if (i == 0) false.B else psrc_cmp(i-1).orR }))) 408 409 // to make sure meEnable functions as expected 410 for (i <- 0 until RenameWidth) { 411 XSDebug(io.out(i).fire() && io.in(i).bits.ctrl.isMove && !meEnable(i) && isMax.get(io.out(i).bits.psrc(0)), 412 p"ME_CANCELLED: ref counter hits max value (pc:0x${Hexadecimal(io.in(i).bits.cf.pc)})\n") 413 XSDebug(io.out(i).fire() && io.in(i).bits.ctrl.isMove && !meEnable(i) && { if (i == 0) false.B else io.renameBypass.lsrc1_bypass(i-1).orR }, 414 p"ME_CANCELLED: RAW dependency (pc:0x${Hexadecimal(io.in(i).bits.cf.pc)})\n") 415 XSDebug(io.out(i).fire() && io.in(i).bits.ctrl.isMove && !meEnable(i) && { if (i == 0) false.B else psrc_cmp(i-1).orR }, 416 p"ME_CANCELLED: psrc duplicates with former instruction (pc:0x${Hexadecimal(io.in(i).bits.cf.pc)})\n") 417 } 418 XSDebug(VecInit(Seq.tabulate(RenameWidth)(i => io.out(i).fire() && io.in(i).bits.ctrl.isMove && !meEnable(i))).asUInt().orR, 419 p"ME_CANCELLED: pc group [ " + (0 until RenameWidth).map(i => p"fire:${io.out(i).fire()},pc:0x${Hexadecimal(io.in(i).bits.cf.pc)} ").reduceLeft(_ + _) + p"]\n") 420 XSInfo(meEnable.asUInt().orR(), p"meEnableVec:${Binary(meEnable.asUInt)}\n") 421 } 422} 423