xref: /XiangShan/src/main/scala/xiangshan/Parameters.scala (revision 1a2cf1521d2269374286d137546263e946c0fc7c) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan
18
19import chipsalliance.rocketchip.config.{Field, Parameters}
20import chisel3._
21import chisel3.util._
22import xiangshan.backend.exu._
23import xiangshan.backend.fu._
24import xiangshan.backend.fu.fpu._
25import xiangshan.backend.dispatch.DispatchParameters
26import xiangshan.cache.{DCacheParameters, ICacheParameters, L1plusCacheParameters}
27import xiangshan.cache.prefetch.{BOPParameters, L1plusPrefetcherParameters, L2PrefetcherParameters, StreamPrefetchParameters}
28import freechips.rocketchip.diplomacy.AddressSet
29
30case object XSCoreParamsKey extends Field[XSCoreParameters]
31
32case class XSCoreParameters
33(
34  HasPrefetch: Boolean = false,
35  HartId: Int = 0,
36  XLEN: Int = 64,
37  HasMExtension: Boolean = true,
38  HasCExtension: Boolean = true,
39  HasDiv: Boolean = true,
40  HasICache: Boolean = true,
41  HasDCache: Boolean = true,
42  AddrBits: Int = 64,
43  VAddrBits: Int = 39,
44  PAddrBits: Int = 40,
45  HasFPU: Boolean = true,
46  FetchWidth: Int = 8,
47  EnableBPU: Boolean = true,
48  EnableBPD: Boolean = true,
49  EnableRAS: Boolean = true,
50  EnableLB: Boolean = false,
51  EnableLoop: Boolean = true,
52  EnableSC: Boolean = true,
53  EnbaleTlbDebug: Boolean = false,
54  EnableJal: Boolean = false,
55  EnableUBTB: Boolean = true,
56  HistoryLength: Int = 64,
57  BtbSize: Int = 2048,
58  JbtacSize: Int = 1024,
59  JbtacBanks: Int = 8,
60  RasSize: Int = 16,
61  CacheLineSize: Int = 512,
62  UBtbWays: Int = 16,
63  BtbWays: Int = 2,
64
65  EnableL1plusPrefetcher: Boolean = true,
66  IBufSize: Int = 48,
67  DecodeWidth: Int = 6,
68  RenameWidth: Int = 6,
69  CommitWidth: Int = 6,
70  BrqSize: Int = 32,
71  FtqSize: Int = 48,
72  EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false
73  IssQueSize: Int = 16,
74  NRPhyRegs: Int = 160,
75  NRIntReadPorts: Int = 14,
76  NRIntWritePorts: Int = 8,
77  NRFpReadPorts: Int = 14,
78  NRFpWritePorts: Int = 8,
79  LoadQueueSize: Int = 64,
80  StoreQueueSize: Int = 48,
81  RoqSize: Int = 192,
82  dpParams: DispatchParameters = DispatchParameters(
83    IntDqSize = 16,
84    FpDqSize = 16,
85    LsDqSize = 16,
86    IntDqDeqWidth = 4,
87    FpDqDeqWidth = 4,
88    LsDqDeqWidth = 4
89  ),
90  exuParameters: ExuParameters = ExuParameters(
91    JmpCnt = 1,
92    AluCnt = 4,
93    MulCnt = 0,
94    MduCnt = 2,
95    FmacCnt = 4,
96    FmiscCnt = 2,
97    FmiscDivSqrtCnt = 0,
98    LduCnt = 2,
99    StuCnt = 2
100  ),
101  LoadPipelineWidth: Int = 2,
102  StorePipelineWidth: Int = 2,
103  StoreBufferSize: Int = 16,
104  StoreBufferThreshold: Int = 7,
105  RefillSize: Int = 512,
106  TlbEntrySize: Int = 32,
107  TlbSPEntrySize: Int = 4,
108  PtwL3EntrySize: Int = 4096, //(512 * 8) or 512
109  PtwSPEntrySize: Int = 16,
110  PtwL1EntrySize: Int = 16,
111  PtwL2EntrySize: Int = 256, //(256 * 8)
112  PtwMissQueueSize: Int = 8,
113  NumPerfCounters: Int = 16,
114  icacheParameters: ICacheParameters = ICacheParameters(
115    tagECC = Some("parity"),
116    dataECC = Some("parity"),
117    replacer = Some("setplru"),
118    nMissEntries = 2
119  ),
120  l1plusCacheParameters: L1plusCacheParameters = L1plusCacheParameters(
121    tagECC = Some("secded"),
122    dataECC = Some("secded"),
123    replacer = Some("setplru"),
124    nMissEntries = 8
125  ),
126  dcacheParameters: DCacheParameters = DCacheParameters(
127    tagECC = Some("secded"),
128    dataECC = Some("secded"),
129    replacer = Some("setplru"),
130    nMissEntries = 16,
131    nProbeEntries = 16,
132    nReleaseEntries = 16,
133    nStoreReplayEntries = 16
134  ),
135  L2Size: Int = 512 * 1024, // 512KB
136  L2NWays: Int = 8,
137  usePTWRepeater: Boolean = false,
138  useFakePTW: Boolean = false,
139  useFakeDCache: Boolean = false,
140  useFakeL1plusCache: Boolean = false,
141  useFakeL2Cache: Boolean = false
142){
143  val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg)
144  val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg)
145
146  val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++
147    Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) ++
148    Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg)
149
150  val fpExuConfigs =
151    Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++
152      Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg)
153
154  val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs
155}
156
157case object DebugOptionsKey extends Field[DebugOptions]
158
159case class DebugOptions
160(
161  FPGAPlatform: Boolean = true,
162  EnableDebug: Boolean = true,
163  EnablePerfDebug: Boolean = true,
164  UseDRAMSim: Boolean = false
165)
166
167trait HasXSParameter {
168
169  implicit val p: Parameters
170
171  val coreParams = p(XSCoreParamsKey)
172  val env = p(DebugOptionsKey)
173
174  val XLEN = coreParams.XLEN
175  val hardId = coreParams.HartId
176  val minFLen = 32
177  val fLen = 64
178  def xLen = XLEN
179
180  val HasMExtension = coreParams.HasMExtension
181  val HasCExtension = coreParams.HasCExtension
182  val HasDiv = coreParams.HasDiv
183  val HasIcache = coreParams.HasICache
184  val HasDcache = coreParams.HasDCache
185  val AddrBits = coreParams.AddrBits // AddrBits is used in some cases
186  val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits
187  val PAddrBits = coreParams.PAddrBits // PAddrBits is Phyical Memory addr bits
188  val AddrBytes = AddrBits / 8 // unused
189  val DataBits = XLEN
190  val DataBytes = DataBits / 8
191  val HasFPU = coreParams.HasFPU
192  val FetchWidth = coreParams.FetchWidth
193  val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1)
194  val EnableBPU = coreParams.EnableBPU
195  val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3
196  val EnableRAS = coreParams.EnableRAS
197  val EnableLB = coreParams.EnableLB
198  val EnableLoop = coreParams.EnableLoop
199  val EnableSC = coreParams.EnableSC
200  val EnbaleTlbDebug = coreParams.EnbaleTlbDebug
201  val HistoryLength = coreParams.HistoryLength
202  val BtbSize = coreParams.BtbSize
203  // val BtbWays = 4
204  val BtbBanks = PredictWidth
205  // val BtbSets = BtbSize / BtbWays
206  val JbtacSize = coreParams.JbtacSize
207  val JbtacBanks = coreParams.JbtacBanks
208  val RasSize = coreParams.RasSize
209  val CacheLineSize = coreParams.CacheLineSize
210  val CacheLineHalfWord = CacheLineSize / 16
211  val ExtHistoryLength = HistoryLength + 64
212  val UBtbWays = coreParams.UBtbWays
213  val BtbWays = coreParams.BtbWays
214  val EnableL1plusPrefetcher = coreParams.EnableL1plusPrefetcher
215  val IBufSize = coreParams.IBufSize
216  val DecodeWidth = coreParams.DecodeWidth
217  val RenameWidth = coreParams.RenameWidth
218  val CommitWidth = coreParams.CommitWidth
219  val BrqSize = coreParams.BrqSize
220  val FtqSize = coreParams.FtqSize
221  val IssQueSize = coreParams.IssQueSize
222  val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp
223  val BrTagWidth = log2Up(BrqSize)
224  val NRPhyRegs = coreParams.NRPhyRegs
225  val PhyRegIdxWidth = log2Up(NRPhyRegs)
226  val RoqSize = coreParams.RoqSize
227  val LoadQueueSize = coreParams.LoadQueueSize
228  val StoreQueueSize = coreParams.StoreQueueSize
229  val dpParams = coreParams.dpParams
230  val exuParameters = coreParams.exuParameters
231  val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt
232  val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts
233  val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt
234  val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt
235  val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt
236  val LoadPipelineWidth = coreParams.LoadPipelineWidth
237  val StorePipelineWidth = coreParams.StorePipelineWidth
238  val StoreBufferSize = coreParams.StoreBufferSize
239  val StoreBufferThreshold = coreParams.StoreBufferThreshold
240  val RefillSize = coreParams.RefillSize
241  val DTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth
242  val TlbEntrySize = coreParams.TlbEntrySize
243  val TlbSPEntrySize = coreParams.TlbSPEntrySize
244  val PtwL3EntrySize = coreParams.PtwL3EntrySize
245  val PtwSPEntrySize = coreParams.PtwSPEntrySize
246  val PtwL1EntrySize = coreParams.PtwL1EntrySize
247  val PtwL2EntrySize = coreParams.PtwL2EntrySize
248  val PtwMissQueueSize = coreParams.PtwMissQueueSize
249  val NumPerfCounters = coreParams.NumPerfCounters
250
251  val instBytes = if (HasCExtension) 2 else 4
252  val instOffsetBits = log2Ceil(instBytes)
253
254  val icacheParameters = coreParams.icacheParameters
255  val l1plusCacheParameters = coreParams.l1plusCacheParameters
256  val dcacheParameters = coreParams.dcacheParameters
257
258  val LRSCCycles = 100
259
260
261  // cache hierarchy configurations
262  val l1BusDataWidth = 256
263
264  val usePTWRepeater = coreParams.usePTWRepeater
265  val useFakeDCache = coreParams.useFakeDCache
266  val useFakePTW = coreParams.useFakePTW
267  val useFakeL1plusCache = coreParams.useFakeL1plusCache
268  // L2 configurations
269  val useFakeL2Cache = useFakeDCache && useFakePTW && useFakeL1plusCache || coreParams.useFakeL2Cache
270  val L1BusWidth = 256
271  val L2Size = coreParams.L2Size
272  val L2BlockSize = 64
273  val L2NWays = coreParams.L2NWays
274  val L2NSets = L2Size / L2BlockSize / L2NWays
275
276  // L3 configurations
277  val L2BusWidth = 256
278
279  // icache prefetcher
280  val l1plusPrefetcherParameters = L1plusPrefetcherParameters(
281    enable = true,
282    _type = "stream",
283    streamParams = StreamPrefetchParameters(
284      streamCnt = 2,
285      streamSize = 4,
286      ageWidth = 4,
287      blockBytes = l1plusCacheParameters.blockBytes,
288      reallocStreamOnMissInstantly = true,
289      cacheName = "icache"
290    )
291  )
292
293  // dcache prefetcher
294  val l2PrefetcherParameters = L2PrefetcherParameters(
295    enable = true,
296    _type = "bop", // "stream" or "bop"
297    streamParams = StreamPrefetchParameters(
298      streamCnt = 4,
299      streamSize = 4,
300      ageWidth = 4,
301      blockBytes = L2BlockSize,
302      reallocStreamOnMissInstantly = true,
303      cacheName = "dcache"
304    ),
305    bopParams = BOPParameters(
306      rrTableEntries = 256,
307      rrTagBits = 12,
308      scoreBits = 5,
309      roundMax = 50,
310      badScore = 1,
311      blockBytes = L2BlockSize,
312      nEntries = dcacheParameters.nMissEntries * 2 // TODO: this is too large
313    ),
314  )
315
316  // load violation predict
317  val ResetTimeMax2Pow = 20 //1078576
318  val ResetTimeMin2Pow = 10 //1024
319  // wait table parameters
320  val WaitTableSize = 1024
321  val MemPredPCWidth = log2Up(WaitTableSize)
322  val LWTUse2BitCounter = true
323  // store set parameters
324  val SSITSize = WaitTableSize
325  val LFSTSize = 32
326  val SSIDWidth = log2Up(LFSTSize)
327  val LFSTWidth = 4
328  val StoreSetEnable = true // LWT will be disabled if SS is enabled
329
330  val loadExuConfigs = coreParams.loadExuConfigs
331  val storeExuConfigs = coreParams.storeExuConfigs
332
333  val intExuConfigs = coreParams.intExuConfigs
334
335  val fpExuConfigs = coreParams.fpExuConfigs
336
337  val exuConfigs = coreParams.exuConfigs
338
339}
340