| 0d32f713 | 06-Sep-2023 |
happy-lx <[email protected]> |
L1 Prefetch (#2261)
* dcache: optimize the ready signal of missqueue
Add a custom arbiter. In the case of multiple sources with the same
cache block address, the arbiter will assign only one ent
L1 Prefetch (#2261)
* dcache: optimize the ready signal of missqueue
Add a custom arbiter. In the case of multiple sources with the same
cache block address, the arbiter will assign only one entry in
misssqueue but ready for all same cache block address requests.
This will reduce the number of replays of the load instruction which cannot
enter the missqueue
* sta, dcache: add A StorePipe in dcache
When the store command passes through the sta pipeline, access the tag
and meta of dcache to determine whether it hits, if it hits, update the
replacement algorithm, and if miss, send a write intent to missqueue
* sta prefetch: add a queue
Enter this queue when the Store Address pipeline sends a request,
determines that it has a cache miss, and the contention for MSHR fails.
The miss request in this queue will be sent to the Store pipeline later.
* sbuffer, dcache: store prefetch burst
A basic implementation of "Boosting Store Buffer Efficiency with
Store-Prefetch Bursts".
Store prefetch at exe is disabled.
Now, when store goes from sq to sbuffer, it will trigger a store
prefetch; when 48 stores fall into 6 cache lines, trigger a store burst
perfetch, which will bring a whole page back into dcache.
* dcache: restric mshr alloc for prefetch req
* restric the max number of entries which can be used by prefetch
* merge two same cache line address prefetch write req
* dynamically detect memset pattern, all mshr can accept prefetch when
pattern is detected
* spb: constantin support
* dcache: fix missqueue prefetch ready
* make prefetch req goes mshr with bigger id
* Revert "spb: constantin support"
This reverts commit 4ee50b89ba4a62cd28fa22d7fbcb2338ad4b1849.
* spb: fix bug in burst generator
* spb: add load prefetch burst support
* topdown: add defines of topdown counters enum
* redirect: add redirect type for perf
* top-down: add stallReason IOs
frontend -> ctrlBlock -> decode -> rename -> dispatch
* top-down: add dummy connections
* top-down: update TopdownCounters
* top-down: imp backend analysis and counter dump
* top-down: add HartId in `addSource`
* top-down: broadcast lqIdx of ROB head
* top-down: frontend signal done
* top-down: add memblock topdown interface
* Bump HuanCun: add TopDownMonitor
* top-down: receive and handle reasons in dispatch
* top-down: remove previous top-down code
* TopDown: add MemReqSource enum
* TopDown: extend mshr_latency range
* TopDown: add basic Req Source
TODO: distinguish prefetch
* store prefetch: refactor parameters and fix bug
* change some parameters
* fix store pipe bug
* fix load prefetch burst
* dcache: distinguish L1DataPrefetch and CPUData
* top-down: comment out debugging perf counters in ibuffer
* TopDown: add path to pass MemReqSource to HuanCun
* TopDown: use simpler logic to count reqSource and update Probe count
* frontend: update topdown counters
* Update HuanCun Topdown for MemReqSource
* top-down: fix load stalls
* top-down: Change the priority of different stall reasons
* store prefetch: add stride and l2 prefetch
* add a stride prefetcher
* spb and stride will issue prefetch to l2
* when store commits, issue a prefetch to l1
* sbuffer: fix eviction
* when valid count reaches StoreBufferSize, do eviction
* spf: change store prefetch structure
* prefetch @ exe -> l2 cache
* stride -> l2 cache
* sbuffer: fix replaceIdx
* If the way selected by the replacement algorithm cannot be written into dcache, its result is not used.
* Revert "sbuffer: fix replaceIdx"
This reverts commit 40c16aca956af9fb32554a0f12d18db41c22eecd.
* spf: find best interval in stamissqueue
* Revert "spf: find best interval in stamissqueue"
This reverts commit d179f0ce15a5ab989a822de7fe48cc5e2cd96914.
* sms: port store to sms
Miss store will train sms like load.
Now, sms will recieve 4 train sources, 2 for miss load, 2 for miss
store, but prefetcher consume 1 train req per cycle, PrefetchTrainFilter
is added to deal with this case.
* bump huancun
* spf: refactor structure
* miss stores will train sms, and send prefetch to l2
* miss stores will send prefetch to l1 on issue or commit
* spb will send prefetch to l1
* memset: fix memset detection
use lqEmpty to check this
* constantin: storepf constantin support
cherry-pick this to use constantin in storepf
* Revert "constantin: storepf constantin support"
This reverts commit 2b97767b9fa757d920cac3d80d4893a1380592c7.
* storepf: add EnableAtCommitMissTrigger
* trigger prefetch at commit only when the store misses with
EnableAtCommitMissTrigger
* bump coupledl2
* prefetch req from L1 to L2 will Acquire T
* fix merge conflict
* storepf: do not read meta&tag when pf is disabled
* storepf: do not read pcMem when sms store is disabled
* fix verilog check
* fix verilog
* missqueue: support merging prefetch
* prefetch req can be merged to pipeline reg
* merging prefetch write will update cmd
* delay sending out acquire when a prefetch write is about to merge
* missqueue: fix bug of merging prefetch write
* delay sending out acquire when a pipeline reg is about to merging a
prefetch write
* temp: disable store pf
* missqueue: disable merging prefetch
* late prefetch will be ignored
* check alias when merging
* enable store pf at issue
* add L1StreamPrefetcher
* fix assert
* let prefetch req prefer loadunit1 more than 0
* stream prefetcher
* disable stream component in SMS, SMS is only trained on real miss
* add a prefetcher monitor to adjust depth & confidence ..
* add L1 L2 stream prefetch
* add gene support
* Revert "add gene support"
This reverts commit 59ae15640ff3d1cc96347f4d3567d48c740a03bb.
* add miss db
* l1pf: add stride & store source info in cache meta
* add a Stride prefetcher and disable Stride component in sms
* prefetch bit in meta is expanded into 3 bits to store source info of
prefetcher
* prefetch: support sending prefetch req to l3
* l1pf: add FDP & refactor
* add basic FDP counters
* change stride from Block addr to Byte addr
* refactor the code
* bump submodules
* disable load related chiseldb to reduce db size
* fix compile
* fix minimalConfig & enable stream
* fix stride pc problem
* fix minimalconfig compile
* bump submodules
* refactor stream stride helper
* fix compile
* bump huancun
* disable db to save size
* fix l2 assert
* bump submodules
---------
Co-authored-by: tastynoob <[email protected]>
Co-authored-by: Haojin Tang <[email protected]>
Co-authored-by: Guokai Chen <[email protected]>
Co-authored-by: XiChen <[email protected]>
Co-authored-by: Zhou Yaoyang <[email protected]>
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| 2fdb4d6a | 25-Jul-2023 |
happy-lx <[email protected]> |
Fix sbuffer's eviction and replace logic (#2075)
when valid count reaches StoreBufferSize, do eviction
* If the way selected by the replacement algorithm cannot be written into dcache, its result i
Fix sbuffer's eviction and replace logic (#2075)
when valid count reaches StoreBufferSize, do eviction
* If the way selected by the replacement algorithm cannot be written into dcache, its result is not used
* It should remove store stall we observed in lbm.
* Add the dynamic prioritization mechanism between load stores.
* Detects the number of valid entries in the storeQueue, and if it is larger than ForceWriteUpper, forces the sbuffer to be written down to Dcache until the number of valid entries in the storeQueue is lower than ForceWriteLower.
---------
Co-authored-by: Lyn <[email protected]>
Co-authored-by: sfencevma <[email protected]>
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| 3d3419b9 | 26-Jul-2022 |
William Wang <[email protected]> |
sbuffer: add an extra cycle for sbuffer write
In previous design, sbuffer valid entry select and
sbuffer data write are in the same cycle, which
caused huge fanout. An extra write stage is added to
sbuffer: add an extra cycle for sbuffer write
In previous design, sbuffer valid entry select and
sbuffer data write are in the same cycle, which
caused huge fanout. An extra write stage is added to
solve this problem.
Now sbuffer enq logic is divided into 3 stages:
sbuffer_in_s0:
* read data and meta from store queue
* store them in 2 entry fifo queue
sbuffer_in_s1:
* read data and meta from fifo queue
* update sbuffer meta (vtag, ptag, flag)
* prevert that line from being sent to dcache (add a block condition)
* prepare cacheline level write enable signal, RegNext() data and mask
sbuffer_in_s2:
* use cacheline level buffer to update sbuffer data and mask
* remove dcache write block (if there is)
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