1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.exu 18 19 20import org.chipsalliance.cde.config.Parameters 21import chisel3._ 22import chisel3.experimental.hierarchy.{Definition, instantiable} 23import chisel3.util._ 24import utils._ 25import utility._ 26import xiangshan._ 27import xiangshan.backend.fu.fpu.{FMA, FPUSubModule} 28import xiangshan.backend.fu.{CSR, FUWithRedirect, Fence, FenceToSbuffer} 29 30class FenceIO(implicit p: Parameters) extends XSBundle { 31 val sfence = Output(new SfenceBundle) 32 val fencei = Output(Bool()) 33 val sbuffer = new FenceToSbuffer 34} 35 36@instantiable 37class ExeUnit(config: ExuConfig)(implicit p: Parameters) extends Exu(config) { 38 39 val disableSfence = WireInit(false.B) 40 val csr_frm = WireInit(frm.getOrElse(0.U(3.W))) 41 42 val hasRedirect = config.fuConfigs.zip(functionUnits).filter(_._1.hasRedirect).map(_._2) 43 println(s"${functionUnits} ${hasRedirect} hasRedirect: ${hasRedirect.length}") 44 if (hasRedirect.nonEmpty) { 45 require(hasRedirect.length <= 1) 46 io.out.bits.redirectValid := hasRedirect.head.asInstanceOf[FUWithRedirect].redirectOutValid 47 io.out.bits.redirect := hasRedirect.head.asInstanceOf[FUWithRedirect].redirectOut 48 } 49 50 if (config.fuConfigs.contains(csrCfg)) { 51 val csr = functionUnits.collectFirst{ 52 case c: CSR => c 53 }.get 54 csr.csrio <> csrio.get 55 csrio.get.tlb := DelayN(csr.csrio.tlb, 2) 56 csrio.get.customCtrl := DelayN(csr.csrio.customCtrl, 2) 57 csrio.get.trapTarget := RegNext(csr.csrio.trapTarget) 58 csr.csrio.exception := DelayN(csrio.get.exception, 2) 59 disableSfence := csr.csrio.disableSfence 60 csr_frm := csr.csrio.fpu.frm 61 // setup skip for hpm CSR read 62 io.out.bits.debug.isPerfCnt := RegNext(csr.csrio.isPerfCnt) // TODO: this is dirty 63 } 64 65 if (config.fuConfigs.contains(fenceCfg)) { 66 val fence = functionUnits.collectFirst{ 67 case f: Fence => f 68 }.get 69 fenceio.get.sfence <> fence.sfence 70 fenceio.get.fencei <> fence.fencei 71 fenceio.get.sbuffer <> fence.toSbuffer 72 fence.io.out.ready := true.B 73 fence.disableSfence := disableSfence 74 } 75 76 val fpModules = functionUnits.zip(config.fuConfigs.zipWithIndex).filter(_._1.isInstanceOf[FPUSubModule]) 77 if (fpModules.nonEmpty) { 78 // frm is from csr/frm (from CSR) or instr_rm (from instruction decoding) 79 val fpSubModules = fpModules.map(_._1.asInstanceOf[FPUSubModule]) 80 fpSubModules.foreach(mod => { 81 val instr_rm = mod.io.in.bits.uop.ctrl.fpu.rm 82 mod.rm := Mux(instr_rm =/= 7.U, instr_rm, csr_frm) 83 }) 84 // fflags is selected by arbSelReg 85 require(config.hasFastUopOut, "non-fast not implemented") 86 val fflagsSel = fpModules.map{ case (fu, (cfg, i)) => 87 val fflagsValid = arbSelReg(i) 88 val fflags = fu.asInstanceOf[FPUSubModule].fflags 89 val fflagsBits = if (cfg.fastImplemented) fflags else RegNext(fflags) 90 (fflagsValid, fflagsBits) 91 } 92 io.out.bits.fflags := Mux1H(fflagsSel.map(_._1), fflagsSel.map(_._2)) 93 } 94 95 val fmaModules = functionUnits.filter(_.isInstanceOf[FMA]).map(_.asInstanceOf[FMA]) 96 if (fmaModules.nonEmpty) { 97 require(fmaModules.length == 1) 98 fmaModules.head.midResult <> fmaMid.get 99 } 100 101 if (config.readIntRf) { 102 val in = io.fromInt 103 val out = io.out 104 XSDebug(in.valid, p"fromInt(${in.valid} ${in.ready}) toInt(${out.valid} ${out.ready})\n") 105 XSDebug(io.redirect.valid, p"Redirect:(${io.redirect.valid}) robIdx:${io.redirect.bits.robIdx}\n") 106 XSDebug(in.valid, p"src1:${Hexadecimal(in.bits.src(0))} src2:${Hexadecimal(in.bits.src(1))} " + 107 p"func:${Binary(in.bits.uop.ctrl.fuOpType)} pc:${Hexadecimal(in.bits.uop.cf.pc)} robIdx:${in.bits.uop.robIdx}\n") 108 XSDebug(out.valid, p"out res:${Hexadecimal(out.bits.data)} robIdx:${out.bits.uop.robIdx}\n") 109 } 110 111} 112 113class AluExeUnit(implicit p: Parameters) extends ExeUnit(AluExeUnitCfg) 114class JumpCSRExeUnit(implicit p: Parameters) extends ExeUnit(JumpCSRExeUnitCfg) 115class JumpExeUnit(implicit p: Parameters) extends ExeUnit(JumpExeUnitCfg) 116class StdExeUnit(implicit p: Parameters) extends ExeUnit(StdExeUnitCfg) 117class FmacExeUnit(implicit p: Parameters) extends ExeUnit(FmacExeUnitCfg) 118class FmiscExeUnit(implicit p: Parameters) extends ExeUnit(FmiscExeUnitCfg) 119 120object ExeUnitDef { 121 val defMap = new scala.collection.mutable.HashMap[ExuConfig, Definition[ExeUnit]]() 122 123 def apply(cfg: ExuConfig)(implicit p: Parameters): Definition[ExeUnit] = { 124 cfg match { 125 case JumpExeUnitCfg => defMap.getOrElseUpdate(cfg, Definition(new JumpExeUnit)) 126 case AluExeUnitCfg => defMap.getOrElseUpdate(cfg, Definition(new AluExeUnit)) 127 case MulDivExeUnitCfg => defMap.getOrElseUpdate(cfg, Definition(new MulDivExeUnit)) 128 // TODO: CSR should also use instance. We need to fix difftest. 129 // We should not call DifftestModule in Definition/Instance for now. 130 case JumpCSRExeUnitCfg => Definition(new JumpCSRExeUnit) 131 case FmacExeUnitCfg => defMap.getOrElseUpdate(cfg, Definition(new FmacExeUnit)) 132 case FmiscExeUnitCfg => defMap.getOrElseUpdate(cfg, Definition(new FmiscExeUnit)) 133 case StdExeUnitCfg => defMap.getOrElseUpdate(cfg, Definition(new StdExeUnit)) 134 case _ => { 135 println(s"cannot generate exeUnit from $cfg") 136 null 137 } 138 } 139 } 140} 141