1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import freechips.rocketchip.rocket.Instructions._ 29 30/** 31 * Abstract trait giving defaults and other relevant values to different Decode constants/ 32 */ 33abstract trait DecodeConstants { 34 // This X should be used only in 1-bit signal. Otherwise, use BitPat("b???") to align with the width of UInt. 35 def X = BitPat("b?") 36 def N = BitPat("b0") 37 def Y = BitPat("b1") 38 39 def decodeDefault: List[BitPat] = // illegal instruction 40 // srcType(0) srcType(1) srcType(2) fuType fuOpType rfWen 41 // | | | | | | fpWen 42 // | | | | | | | isXSTrap 43 // | | | | | | | | noSpecExec 44 // | | | | | | | | | blockBackward 45 // | | | | | | | | | | flushPipe 46 // | | | | | | | | | | | selImm 47 // | | | | | | | | | | | | 48 List(SrcType.X, SrcType.X, SrcType.X, FuType.X, FuOpType.X, N, N, N, N, N, N, SelImm.INVALID_INSTR) // Use SelImm to indicate invalid instr 49 50 val table: Array[(BitPat, List[BitPat])] 51} 52 53trait DecodeUnitConstants 54{ 55 // abstract out instruction decode magic numbers 56 val RD_MSB = 11 57 val RD_LSB = 7 58 val RS1_MSB = 19 59 val RS1_LSB = 15 60 val RS2_MSB = 24 61 val RS2_LSB = 20 62 val RS3_MSB = 31 63 val RS3_LSB = 27 64} 65 66/** 67 * Decoded control signals 68 * See xiangshan/package.scala, xiangshan/backend/package.scala, Bundle.scala 69 */ 70 71/** 72 * Decode constants for RV64 73 */ 74object X64Decode extends DecodeConstants { 75 val table: Array[(BitPat, List[BitPat])] = Array( 76 LD -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.ld, Y, N, N, N, N, N, SelImm.IMM_I), 77 LWU -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lwu, Y, N, N, N, N, N, SelImm.IMM_I), 78 SD -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.sd, N, N, N, N, N, N, SelImm.IMM_S), 79 80 SLLI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sll, Y, N, N, N, N, N, SelImm.IMM_I), 81 SRLI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.srl, Y, N, N, N, N, N, SelImm.IMM_I), 82 SRAI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sra, Y, N, N, N, N, N, SelImm.IMM_I), 83 84 ADDIW -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.addw, Y, N, N, N, N, N, SelImm.IMM_I), 85 SLLIW -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sllw, Y, N, N, N, N, N, SelImm.IMM_I), 86 SRAIW -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sraw, Y, N, N, N, N, N, SelImm.IMM_I), 87 SRLIW -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.srlw, Y, N, N, N, N, N, SelImm.IMM_I), 88 89 ADDW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.addw, Y, N, N, N, N, N, SelImm.X), 90 SUBW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.subw, Y, N, N, N, N, N, SelImm.X), 91 SLLW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sllw, Y, N, N, N, N, N, SelImm.X), 92 SRAW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sraw, Y, N, N, N, N, N, SelImm.X), 93 SRLW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.srlw, Y, N, N, N, N, N, SelImm.X), 94 95 RORW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.rorw, Y, N, N, N, N, N, SelImm.X), 96 RORIW -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.rorw, Y, N, N, N, N, N, SelImm.IMM_I), 97 ROLW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.rolw, Y, N, N, N, N, N, SelImm.X) 98 ) 99} 100 101/** 102 * Overall Decode constants 103 */ 104object XDecode extends DecodeConstants { 105 val table: Array[(BitPat, List[BitPat])] = Array( 106 LW -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lw, Y, N, N, N, N, N, SelImm.IMM_I), 107 LH -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lh, Y, N, N, N, N, N, SelImm.IMM_I), 108 LHU -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lhu, Y, N, N, N, N, N, SelImm.IMM_I), 109 LB -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lb, Y, N, N, N, N, N, SelImm.IMM_I), 110 LBU -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lbu, Y, N, N, N, N, N, SelImm.IMM_I), 111 112 SW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.sw, N, N, N, N, N, N, SelImm.IMM_S), 113 SH -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.sh, N, N, N, N, N, N, SelImm.IMM_S), 114 SB -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.sb, N, N, N, N, N, N, SelImm.IMM_S), 115 116 LUI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.add, Y, N, N, N, N, N, SelImm.IMM_U), 117 118 ADDI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.add, Y, N, N, N, N, N, SelImm.IMM_I), 119 ANDI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.and, Y, N, N, N, N, N, SelImm.IMM_I), 120 ORI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.or, Y, N, N, N, N, N, SelImm.IMM_I), 121 XORI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.xor, Y, N, N, N, N, N, SelImm.IMM_I), 122 SLTI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.slt, Y, N, N, N, N, N, SelImm.IMM_I), 123 SLTIU -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sltu, Y, N, N, N, N, N, SelImm.IMM_I), 124 125 SLL -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sll, Y, N, N, N, N, N, SelImm.X), 126 ADD -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.add, Y, N, N, N, N, N, SelImm.X), 127 SUB -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sub, Y, N, N, N, N, N, SelImm.X), 128 SLT -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.slt, Y, N, N, N, N, N, SelImm.X), 129 SLTU -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sltu, Y, N, N, N, N, N, SelImm.X), 130 AND -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.and, Y, N, N, N, N, N, SelImm.X), 131 OR -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.or, Y, N, N, N, N, N, SelImm.X), 132 XOR -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.xor, Y, N, N, N, N, N, SelImm.X), 133 SRA -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sra, Y, N, N, N, N, N, SelImm.X), 134 SRL -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.srl, Y, N, N, N, N, N, SelImm.X), 135 136 MUL -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mul, Y, N, N, N, N, N, SelImm.X), 137 MULH -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mulh, Y, N, N, N, N, N, SelImm.X), 138 MULHU -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mulhu, Y, N, N, N, N, N, SelImm.X), 139 MULHSU -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mulhsu, Y, N, N, N, N, N, SelImm.X), 140 MULW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mulw, Y, N, N, N, N, N, SelImm.X), 141 142 DIV -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.div, Y, N, N, N, N, N, SelImm.X), 143 DIVU -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.divu, Y, N, N, N, N, N, SelImm.X), 144 REM -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.rem, Y, N, N, N, N, N, SelImm.X), 145 REMU -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.remu, Y, N, N, N, N, N, SelImm.X), 146 DIVW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.divw, Y, N, N, N, N, N, SelImm.X), 147 DIVUW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.divuw, Y, N, N, N, N, N, SelImm.X), 148 REMW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.remw, Y, N, N, N, N, N, SelImm.X), 149 REMUW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.remuw, Y, N, N, N, N, N, SelImm.X), 150 151 AUIPC -> List(SrcType.pc , SrcType.imm, SrcType.X, FuType.jmp, JumpOpType.auipc, Y, N, N, N, N, N, SelImm.IMM_U), 152 JAL -> List(SrcType.pc , SrcType.imm, SrcType.X, FuType.jmp, JumpOpType.jal, Y, N, N, N, N, N, SelImm.IMM_UJ), 153 JALR -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.jmp, JumpOpType.jalr, Y, N, N, N, N, N, SelImm.IMM_I), 154 BEQ -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.beq, N, N, N, N, N, N, SelImm.IMM_SB), 155 BNE -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bne, N, N, N, N, N, N, SelImm.IMM_SB), 156 BGE -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bge, N, N, N, N, N, N, SelImm.IMM_SB), 157 BGEU -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bgeu, N, N, N, N, N, N, SelImm.IMM_SB), 158 BLT -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.blt, N, N, N, N, N, N, SelImm.IMM_SB), 159 BLTU -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bltu, N, N, N, N, N, N, SelImm.IMM_SB), 160 161 // I-type, the immediate12 holds the CSR register. 162 CSRRW -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.wrt, Y, N, N, Y, Y, N, SelImm.IMM_I), 163 CSRRS -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.set, Y, N, N, Y, Y, N, SelImm.IMM_I), 164 CSRRC -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.clr, Y, N, N, Y, Y, N, SelImm.IMM_I), 165 166 CSRRWI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.wrti, Y, N, N, Y, Y, N, SelImm.IMM_Z), 167 CSRRSI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.seti, Y, N, N, Y, Y, N, SelImm.IMM_Z), 168 CSRRCI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.clri, Y, N, N, Y, Y, N, SelImm.IMM_Z), 169 170 SFENCE_VMA->List(SrcType.reg, SrcType.reg, SrcType.X, FuType.fence, FenceOpType.sfence, N, N, N, Y, Y, Y, SelImm.X), 171 EBREAK -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, Y, N, N, Y, Y, N, SelImm.IMM_I), 172 ECALL -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, Y, N, N, Y, Y, N, SelImm.IMM_I), 173 SRET -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, Y, N, N, Y, Y, N, SelImm.IMM_I), 174 MRET -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, Y, N, N, Y, Y, N, SelImm.IMM_I), 175 DRET -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, Y, N, N, Y, Y, N, SelImm.IMM_I), 176 177 WFI -> List(SrcType.pc, SrcType.imm, SrcType.X, FuType.csr, CSROpType.wfi, Y, N, N, Y, Y, N, SelImm.X), 178 179 FENCE_I -> List(SrcType.pc, SrcType.imm, SrcType.X, FuType.fence, FenceOpType.fencei, N, N, N, Y, Y, Y, SelImm.X), 180 FENCE -> List(SrcType.pc, SrcType.imm, SrcType.X, FuType.fence, FenceOpType.fence, N, N, N, Y, Y, Y, SelImm.X), 181 182 // A-type 183 AMOADD_W-> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoadd_w, Y, N, N, Y, Y, N, SelImm.X), 184 AMOXOR_W-> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoxor_w, Y, N, N, Y, Y, N, SelImm.X), 185 AMOSWAP_W->List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoswap_w, Y, N, N, Y, Y, N, SelImm.X), 186 AMOAND_W-> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoand_w, Y, N, N, Y, Y, N, SelImm.X), 187 AMOOR_W -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoor_w, Y, N, N, Y, Y, N, SelImm.X), 188 AMOMIN_W-> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomin_w, Y, N, N, Y, Y, N, SelImm.X), 189 AMOMINU_W->List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amominu_w, Y, N, N, Y, Y, N, SelImm.X), 190 AMOMAX_W-> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomax_w, Y, N, N, Y, Y, N, SelImm.X), 191 AMOMAXU_W->List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomaxu_w, Y, N, N, Y, Y, N, SelImm.X), 192 193 AMOADD_D-> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoadd_d, Y, N, N, Y, Y, N, SelImm.X), 194 AMOXOR_D-> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoxor_d, Y, N, N, Y, Y, N, SelImm.X), 195 AMOSWAP_D->List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoswap_d, Y, N, N, Y, Y, N, SelImm.X), 196 AMOAND_D-> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoand_d, Y, N, N, Y, Y, N, SelImm.X), 197 AMOOR_D -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoor_d, Y, N, N, Y, Y, N, SelImm.X), 198 AMOMIN_D-> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomin_d, Y, N, N, Y, Y, N, SelImm.X), 199 AMOMINU_D->List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amominu_d, Y, N, N, Y, Y, N, SelImm.X), 200 AMOMAX_D-> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomax_d, Y, N, N, Y, Y, N, SelImm.X), 201 AMOMAXU_D->List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomaxu_d, Y, N, N, Y, Y, N, SelImm.X), 202 203 LR_W -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.mou, LSUOpType.lr_w, Y, N, N, Y, Y, N, SelImm.X), 204 LR_D -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.mou, LSUOpType.lr_d, Y, N, N, Y, Y, N, SelImm.X), 205 SC_W -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.sc_w, Y, N, N, Y, Y, N, SelImm.X), 206 SC_D -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.sc_d, Y, N, N, Y, Y, N, SelImm.X), 207 208 ANDN -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.andn, Y, N, N, N, N, N, SelImm.X), 209 ORN -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.orn, Y, N, N, N, N, N, SelImm.X), 210 XNOR -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.xnor, Y, N, N, N, N, N, SelImm.X), 211 ORC_B -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.orcb, Y, N, N, N, N, N, SelImm.X), 212 213 MIN -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.min, Y, N, N, N, N, N, SelImm.X), 214 MINU -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.minu, Y, N, N, N, N, N, SelImm.X), 215 MAX -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.max, Y, N, N, N, N, N, SelImm.X), 216 MAXU -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.maxu, Y, N, N, N, N, N, SelImm.X), 217 218 SEXT_B -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.sextb, Y, N, N, N, N, N, SelImm.X), 219 PACKH -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.packh, Y, N, N, N, N, N, SelImm.X), 220 SEXT_H -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.sexth, Y, N, N, N, N, N, SelImm.X), 221 PACKW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.packw, Y, N, N, N, N, N, SelImm.X), 222 BREV8 -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.revb, Y, N, N, N, N, N, SelImm.X), 223 REV8 -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.rev8, Y, N, N, N, N, N, SelImm.X), 224 PACK -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.pack, Y, N, N, N, N, N, SelImm.X), 225 226 BSET -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bset, Y, N, N, N, N, N, SelImm.X), 227 BSETI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.bset, Y, N, N, N, N, N, SelImm.IMM_I), 228 BCLR -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bclr, Y, N, N, N, N, N, SelImm.X), 229 BCLRI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.bclr, Y, N, N, N, N, N, SelImm.IMM_I), 230 BINV -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.binv, Y, N, N, N, N, N, SelImm.X), 231 BINVI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.binv, Y, N, N, N, N, N, SelImm.IMM_I), 232 BEXT -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bext, Y, N, N, N, N, N, SelImm.X), 233 BEXTI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.bext, Y, N, N, N, N, N, SelImm.IMM_I), 234 235 ROR -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.ror, Y, N, N, N, N, N, SelImm.X), 236 RORI -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.ror, Y, N, N, N, N, N, SelImm.IMM_I), 237 ROL -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.rol, Y, N, N, N, N, N, SelImm.X), 238 239 SH1ADD -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh1add, Y, N, N, N, N, N, SelImm.X), 240 SH2ADD -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh2add, Y, N, N, N, N, N, SelImm.X), 241 SH3ADD -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh3add, Y, N, N, N, N, N, SelImm.X), 242 SH1ADD_UW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh1adduw, Y, N, N, N, N, N, SelImm.X), 243 SH2ADD_UW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh2adduw, Y, N, N, N, N, N, SelImm.X), 244 SH3ADD_UW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh3adduw, Y, N, N, N, N, N, SelImm.X), 245 ADD_UW -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.adduw, Y, N, N, N, N, N, SelImm.X), 246 SLLI_UW -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.slliuw, Y, N, N, N, N, N, SelImm.IMM_I) 247 ) 248} 249 250/** 251 * FP Decode constants 252 */ 253object FDecode extends DecodeConstants{ 254 val table: Array[(BitPat, List[BitPat])] = Array( 255 256 FLW -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lw, N, Y, N, N, N, N, SelImm.IMM_I), 257 FLD -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.ld, N, Y, N, N, N, N, SelImm.IMM_I), 258 FSW -> List(SrcType.reg, SrcType.fp, SrcType.X, FuType.stu, LSUOpType.sw, N, N, N, N, N, N, SelImm.IMM_S), 259 FSD -> List(SrcType.reg, SrcType.fp, SrcType.X, FuType.stu, LSUOpType.sd, N, N, N, N, N, N, SelImm.IMM_S), 260 261 FCLASS_S-> List(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), 262 FCLASS_D-> List(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), 263 264 FMV_D_X -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 265 FMV_X_D -> List(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), 266 FMV_X_W -> List(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), 267 FMV_W_X -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 268 269 FSGNJ_S -> List(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 270 FSGNJ_D -> List(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 271 FSGNJX_S-> List(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 272 FSGNJX_D-> List(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 273 FSGNJN_S-> List(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 274 FSGNJN_D-> List(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 275 276 // FP to FP 277 FCVT_S_D-> List(SrcType.fp, SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 278 FCVT_D_S-> List(SrcType.fp, SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 279 280 // Int to FP 281 FCVT_S_W-> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 282 FCVT_S_WU->List(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 283 FCVT_S_L-> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 284 FCVT_S_LU->List(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 285 286 FCVT_D_W-> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 287 FCVT_D_WU->List(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 288 FCVT_D_L-> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 289 FCVT_D_LU->List(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 290 291 // FP to Int 292 FCVT_W_S-> List(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), 293 FCVT_WU_S->List(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), 294 FCVT_L_S-> List(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), 295 FCVT_LU_S->List(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), 296 297 FCVT_W_D-> List(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), 298 FCVT_WU_D->List(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), 299 FCVT_L_D-> List(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), 300 FCVT_LU_D->List(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), 301 302 // "fp_single" is used for wb_data formatting (and debugging) 303 FEQ_S ->List(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), 304 FLT_S ->List(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), 305 FLE_S ->List(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), 306 307 FEQ_D ->List(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), 308 FLT_D ->List(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), 309 FLE_D ->List(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, Y, N, N, N, N, N, SelImm.X), 310 311 FMIN_S ->List(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 312 FMAX_S ->List(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 313 FMIN_D ->List(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 314 FMAX_D ->List(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 315 316 FADD_S ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 317 FSUB_S ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 318 FMUL_S ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 319 FADD_D ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 320 FSUB_D ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 321 FMUL_D ->List(SrcType.fp, SrcType.fp, SrcType.DC, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 322 323 FMADD_S ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 324 FMSUB_S ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 325 FNMADD_S ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 326 FNMSUB_S ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 327 FMADD_D ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 328 FMSUB_D ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 329 FNMADD_D ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 330 FNMSUB_D ->List(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, N, Y, N, N, N, N, SelImm.X) 331 ) 332} 333 334/** 335 * Bit Manipulation Decode 336 */ 337object BDecode extends DecodeConstants{ 338 val table: Array[(BitPat, List[BitPat])] = Array( 339 // Basic bit manipulation 340 CLZ -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.clz, Y, N, N, N, N, N, SelImm.X), 341 CTZ -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.ctz, Y, N, N, N, N, N, SelImm.X), 342 CPOP -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.cpop, Y, N, N, N, N, N, SelImm.X), 343 XPERM8 -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.xpermb, Y, N, N, N, N, N, SelImm.X), 344 XPERM4 -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.xpermn, Y, N, N, N, N, N, SelImm.X), 345 346 CLZW -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.clzw, Y, N, N, N, N, N, SelImm.X), 347 CTZW -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.ctzw, Y, N, N, N, N, N, SelImm.X), 348 CPOPW -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.cpopw, Y, N, N, N, N, N, SelImm.X), 349 350 CLMUL -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.clmul, Y, N, N, N, N, N, SelImm.X), 351 CLMULH -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.clmulh, Y, N, N, N, N, N, SelImm.X), 352 CLMULR -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.clmulr, Y, N, N, N, N, N, SelImm.X), 353 354 AES64ES -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64es, Y, N, N, N, N, N, SelImm.X), 355 AES64ESM -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64esm, Y, N, N, N, N, N, SelImm.X), 356 AES64DS -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64ds, Y, N, N, N, N, N, SelImm.X), 357 AES64DSM -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64dsm, Y, N, N, N, N, N, SelImm.X), 358 AES64IM -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.aes64im, Y, N, N, N, N, N, SelImm.X), 359 AES64KS1I -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.bku, BKUOpType.aes64ks1i, Y, N, N, N, N, N, SelImm.IMM_I), 360 AES64KS2 -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64ks2, Y, N, N, N, N, N, SelImm.X), 361 SHA256SUM0 -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha256sum0, Y, N, N, N, N, N, SelImm.X), 362 SHA256SUM1 -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha256sum1, Y, N, N, N, N, N, SelImm.X), 363 SHA256SIG0 -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha256sig0, Y, N, N, N, N, N, SelImm.X), 364 SHA256SIG1 -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha256sig1, Y, N, N, N, N, N, SelImm.X), 365 SHA512SUM0 -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha512sum0, Y, N, N, N, N, N, SelImm.X), 366 SHA512SUM1 -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha512sum1, Y, N, N, N, N, N, SelImm.X), 367 SHA512SIG0 -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha512sig0, Y, N, N, N, N, N, SelImm.X), 368 SHA512SIG1 -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha512sig1, Y, N, N, N, N, N, SelImm.X), 369 SM3P0 -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sm3p0, Y, N, N, N, N, N, SelImm.X), 370 SM3P1 -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sm3p1, Y, N, N, N, N, N, SelImm.X), 371 SM4KS0 -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ks0, Y, N, N, N, N, N, SelImm.X), 372 SM4KS1 -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ks1, Y, N, N, N, N, N, SelImm.X), 373 SM4KS2 -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ks2, Y, N, N, N, N, N, SelImm.X), 374 SM4KS3 -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ks3, Y, N, N, N, N, N, SelImm.X), 375 SM4ED0 -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ed0, Y, N, N, N, N, N, SelImm.X), 376 SM4ED1 -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ed1, Y, N, N, N, N, N, SelImm.X), 377 SM4ED2 -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ed2, Y, N, N, N, N, N, SelImm.X), 378 SM4ED3 -> List(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ed3, Y, N, N, N, N, N, SelImm.X), 379 ) 380} 381 382/** 383 * FP Divide SquareRoot Constants 384 */ 385object FDivSqrtDecode extends DecodeConstants { 386 val table: Array[(BitPat, List[BitPat])] = Array( 387 FDIV_S ->List(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 388 FDIV_D ->List(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 389 FSQRT_S ->List(SrcType.fp, SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, SelImm.X), 390 FSQRT_D ->List(SrcType.fp, SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, N, Y, N, N, N, N, SelImm.X) 391 ) 392} 393 394/** 395 * Svinval extension Constants 396 */ 397object SvinvalDecode extends DecodeConstants { 398 val table: Array[(BitPat, List[BitPat])] = Array( 399 /* sinval_vma is like sfence.vma , but sinval_vma can be dispatched and issued like normal instructions while sfence.vma 400 * must assure it is the ONLY instrucion executing in backend. 401 */ 402 SINVAL_VMA ->List(SrcType.reg, SrcType.reg, SrcType.X, FuType.fence, FenceOpType.sfence, N, N, N, N, N, N, SelImm.X), 403 /* sfecne.w.inval is the begin instrucion of a TLB flush which set *noSpecExec* and *blockBackward* signals 404 * so when it comes to dispatch , it will block all instruction after itself until all instrucions ahead of it in rob commit 405 * then dispatch and issue this instrucion to flush sbuffer to dcache 406 * after this instrucion commits , issue following sinval_vma instructions (out of order) to flush TLB 407 */ 408 SFENCE_W_INVAL ->List(SrcType.DC, SrcType.DC, SrcType.X, FuType.fence, FenceOpType.nofence, N, N, N, Y, Y, N, SelImm.X), 409 /* sfecne.inval.ir is the end instrucion of a TLB flush which set *noSpecExec* *blockBackward* and *flushPipe* signals 410 * so when it comes to dispatch , it will wait until all sinval_vma ahead of it in rob commit 411 * then dispatch and issue this instrucion 412 * when it commit at the head of rob , flush the pipeline since some instrucions have been fetched to ibuffer using old TLB map 413 */ 414 SFENCE_INVAL_IR ->List(SrcType.DC, SrcType.DC, SrcType.X, FuType.fence, FenceOpType.nofence, N, N, N, Y, Y, Y, SelImm.X) 415 /* what is Svinval extension ? 416 * -----> sfecne.w.inval 417 * sfence.vma vpn1 -----> sinval_vma vpn1 418 * sfence.vma vpn2 -----> sinval_vma vpn2 419 * -----> sfecne.inval.ir 420 * 421 * sfence.vma should be executed in-order and it flushes the pipeline after committing 422 * we can parallel sfence instrucions with this extension 423 */ 424 ) 425} 426/* 427 * CBO decode 428 */ 429object CBODecode extends DecodeConstants { 430 val table: Array[(BitPat, List[BitPat])] = Array( 431 CBO_ZERO -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.stu, LSUOpType.cbo_zero , N, N, N, N, N, N, SelImm.IMM_S), 432 CBO_CLEAN -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.stu, LSUOpType.cbo_clean, N, N, N, N, N, N, SelImm.IMM_S), 433 CBO_FLUSH -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.stu, LSUOpType.cbo_flush, N, N, N, N, N, N, SelImm.IMM_S), 434 CBO_INVAL -> List(SrcType.reg, SrcType.DC, SrcType.X, FuType.stu, LSUOpType.cbo_inval, N, N, N, N, N, N, SelImm.IMM_S) 435 ) 436} 437 438/** 439 * XiangShan Trap Decode constants 440 */ 441object XSTrapDecode extends DecodeConstants { 442 def TRAP = BitPat("b000000000000?????000000001101011") 443 val table: Array[(BitPat, List[BitPat])] = Array( 444 TRAP -> List(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.add, Y, N, Y, Y, Y, N, SelImm.IMM_I) 445 ) 446} 447 448//object Imm32Gen { 449// def apply(sel: UInt, inst: UInt) = { 450// val sign = Mux(sel === SelImm.IMM_Z, 0.S, inst(31).asSInt) 451// val b30_20 = Mux(sel === SelImm.IMM_U, inst(30,20).asSInt, sign) 452// val b19_12 = Mux(sel =/= SelImm.IMM_U && sel =/= SelImm.IMM_UJ, sign, inst(19,12).asSInt) 453// val b11 = Mux(sel === SelImm.IMM_U || sel === SelImm.IMM_Z, 0.S, 454// Mux(sel === SelImm.IMM_UJ, inst(20).asSInt, 455// Mux(sel === SelImm.IMM_SB, inst(7).asSInt, sign))) 456// val b10_5 = Mux(sel === SelImm.IMM_U || sel === SelImm.IMM_Z, 0.U(1.W), inst(30,25)) 457// val b4_1 = Mux(sel === SelImm.IMM_U, 0.U(1.W), 458// Mux(sel === SelImm.IMM_S || sel === SelImm.IMM_SB, inst(11,8), 459// Mux(sel === SelImm.IMM_Z, inst(19,16), inst(24,21)))) 460// val b0 = Mux(sel === SelImm.IMM_S, inst(7), 461// Mux(sel === SelImm.IMM_I, inst(20), 462// Mux(sel === SelImm.IMM_Z, inst(15), 0.U(1.W)))) 463// 464// Cat(sign, b30_20, b19_12, b11, b10_5, b4_1, b0) 465// } 466//} 467 468abstract class Imm(val len: Int) extends Bundle { 469 def toImm32(minBits: UInt): UInt = do_toImm32(minBits(len - 1, 0)) 470 def do_toImm32(minBits: UInt): UInt 471 def minBitsFromInstr(instr: UInt): UInt 472} 473 474case class Imm_I() extends Imm(12) { 475 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits(len - 1, 0), 32) 476 477 override def minBitsFromInstr(instr: UInt): UInt = 478 Cat(instr(31, 20)) 479} 480 481case class Imm_S() extends Imm(12) { 482 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits, 32) 483 484 override def minBitsFromInstr(instr: UInt): UInt = 485 Cat(instr(31, 25), instr(11, 7)) 486} 487 488case class Imm_B() extends Imm(12) { 489 override def do_toImm32(minBits: UInt): UInt = SignExt(Cat(minBits, 0.U(1.W)), 32) 490 491 override def minBitsFromInstr(instr: UInt): UInt = 492 Cat(instr(31), instr(7), instr(30, 25), instr(11, 8)) 493} 494 495case class Imm_U() extends Imm(20){ 496 override def do_toImm32(minBits: UInt): UInt = Cat(minBits(len - 1, 0), 0.U(12.W)) 497 498 override def minBitsFromInstr(instr: UInt): UInt = { 499 instr(31, 12) 500 } 501} 502 503case class Imm_J() extends Imm(20){ 504 override def do_toImm32(minBits: UInt): UInt = SignExt(Cat(minBits, 0.U(1.W)), 32) 505 506 override def minBitsFromInstr(instr: UInt): UInt = { 507 Cat(instr(31), instr(19, 12), instr(20), instr(30, 25), instr(24, 21)) 508 } 509} 510 511case class Imm_Z() extends Imm(12 + 5){ 512 override def do_toImm32(minBits: UInt): UInt = minBits 513 514 override def minBitsFromInstr(instr: UInt): UInt = { 515 Cat(instr(19, 15), instr(31, 20)) 516 } 517} 518 519case class Imm_B6() extends Imm(6){ 520 override def do_toImm32(minBits: UInt): UInt = ZeroExt(minBits, 32) 521 522 override def minBitsFromInstr(instr: UInt): UInt = { 523 instr(25, 20) 524 } 525} 526 527object ImmUnion { 528 val I = Imm_I() 529 val S = Imm_S() 530 val B = Imm_B() 531 val U = Imm_U() 532 val J = Imm_J() 533 val Z = Imm_Z() 534 val B6 = Imm_B6() 535 val imms = Seq(I, S, B, U, J, Z, B6) 536 val maxLen = imms.maxBy(_.len).len 537 val immSelMap = Seq( 538 SelImm.IMM_I, 539 SelImm.IMM_S, 540 SelImm.IMM_SB, 541 SelImm.IMM_U, 542 SelImm.IMM_UJ, 543 SelImm.IMM_Z, 544 SelImm.IMM_B6 545 ).zip(imms) 546 println(s"ImmUnion max len: $maxLen") 547} 548 549case class Imm_LUI_LOAD() { 550 def immFromLuiLoad(lui_imm: UInt, load_imm: UInt): UInt = { 551 val loadImm = load_imm(Imm_I().len - 1, 0) 552 Cat(lui_imm(Imm_U().len - loadImm.getWidth - 1, 0), loadImm) 553 } 554 def getLuiImm(uop: MicroOp): UInt = { 555 val loadImmLen = Imm_I().len 556 val imm_u = Cat(uop.psrc(1), uop.psrc(0), uop.ctrl.imm(ImmUnion.maxLen - 1, loadImmLen)) 557 Imm_U().do_toImm32(imm_u) 558 } 559} 560 561/** 562 * IO bundle for the Decode unit 563 */ 564class DecodeUnitIO(implicit p: Parameters) extends XSBundle { 565 val enq = new Bundle { val ctrl_flow = Input(new CtrlFlow) } 566 val deq = new Bundle { val cf_ctrl = Output(new CfCtrl) } 567 val csrCtrl = Input(new CustomCSRCtrlIO) 568} 569 570/** 571 * Decode unit that takes in a single CtrlFlow and generates a CfCtrl. 572 */ 573class DecodeUnit(implicit p: Parameters) extends XSModule with DecodeUnitConstants { 574 val io = IO(new DecodeUnitIO) 575 576 val ctrl_flow = Wire(new CtrlFlow) // input with RVC Expanded 577 val cf_ctrl = Wire(new CfCtrl) 578 579 ctrl_flow := io.enq.ctrl_flow 580 581 val decode_table = XDecode.table ++ 582 FDecode.table ++ 583 FDivSqrtDecode.table ++ 584 X64Decode.table ++ 585 XSTrapDecode.table ++ 586 BDecode.table ++ 587 CBODecode.table ++ 588 SvinvalDecode.table 589 // assertion for LUI: only LUI should be assigned `selImm === SelImm.IMM_U && fuType === FuType.alu` 590 val luiMatch = (t: Seq[BitPat]) => t(3).value == FuType.alu.litValue && t.reverse.head.value == SelImm.IMM_U.litValue 591 val luiTable = decode_table.filter(t => luiMatch(t._2)).map(_._1).distinct 592 assert(luiTable.length == 1 && luiTable.head == LUI, "Conflicts: LUI is determined by FuType and SelImm in Dispatch") 593 594 // output 595 cf_ctrl.cf := ctrl_flow 596 val cs: CtrlSignals = Wire(new CtrlSignals()).decode(ctrl_flow.instr, decode_table) 597 cs.singleStep := false.B 598 cs.replayInst := false.B 599 cs.debug_globalID := DontCare 600 601 val fpDecoder = Module(new FPDecoder) 602 fpDecoder.io.instr := ctrl_flow.instr 603 cs.fpu := fpDecoder.io.fpCtrl 604 605 val isMove = BitPat("b000000000000_?????_000_?????_0010011") === ctrl_flow.instr 606 cs.isMove := isMove && ctrl_flow.instr(RD_MSB, RD_LSB) =/= 0.U 607 608 // read src1~3 location 609 cs.lsrc(0) := ctrl_flow.instr(RS1_MSB, RS1_LSB) 610 cs.lsrc(1) := ctrl_flow.instr(RS2_MSB, RS2_LSB) 611 cs.lsrc(2) := ctrl_flow.instr(RS3_MSB, RS3_LSB) 612 // read dest location 613 cs.ldest := ctrl_flow.instr(RD_MSB, RD_LSB) 614 615 // fill in exception vector 616 cf_ctrl.cf.exceptionVec := io.enq.ctrl_flow.exceptionVec 617 cf_ctrl.cf.exceptionVec(illegalInstr) := cs.selImm === SelImm.INVALID_INSTR 618 619 when (!io.csrCtrl.svinval_enable) { 620 val base_ii = cs.selImm === SelImm.INVALID_INSTR 621 val sinval = BitPat("b0001011_?????_?????_000_00000_1110011") === ctrl_flow.instr 622 val w_inval = BitPat("b0001100_00000_00000_000_00000_1110011") === ctrl_flow.instr 623 val inval_ir = BitPat("b0001100_00001_00000_000_00000_1110011") === ctrl_flow.instr 624 val svinval_ii = sinval || w_inval || inval_ir 625 cf_ctrl.cf.exceptionVec(illegalInstr) := base_ii || svinval_ii 626 cs.flushPipe := false.B 627 } 628 629 // fix frflags 630 // fflags zero csrrs rd csr 631 val isFrflags = BitPat("b000000000001_00000_010_?????_1110011") === ctrl_flow.instr 632 when (cs.fuType === FuType.csr && isFrflags) { 633 cs.blockBackward := false.B 634 } 635 636 cs.imm := LookupTree(cs.selImm, ImmUnion.immSelMap.map( 637 x => { 638 val minBits = x._2.minBitsFromInstr(ctrl_flow.instr) 639 require(minBits.getWidth == x._2.len) 640 x._1 -> minBits 641 } 642 )) 643 644 cf_ctrl.ctrl := cs 645 646 io.deq.cf_ctrl := cf_ctrl 647 648 //------------------------------------------------------------- 649 // Debug Info 650 XSDebug("in: instr=%x pc=%x excepVec=%b crossPageIPFFix=%d\n", 651 io.enq.ctrl_flow.instr, io.enq.ctrl_flow.pc, io.enq.ctrl_flow.exceptionVec.asUInt, 652 io.enq.ctrl_flow.crossPageIPFFix) 653 XSDebug("out: srcType(0)=%b srcType(1)=%b srcType(2)=%b lsrc(0)=%d lsrc(1)=%d lsrc(2)=%d ldest=%d fuType=%b fuOpType=%b\n", 654 io.deq.cf_ctrl.ctrl.srcType(0), io.deq.cf_ctrl.ctrl.srcType(1), io.deq.cf_ctrl.ctrl.srcType(2), 655 io.deq.cf_ctrl.ctrl.lsrc(0), io.deq.cf_ctrl.ctrl.lsrc(1), io.deq.cf_ctrl.ctrl.lsrc(2), 656 io.deq.cf_ctrl.ctrl.ldest, io.deq.cf_ctrl.ctrl.fuType, io.deq.cf_ctrl.ctrl.fuOpType) 657 XSDebug("out: rfWen=%d fpWen=%d isXSTrap=%d noSpecExec=%d isBlocked=%d flushPipe=%d imm=%x\n", 658 io.deq.cf_ctrl.ctrl.rfWen, io.deq.cf_ctrl.ctrl.fpWen, io.deq.cf_ctrl.ctrl.isXSTrap, 659 io.deq.cf_ctrl.ctrl.noSpecExec, io.deq.cf_ctrl.ctrl.blockBackward, io.deq.cf_ctrl.ctrl.flushPipe, 660 io.deq.cf_ctrl.ctrl.imm) 661 XSDebug("out: excepVec=%b\n", io.deq.cf_ctrl.cf.exceptionVec.asUInt) 662} 663