1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.CSRs 23import freechips.rocketchip.rocket.Instructions._ 24import freechips.rocketchip.rocket.CustomInstructions._ 25import freechips.rocketchip.util.uintToBitPat 26import utility._ 27import utils._ 28import xiangshan.ExceptionNO.{EX_II, breakPoint, illegalInstr, virtualInstr} 29import xiangshan._ 30import xiangshan.backend.fu.FuType 31import xiangshan.backend.Bundles.{DecodedInst, DynInst, StaticInst} 32import xiangshan.backend.decode.isa.PseudoInstructions 33import xiangshan.backend.decode.isa.bitfield.{InstVType, OPCODE5Bit, XSInstBitFields} 34import xiangshan.backend.fu.vector.Bundles.{VType, Vl} 35import xiangshan.backend.fu.wrapper.CSRToDecode 36import xiangshan.backend.decode.Zimop._ 37import yunsuan.{VfaluType, VfcvtType} 38 39/** 40 * Abstract trait giving defaults and other relevant values to different Decode constants/ 41 */ 42trait DecodeConstants { 43 // This X should be used only in 1-bit signal. Otherwise, use BitPat("b???") to align with the width of UInt. 44 def X = BitPat("b0") 45 def N = BitPat("b0") 46 def Y = BitPat("b1") 47 def T = true 48 def F = false 49 50 def decodeDefault: List[BitPat] = // illegal instruction 51 // srcType(0) srcType(1) srcType(2) fuType fuOpType rfWen 52 // | | | | | | fpWen 53 // | | | | | | | vecWen 54 // | | | | | | | | isXSTrap 55 // | | | | | | | | | noSpecExec 56 // | | | | | | | | | | blockBackward 57 // | | | | | | | | | | | flushPipe 58 // | | | | | | | | | | | | canRobCompress 59 // | | | | | | | | | | | | | uopSplitType 60 // | | | | | | | | | | | | | | selImm 61 List(SrcType.X, SrcType.X, SrcType.X, FuType.X, FuOpType.X, N, N, N, N, N, N, N, N, UopSplitType.X, SelImm.INVALID_INSTR) // Use SelImm to indicate invalid instr 62 63 val decodeArray: Array[(BitPat, XSDecodeBase)] 64 final def table: Array[(BitPat, List[BitPat])] = decodeArray.map(x => (x._1, x._2.generate())) 65} 66 67trait DecodeUnitConstants 68{ 69 // abstract out instruction decode magic numbers 70 val RD_MSB = 11 71 val RD_LSB = 7 72 val RS1_MSB = 19 73 val RS1_LSB = 15 74 val RS2_MSB = 24 75 val RS2_LSB = 20 76 val RS3_MSB = 31 77 val RS3_LSB = 27 78} 79 80/** 81 * Decoded control signals 82 * See xiangshan/package.scala, xiangshan/backend/package.scala, Bundle.scala 83 */ 84 85abstract class XSDecodeBase { 86 def X = BitPat("b?") 87 def N = BitPat("b0") 88 def Y = BitPat("b1") 89 def T = true 90 def F = false 91 def generate() : List[BitPat] 92} 93 94case class XSDecode( 95 src1: BitPat, src2: BitPat, src3: BitPat, 96 fu: FuType.OHType, fuOp: BitPat, selImm: BitPat, 97 uopSplitType: BitPat = UopSplitType.X, 98 xWen: Boolean = false, 99 fWen: Boolean = false, 100 vWen: Boolean = false, 101 mWen: Boolean = false, 102 xsTrap: Boolean = false, 103 noSpec: Boolean = false, 104 blockBack: Boolean = false, 105 flushPipe: Boolean = false, 106 canRobCompress: Boolean = false, 107) extends XSDecodeBase { 108 def generate() : List[BitPat] = { 109 List (src1, src2, src3, BitPat(fu.U(FuType.num.W)), fuOp, xWen.B, fWen.B, (vWen || mWen).B, xsTrap.B, noSpec.B, blockBack.B, flushPipe.B, canRobCompress.B, uopSplitType, selImm) 110 } 111} 112 113case class FDecode( 114 src1: BitPat, src2: BitPat, src3: BitPat, 115 fu: FuType.OHType, fuOp: BitPat, selImm: BitPat = SelImm.X, 116 uopSplitType: BitPat = UopSplitType.X, 117 xWen: Boolean = false, 118 fWen: Boolean = false, 119 vWen: Boolean = false, 120 mWen: Boolean = false, 121 xsTrap: Boolean = false, 122 noSpec: Boolean = false, 123 blockBack: Boolean = false, 124 flushPipe: Boolean = false, 125 canRobCompress: Boolean = false, 126) extends XSDecodeBase { 127 def generate() : List[BitPat] = { 128 XSDecode(src1, src2, src3, fu, fuOp, selImm, uopSplitType, xWen, fWen, vWen, mWen, xsTrap, noSpec, blockBack, flushPipe, canRobCompress).generate() 129 } 130} 131 132/** 133 * Overall Decode constants 134 */ 135object XDecode extends DecodeConstants { 136 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 137 // RV32I 138 LW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lw , SelImm.IMM_I, xWen = T), 139 LH -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lh , SelImm.IMM_I, xWen = T), 140 LHU -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lhu , SelImm.IMM_I, xWen = T), 141 LB -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lb , SelImm.IMM_I, xWen = T), 142 LBU -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lbu , SelImm.IMM_I, xWen = T), 143 SW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.sw , SelImm.IMM_S ), 144 SH -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.sh , SelImm.IMM_S ), 145 SB -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.sb , SelImm.IMM_S ), 146 LUI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.add , SelImm.IMM_U, xWen = T, canRobCompress = T), 147 ADDI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.add , SelImm.IMM_I, xWen = T, canRobCompress = T), 148 ANDI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.and , SelImm.IMM_I, xWen = T, canRobCompress = T), 149 ORI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.or , SelImm.IMM_I, xWen = T, canRobCompress = T), 150 XORI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.xor , SelImm.IMM_I, xWen = T, canRobCompress = T), 151 SLTI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.slt , SelImm.IMM_I, xWen = T, canRobCompress = T), 152 SLTIU -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sltu, SelImm.IMM_I, xWen = T, canRobCompress = T), 153 SLL -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sll , SelImm.X , xWen = T, canRobCompress = T), 154 ADD -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.add , SelImm.X , xWen = T, canRobCompress = T), 155 SUB -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sub , SelImm.X , xWen = T, canRobCompress = T), 156 SLT -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.slt , SelImm.X , xWen = T, canRobCompress = T), 157 SLTU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sltu, SelImm.X , xWen = T, canRobCompress = T), 158 AND -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.and , SelImm.X , xWen = T, canRobCompress = T), 159 OR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.or , SelImm.X , xWen = T, canRobCompress = T), 160 XOR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.xor , SelImm.X , xWen = T, canRobCompress = T), 161 SRA -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sra , SelImm.X , xWen = T, canRobCompress = T), 162 SRL -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.srl , SelImm.X , xWen = T, canRobCompress = T), 163 164 // RV64I （extend from RV32I) 165 LD -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.ld , SelImm.IMM_I, xWen = T), 166 LWU -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lwu , SelImm.IMM_I, xWen = T), 167 SD -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.sd , SelImm.IMM_S ), 168 169 SLLI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sll , SelImm.IMM_I, xWen = T, canRobCompress = T), 170 SRLI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.srl , SelImm.IMM_I, xWen = T, canRobCompress = T), 171 SRAI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sra , SelImm.IMM_I, xWen = T, canRobCompress = T), 172 173 ADDIW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.addw, SelImm.IMM_I, xWen = T, canRobCompress = T), 174 SLLIW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sllw, SelImm.IMM_I, xWen = T, canRobCompress = T), 175 SRAIW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sraw, SelImm.IMM_I, xWen = T, canRobCompress = T), 176 SRLIW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.srlw, SelImm.IMM_I, xWen = T, canRobCompress = T), 177 178 ADDW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.addw, SelImm.X , xWen = T, canRobCompress = T), 179 SUBW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.subw, SelImm.X , xWen = T, canRobCompress = T), 180 SLLW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sllw, SelImm.X , xWen = T, canRobCompress = T), 181 SRAW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sraw, SelImm.X , xWen = T, canRobCompress = T), 182 SRLW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.srlw, SelImm.X , xWen = T, canRobCompress = T), 183 184 // RV64M 185 MUL -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mul , SelImm.X, xWen = T, canRobCompress = T), 186 MULH -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mulh , SelImm.X, xWen = T, canRobCompress = T), 187 MULHU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mulhu , SelImm.X, xWen = T, canRobCompress = T), 188 MULHSU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mulhsu, SelImm.X, xWen = T, canRobCompress = T), 189 MULW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mulw , SelImm.X, xWen = T, canRobCompress = T), 190 191 DIV -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.div , SelImm.X, xWen = T, canRobCompress = T), 192 DIVU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.divu , SelImm.X, xWen = T, canRobCompress = T), 193 REM -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.rem , SelImm.X, xWen = T, canRobCompress = T), 194 REMU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.remu , SelImm.X, xWen = T, canRobCompress = T), 195 DIVW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.divw , SelImm.X, xWen = T, canRobCompress = T), 196 DIVUW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.divuw , SelImm.X, xWen = T, canRobCompress = T), 197 REMW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.remw , SelImm.X, xWen = T, canRobCompress = T), 198 REMUW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.remuw , SelImm.X, xWen = T, canRobCompress = T), 199 200 AUIPC -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.jmp, JumpOpType.auipc, SelImm.IMM_U , xWen = T), 201 JAL -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.jmp, JumpOpType.jal , SelImm.IMM_UJ, xWen = T), 202 JALR -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.jmp, JumpOpType.jalr , SelImm.IMM_I , xWen = T), 203 BEQ -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.brh, BRUOpType.beq , SelImm.IMM_SB ), 204 BNE -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.brh, BRUOpType.bne , SelImm.IMM_SB ), 205 BGE -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.brh, BRUOpType.bge , SelImm.IMM_SB ), 206 BGEU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.brh, BRUOpType.bgeu , SelImm.IMM_SB ), 207 BLT -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.brh, BRUOpType.blt , SelImm.IMM_SB ), 208 BLTU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.brh, BRUOpType.bltu , SelImm.IMM_SB ), 209 210 // System, the immediate12 holds the CSR register. 211 212 CSRRW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.wrt , SelImm.IMM_Z, xWen = T, noSpec = T, blockBack = T), 213 CSRRS -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.set , SelImm.IMM_Z, xWen = T, noSpec = T, blockBack = T), 214 CSRRC -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.clr , SelImm.IMM_Z, xWen = T, noSpec = T, blockBack = T), 215 216 CSRRWI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.wrti, SelImm.IMM_Z, xWen = T, noSpec = T, blockBack = T), 217 CSRRSI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.seti, SelImm.IMM_Z, xWen = T, noSpec = T, blockBack = T), 218 CSRRCI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.clri, SelImm.IMM_Z, xWen = T, noSpec = T, blockBack = T), 219 220 EBREAK -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 221 ECALL -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 222 SRET -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 223 MRET -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 224 MNRET -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 225 DRET -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 226 WFI -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.csr, CSROpType.wfi, SelImm.X , xWen = T, noSpec = T, blockBack = T), 227 228 SFENCE_VMA -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.fence, FenceOpType.sfence, SelImm.X, noSpec = T, blockBack = T, flushPipe = T), 229 FENCE_I -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.fence, FenceOpType.fencei, SelImm.X, noSpec = T, blockBack = T, flushPipe = T), 230 FENCE -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.fence, FenceOpType.fence , SelImm.X, noSpec = T, blockBack = T, flushPipe = T), 231 PAUSE -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.fence, FenceOpType.fence , SelImm.X, noSpec = T, blockBack = T, flushPipe = T), 232 233 // Zawrs 234 WRS_NTO -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.csr, CSROpType.wrs_nto, SelImm.X , noSpec = T, blockBack = T), 235 WRS_STO -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.csr, CSROpType.wrs_sto, SelImm.X , noSpec = T, blockBack = T), 236 237 // RV64A 238 AMOADD_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoadd_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 239 AMOXOR_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoxor_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 240 AMOSWAP_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoswap_w, SelImm.X, xWen = T, noSpec = T, blockBack = T), 241 AMOAND_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoand_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 242 AMOOR_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoor_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 243 AMOMIN_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomin_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 244 AMOMINU_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amominu_w, SelImm.X, xWen = T, noSpec = T, blockBack = T), 245 AMOMAX_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomax_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 246 AMOMAXU_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomaxu_w, SelImm.X, xWen = T, noSpec = T, blockBack = T), 247 AMOCAS_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amocas_w, SelImm.X, uopSplitType = UopSplitType.AMO_CAS_W, xWen = T, noSpec = T, blockBack = T), 248 249 AMOADD_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoadd_d , SelImm.X, xWen = T, noSpec = T, blockBack = T), 250 AMOXOR_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoxor_d , SelImm.X, xWen = T, noSpec = T, blockBack = T), 251 AMOSWAP_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoswap_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 252 AMOAND_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoand_d , SelImm.X, xWen = T, noSpec = T, blockBack = T), 253 AMOOR_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoor_d , SelImm.X, xWen = T, noSpec = T, blockBack = T), 254 AMOMIN_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomin_d , SelImm.X, xWen = T, noSpec = T, blockBack = T), 255 AMOMINU_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amominu_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 256 AMOMAX_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomax_d , SelImm.X, xWen = T, noSpec = T, blockBack = T), 257 AMOMAXU_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomaxu_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 258 AMOCAS_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amocas_d, SelImm.X, uopSplitType = UopSplitType.AMO_CAS_D, xWen = T, noSpec = T, blockBack = T), 259 260 AMOCAS_Q -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amocas_q, SelImm.X, uopSplitType = UopSplitType.AMO_CAS_Q, xWen = T, noSpec = T, blockBack = T), 261 262 LR_W -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.mou, LSUOpType.lr_w, SelImm.X, xWen = T, noSpec = T, blockBack = T), 263 LR_D -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.mou, LSUOpType.lr_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 264 SC_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.sc_w, SelImm.X, xWen = T, noSpec = T, blockBack = T), 265 SC_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.sc_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 266 ) 267} 268 269object BitmanipDecode extends DecodeConstants{ 270 /* 271 Note: Some Bitmanip instruction may have different OP code between rv32 and rv64. 272 Including pseudo instruction like zext.h, and different funct12 like rev8. 273 If some day we need to support change XLEN via CSR, we should care about this. 274 */ 275 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 276 // Zba 277 ADD_UW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.adduw , SelImm.X , xWen = T, canRobCompress = T), 278 SH1ADD -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh1add , SelImm.X , xWen = T, canRobCompress = T), 279 SH1ADD_UW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh1adduw, SelImm.X , xWen = T, canRobCompress = T), 280 SH2ADD -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh2add , SelImm.X , xWen = T, canRobCompress = T), 281 SH2ADD_UW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh2adduw, SelImm.X , xWen = T, canRobCompress = T), 282 SH3ADD -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh3add , SelImm.X , xWen = T, canRobCompress = T), 283 SH3ADD_UW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh3adduw, SelImm.X , xWen = T, canRobCompress = T), 284 SLLI_UW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.slliuw , SelImm.IMM_I, xWen = T, canRobCompress = T), 285 286 // Zbb 287 ANDN -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.andn , SelImm.X , xWen = T, canRobCompress = T), 288 ORN -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.orn , SelImm.X , xWen = T, canRobCompress = T), 289 XNOR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.xnor , SelImm.X , xWen = T, canRobCompress = T), 290 291 CLZ -> XSDecode(SrcType.reg, SrcType.DC , SrcType.X, FuType.bku, BKUOpType.clz , SelImm.X , xWen = T, canRobCompress = T), 292 CLZW -> XSDecode(SrcType.reg, SrcType.DC , SrcType.X, FuType.bku, BKUOpType.clzw , SelImm.X , xWen = T, canRobCompress = T), 293 CTZ -> XSDecode(SrcType.reg, SrcType.DC , SrcType.X, FuType.bku, BKUOpType.ctz , SelImm.X , xWen = T, canRobCompress = T), 294 CTZW -> XSDecode(SrcType.reg, SrcType.DC , SrcType.X, FuType.bku, BKUOpType.ctzw , SelImm.X , xWen = T, canRobCompress = T), 295 296 CPOP -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.cpop , SelImm.X , xWen = T, canRobCompress = T), 297 CPOPW -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.cpopw , SelImm.X , xWen = T, canRobCompress = T), 298 299 MAX -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.max , SelImm.X , xWen = T, canRobCompress = T), 300 MAXU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.maxu , SelImm.X , xWen = T, canRobCompress = T), 301 MIN -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.min , SelImm.X , xWen = T, canRobCompress = T), 302 MINU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.minu , SelImm.X , xWen = T, canRobCompress = T), 303 304 SEXT_B -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.sextb , SelImm.X , xWen = T, canRobCompress = T), 305 SEXT_H -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.sexth , SelImm.X , xWen = T, canRobCompress = T), 306 // zext.h in rv64 is shared with packw in Zbkb with rs2 = $0. 307 // If we configured to have no Zbkb, we should add zext.h here. 308 309 ROL -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.rol , SelImm.X , xWen = T, canRobCompress = T), 310 ROLW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.rolw , SelImm.X , xWen = T, canRobCompress = T), 311 ROR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.ror , SelImm.X , xWen = T, canRobCompress = T), 312 RORI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.ror , SelImm.IMM_I, xWen = T, canRobCompress = T), 313 RORIW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.rorw , SelImm.IMM_I, xWen = T, canRobCompress = T), 314 RORW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.rorw , SelImm.X , xWen = T, canRobCompress = T), 315 316 ORC_B -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.orcb , SelImm.X , xWen = T, canRobCompress = T), 317 318 REV8 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.rev8 , SelImm.X , xWen = T, canRobCompress = T), 319 320 // Zbc 321 CLMUL -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.clmul , SelImm.X , xWen = T, canRobCompress = T), 322 CLMULH -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.clmulh , SelImm.X , xWen = T, canRobCompress = T), 323 CLMULR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.clmulr , SelImm.X , xWen = T, canRobCompress = T), 324 325 // Zbs 326 BCLR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bclr , SelImm.X , xWen = T, canRobCompress = T), 327 BCLRI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.bclr , SelImm.IMM_I, xWen = T, canRobCompress = T), 328 BEXT -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bext , SelImm.X , xWen = T, canRobCompress = T), 329 BEXTI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.bext , SelImm.IMM_I, xWen = T, canRobCompress = T), 330 BINV -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.binv , SelImm.X , xWen = T, canRobCompress = T), 331 BINVI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.binv , SelImm.IMM_I, xWen = T, canRobCompress = T), 332 BSET -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bset , SelImm.X , xWen = T, canRobCompress = T), 333 BSETI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.bset , SelImm.IMM_I, xWen = T, canRobCompress = T), 334 335 // Zbkb 336 // rol, rolw, ror,rori, roriw, rorw, andn, orn, xnor, rev8 is in Zbb 337 PACK -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.pack , SelImm.X , xWen = T, canRobCompress = T), 338 PACKH -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.packh , SelImm.X , xWen = T, canRobCompress = T), 339 PACKW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.packw , SelImm.X , xWen = T, canRobCompress = T), 340 BREV8 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.revb , SelImm.X , xWen = T, canRobCompress = T), 341 // If configured to RV32, we should add zip and unzip. 342 343 // Zbkc 344 // clmul, clmulh is in Zbc 345 346 // Zbkx 347 XPERM4 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.xpermn , SelImm.X , xWen = T, canRobCompress = T), 348 XPERM8 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.xpermb , SelImm.X , xWen = T, canRobCompress = T), 349 ) 350} 351 352object ScalarCryptoDecode extends DecodeConstants { 353 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 354 // Zknd: NIST Suite: AES Decryption 355 AES64DS -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64ds , SelImm.X , xWen = T, canRobCompress = T), 356 AES64DSM -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64dsm , SelImm.X , xWen = T, canRobCompress = T), 357 AES64IM -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.aes64im , SelImm.X , xWen = T, canRobCompress = T), 358 AES64KS1I -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.bku, BKUOpType.aes64ks1i , SelImm.IMM_I, xWen = T, canRobCompress = T), 359 AES64KS2 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64ks2 , SelImm.X , xWen = T, canRobCompress = T), 360 361 // Zkne: NIST Suite: AES Encryption 362 // aes64ks1i, aes64ks2 is in Zknd 363 AES64ES -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64es , SelImm.X , xWen = T, canRobCompress = T), 364 AES64ESM -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64esm , SelImm.X , xWen = T, canRobCompress = T), 365 366 // Zknh: NIST Suite: Hash Function Instructions 367 SHA256SIG0 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha256sig0, SelImm.X , xWen = T, canRobCompress = T), 368 SHA256SIG1 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha256sig1, SelImm.X , xWen = T, canRobCompress = T), 369 SHA256SUM0 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha256sum0, SelImm.X , xWen = T, canRobCompress = T), 370 SHA256SUM1 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha256sum1, SelImm.X , xWen = T, canRobCompress = T), 371 SHA512SIG0 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha512sig0, SelImm.X , xWen = T, canRobCompress = T), 372 SHA512SIG1 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha512sig1, SelImm.X , xWen = T, canRobCompress = T), 373 SHA512SUM0 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha512sum0, SelImm.X , xWen = T, canRobCompress = T), 374 SHA512SUM1 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha512sum1, SelImm.X , xWen = T, canRobCompress = T), 375 376 // Zksed: ShangMi Suite: SM4 Block Cipher Instructions 377 SM4ED0 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ed0 , SelImm.X , xWen = T, canRobCompress = T), 378 SM4ED1 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ed1 , SelImm.X , xWen = T, canRobCompress = T), 379 SM4ED2 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ed2 , SelImm.X , xWen = T, canRobCompress = T), 380 SM4ED3 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ed3 , SelImm.X , xWen = T, canRobCompress = T), 381 SM4KS0 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ks0 , SelImm.X , xWen = T, canRobCompress = T), 382 SM4KS1 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ks1 , SelImm.X , xWen = T, canRobCompress = T), 383 SM4KS2 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ks2 , SelImm.X , xWen = T, canRobCompress = T), 384 SM4KS3 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ks3 , SelImm.X , xWen = T, canRobCompress = T), 385 386 // Zksh: ShangMi Suite: SM3 Hash Function Instructions 387 SM3P0 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sm3p0 , SelImm.X , xWen = T, canRobCompress = T), 388 SM3P1 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sm3p1 , SelImm.X , xWen = T, canRobCompress = T), 389 ) 390} 391 392/** 393 * FP Decode constants 394 */ 395object FpDecode extends DecodeConstants{ 396 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 397 FLH -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lh, selImm = SelImm.IMM_I, fWen = T), 398 FLW -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lw, selImm = SelImm.IMM_I, fWen = T), 399 FLD -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.ld, selImm = SelImm.IMM_I, fWen = T), 400 FSH -> FDecode(SrcType.reg, SrcType.fp, SrcType.X, FuType.stu, LSUOpType.sh, selImm = SelImm.IMM_S ), 401 FSW -> FDecode(SrcType.reg, SrcType.fp, SrcType.X, FuType.stu, LSUOpType.sw, selImm = SelImm.IMM_S ), 402 FSD -> FDecode(SrcType.reg, SrcType.fp, SrcType.X, FuType.stu, LSUOpType.sd, selImm = SelImm.IMM_S ), 403 404 FMV_D_X -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2v, IF2VectorType.FMX_D_X, fWen = T, canRobCompress = T), 405 FMV_W_X -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2v, IF2VectorType.FMX_W_X, fWen = T, canRobCompress = T), 406 FMV_H_X -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2v, IF2VectorType.FMX_H_X, fWen = T, canRobCompress = T), 407 408 // Int to FP 409 FCVT_S_W -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T, canRobCompress = T), 410 FCVT_S_WU -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T, canRobCompress = T), 411 FCVT_S_L -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T, canRobCompress = T), 412 FCVT_S_LU -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T, canRobCompress = T), 413 414 FCVT_D_W -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T, canRobCompress = T), 415 FCVT_D_WU -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T, canRobCompress = T), 416 FCVT_D_L -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T, canRobCompress = T), 417 FCVT_D_LU -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T, canRobCompress = T), 418 419 FCVT_H_W -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T, canRobCompress = T), 420 FCVT_H_WU -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T, canRobCompress = T), 421 FCVT_H_L -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T, canRobCompress = T), 422 FCVT_H_LU -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T, canRobCompress = T), 423 ) 424} 425 426/** 427 * FP Divide SquareRoot Constants 428 */ 429object FDivSqrtDecode extends DecodeConstants { 430 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 431 FDIV_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fDivSqrt, FuOpType.X, fWen = T, canRobCompress = T), 432 FDIV_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fDivSqrt, FuOpType.X, fWen = T, canRobCompress = T), 433 FSQRT_S -> FDecode(SrcType.fp, SrcType.imm, SrcType.X, FuType.fDivSqrt, FuOpType.X, fWen = T, canRobCompress = T), 434 FSQRT_D -> FDecode(SrcType.fp, SrcType.imm, SrcType.X, FuType.fDivSqrt, FuOpType.X, fWen = T, canRobCompress = T), 435 ) 436} 437 438/** 439 * Svinval extension Constants 440 */ 441object SvinvalDecode extends DecodeConstants { 442 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 443 /* sinval_vma is like sfence.vma , but sinval_vma can be dispatched and issued like normal instructions while sfence.vma 444 * must assure it is the ONLY instrucion executing in backend. 445 * Since software cannot promiss all sinval.vma between sfence.w.inval and sfence.inval.ir, we make sinval.vma wait 446 * forward. 447 */ 448 SINVAL_VMA -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.fence, FenceOpType.sfence, SelImm.X, noSpec = T, blockBack = T), 449 /* sfecne.w.inval is the begin instrucion of a TLB flush which set *noSpecExec* and *blockBackward* signals 450 * so when it comes to dispatch , it will block all instruction after itself until all instrucions ahead of it in rob commit 451 * then dispatch and issue this instrucion to flush sbuffer to dcache 452 * after this instrucion commits , issue following sinval_vma instructions (out of order) to flush TLB 453 */ 454 SFENCE_W_INVAL -> XSDecode(SrcType.DC, SrcType.DC, SrcType.X, FuType.fence, FenceOpType.nofence, SelImm.X, noSpec = T, blockBack = T), 455 /* sfecne.inval.ir is the end instrucion of a TLB flush which set *noSpecExec* *blockBackward* and *flushPipe* signals 456 * so when it comes to dispatch , it will wait until all sinval_vma ahead of it in rob commit 457 * then dispatch and issue this instrucion 458 * when it commit at the head of rob , flush the pipeline since some instrucions have been fetched to ibuffer using old TLB map 459 */ 460 SFENCE_INVAL_IR -> XSDecode(SrcType.DC, SrcType.DC, SrcType.X, FuType.fence, FenceOpType.nofence, SelImm.X, noSpec = T, blockBack = T, flushPipe = T) 461 /* what is Svinval extension ? 462 * -----> sfecne.w.inval 463 * sfence.vma vpn1 -----> sinval_vma vpn1 464 * sfence.vma vpn2 -----> sinval_vma vpn2 465 * -----> sfecne.inval.ir 466 * 467 * sfence.vma should be executed in-order and it flushes the pipeline after committing 468 * we can parallel sfence instrucions with this extension 469 */ 470 ) 471} 472 473/* 474 * CBO decode 475 */ 476object CBODecode extends DecodeConstants { 477 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 478 CBO_ZERO -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.stu, LSUOpType.cbo_zero , SelImm.IMM_S), 479 CBO_CLEAN -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.stu, LSUOpType.cbo_clean, SelImm.IMM_S), 480 CBO_FLUSH -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.stu, LSUOpType.cbo_flush, SelImm.IMM_S), 481 CBO_INVAL -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.stu, LSUOpType.cbo_inval, SelImm.IMM_S) 482 ) 483} 484 485/* 486 * Hypervisor decode 487 */ 488object HypervisorDecode extends DecodeConstants { 489 override val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 490 HFENCE_GVMA -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.fence, FenceOpType.hfence_g, SelImm.X, noSpec = T, blockBack = T, flushPipe = T), 491 HFENCE_VVMA -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.fence, FenceOpType.hfence_v, SelImm.X, noSpec = T, blockBack = T, flushPipe = T), 492 493 /** 494 * Since software cannot promiss all sinval.vma between sfence.w.inval and sfence.inval.ir, we make sinval.vma wait 495 * forward. 496 */ 497 HINVAL_GVMA -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.fence, FenceOpType.hfence_g, SelImm.X, noSpec = T, blockBack = T), 498 HINVAL_VVMA -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.fence, FenceOpType.hfence_v, SelImm.X, noSpec = T, blockBack = T), 499 HLV_B -> XSDecode(SrcType.reg, SrcType.X, SrcType.X, FuType.ldu, LSUOpType.hlvb, SelImm.X, xWen = T), 500 HLV_BU -> XSDecode(SrcType.reg, SrcType.X, SrcType.X, FuType.ldu, LSUOpType.hlvbu, SelImm.X, xWen = T), 501 HLV_D -> XSDecode(SrcType.reg, SrcType.X, SrcType.X, FuType.ldu, LSUOpType.hlvd, SelImm.X, xWen = T), 502 HLV_H -> XSDecode(SrcType.reg, SrcType.X, SrcType.X, FuType.ldu, LSUOpType.hlvh, SelImm.X, xWen = T), 503 HLV_HU -> XSDecode(SrcType.reg, SrcType.X, SrcType.X, FuType.ldu, LSUOpType.hlvhu, SelImm.X, xWen = T), 504 HLV_W -> XSDecode(SrcType.reg, SrcType.X, SrcType.X, FuType.ldu, LSUOpType.hlvw, SelImm.X, xWen = T), 505 HLV_WU -> XSDecode(SrcType.reg, SrcType.X, SrcType.X, FuType.ldu, LSUOpType.hlvwu, SelImm.X, xWen = T), 506 HLVX_HU -> XSDecode(SrcType.reg, SrcType.X, SrcType.X, FuType.ldu, LSUOpType.hlvxhu, SelImm.X, xWen = T), 507 HLVX_WU -> XSDecode(SrcType.reg, SrcType.X, SrcType.X, FuType.ldu, LSUOpType.hlvxwu, SelImm.X, xWen = T), 508 HSV_B -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.hsvb, SelImm.X), 509 HSV_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.hsvd, SelImm.X), 510 HSV_H -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.hsvh, SelImm.X), 511 HSV_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.hsvw, SelImm.X), 512 ) 513} 514 515object ZicondDecode extends DecodeConstants { 516 override val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 517 CZERO_EQZ -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.czero_eqz, SelImm.X, xWen = T, canRobCompress = T), 518 CZERO_NEZ -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.czero_nez, SelImm.X, xWen = T, canRobCompress = T), 519 ) 520} 521 522/** 523 * "Zimop" Extension for May-Be-Operations 524 */ 525object ZimopDecode extends DecodeConstants { 526 override val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 527 // temp use addi to decode MOP_R and MOP_RR 528 MOP_R -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.add, SelImm.IMM_I, xWen = T, canRobCompress = T), 529 MOP_RR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.add, SelImm.IMM_I, xWen = T, canRobCompress = T), 530 ) 531} 532 533object ZfaDecode extends DecodeConstants { 534 override val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 535 FLI_H -> FDecode(SrcType.no, SrcType.X, SrcType.X, FuType.f2v, FuOpType.X, fWen = T, canRobCompress = T), 536 FLI_S -> FDecode(SrcType.no, SrcType.X, SrcType.X, FuType.f2v, FuOpType.X, fWen = T, canRobCompress = T), 537 FLI_D -> FDecode(SrcType.no, SrcType.X, SrcType.X, FuType.f2v, FuOpType.X, fWen = T, canRobCompress = T), 538 FMINM_H -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.falu, VfaluType.fminm, fWen = T, canRobCompress = T), 539 FMINM_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.falu, VfaluType.fminm, fWen = T, canRobCompress = T), 540 FMINM_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.falu, VfaluType.fminm, fWen = T, canRobCompress = T), 541 FMAXM_H -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.falu, VfaluType.fmaxm, fWen = T, canRobCompress = T), 542 FMAXM_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.falu, VfaluType.fmaxm, fWen = T, canRobCompress = T), 543 FMAXM_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.falu, VfaluType.fmaxm, fWen = T, canRobCompress = T), 544 FROUND_H -> FDecode(SrcType.fp, SrcType.X, SrcType.X, FuType.fcvt, VfcvtType.fround, fWen = T, canRobCompress = T), 545 FROUND_S -> FDecode(SrcType.fp, SrcType.X, SrcType.X, FuType.fcvt, VfcvtType.fround, fWen = T, canRobCompress = T), 546 FROUND_D -> FDecode(SrcType.fp, SrcType.X, SrcType.X, FuType.fcvt, VfcvtType.fround, fWen = T, canRobCompress = T), 547 FROUNDNX_H -> FDecode(SrcType.fp, SrcType.X, SrcType.X, FuType.fcvt, VfcvtType.froundnx, fWen = T, canRobCompress = T), 548 FROUNDNX_S -> FDecode(SrcType.fp, SrcType.X, SrcType.X, FuType.fcvt, VfcvtType.froundnx, fWen = T, canRobCompress = T), 549 FROUNDNX_D -> FDecode(SrcType.fp, SrcType.X, SrcType.X, FuType.fcvt, VfcvtType.froundnx, fWen = T, canRobCompress = T), 550 FCVTMOD_W_D -> FDecode(SrcType.fp, SrcType.X, SrcType.X, FuType.fcvt, VfcvtType.fcvtmod_w_d, xWen = T, canRobCompress = T), 551 FLEQ_H -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.falu, VfaluType.fleq, xWen = T, canRobCompress = T), 552 FLEQ_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.falu, VfaluType.fleq, xWen = T, canRobCompress = T), 553 FLEQ_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.falu, VfaluType.fleq, xWen = T, canRobCompress = T), 554 FLTQ_H -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.falu, VfaluType.fltq, xWen = T, canRobCompress = T), 555 FLTQ_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.falu, VfaluType.fltq, xWen = T, canRobCompress = T), 556 FLTQ_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.falu, VfaluType.fltq, xWen = T, canRobCompress = T), 557 ) 558} 559 560/** 561 * XiangShan Trap Decode constants 562 */ 563object XSTrapDecode extends DecodeConstants { 564 def TRAP = BitPat("b000000000000?????000000001101011") 565 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 566 TRAP -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.add, SelImm.IMM_I, xWen = T, xsTrap = T, noSpec = T, blockBack = T) 567 ) 568} 569 570abstract class Imm(val len: Int) { 571 def toImm32(minBits: UInt): UInt = do_toImm32(minBits(len - 1, 0)) 572 def do_toImm32(minBits: UInt): UInt 573 def minBitsFromInstr(instr: UInt): UInt 574} 575 576case class Imm_I() extends Imm(12) { 577 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits(len - 1, 0), 32) 578 579 override def minBitsFromInstr(instr: UInt): UInt = 580 Cat(instr(31, 20)) 581} 582 583case class Imm_S() extends Imm(12) { 584 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits, 32) 585 586 override def minBitsFromInstr(instr: UInt): UInt = 587 Cat(instr(31, 25), instr(11, 7)) 588} 589 590case class Imm_B() extends Imm(12) { 591 override def do_toImm32(minBits: UInt): UInt = SignExt(Cat(minBits, 0.U(1.W)), 32) 592 593 override def minBitsFromInstr(instr: UInt): UInt = 594 Cat(instr(31), instr(7), instr(30, 25), instr(11, 8)) 595} 596 597case class Imm_U() extends Imm(20){ 598 override def do_toImm32(minBits: UInt): UInt = Cat(minBits(len - 1, 0), 0.U(12.W)) 599 600 override def minBitsFromInstr(instr: UInt): UInt = { 601 instr(31, 12) 602 } 603} 604 605case class Imm_J() extends Imm(20){ 606 override def do_toImm32(minBits: UInt): UInt = SignExt(Cat(minBits, 0.U(1.W)), 32) 607 608 override def minBitsFromInstr(instr: UInt): UInt = { 609 Cat(instr(31), instr(19, 12), instr(20), instr(30, 25), instr(24, 21)) 610 } 611} 612 613case class Imm_Z() extends Imm(12 + 5 + 5){ 614 override def do_toImm32(minBits: UInt): UInt = minBits 615 616 override def minBitsFromInstr(instr: UInt): UInt = { 617 Cat(instr(11, 7), instr(19, 15), instr(31, 20)) 618 } 619 620 def getCSRAddr(imm: UInt): UInt = { 621 require(imm.getWidth == this.len) 622 imm(11, 0) 623 } 624 625 def getRS1(imm: UInt): UInt = { 626 require(imm.getWidth == this.len) 627 imm(16, 12) 628 } 629 630 def getRD(imm: UInt): UInt = { 631 require(imm.getWidth == this.len) 632 imm(21, 17) 633 } 634 635 def getImm5(imm: UInt): UInt = { 636 require(imm.getWidth == this.len) 637 imm(16, 12) 638 } 639} 640 641case class Imm_B6() extends Imm(6){ 642 override def do_toImm32(minBits: UInt): UInt = ZeroExt(minBits, 32) 643 644 override def minBitsFromInstr(instr: UInt): UInt = { 645 instr(25, 20) 646 } 647} 648 649case class Imm_OPIVIS() extends Imm(5){ 650 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits, 32) 651 652 override def minBitsFromInstr(instr: UInt): UInt = { 653 instr(19, 15) 654 } 655} 656 657case class Imm_OPIVIU() extends Imm(5){ 658 override def do_toImm32(minBits: UInt): UInt = ZeroExt(minBits, 32) 659 660 override def minBitsFromInstr(instr: UInt): UInt = { 661 instr(19, 15) 662 } 663} 664 665case class Imm_VSETVLI() extends Imm(11){ 666 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits, 32) 667 668 override def minBitsFromInstr(instr: UInt): UInt = { 669 instr(30, 20) 670 } 671 /** 672 * get VType from extended imm 673 * @param extedImm 674 * @return VType 675 */ 676 def getVType(extedImm: UInt): InstVType = { 677 val vtype = Wire(new InstVType) 678 vtype := extedImm(10, 0).asTypeOf(new InstVType) 679 vtype 680 } 681} 682 683case class Imm_VSETIVLI() extends Imm(15){ 684 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits, 32) 685 686 override def minBitsFromInstr(instr: UInt): UInt = { 687 val rvInst: XSInstBitFields = instr.asTypeOf(new XSInstBitFields) 688 val uimm5 = rvInst.UIMM_VSETIVLI 689 val vtype8 = rvInst.ZIMM_VSETIVLI 690 Cat(uimm5, vtype8) 691 } 692 /** 693 * get VType from extended imm 694 * @param extedImm 695 * @return VType 696 */ 697 def getVType(extedImm: UInt): InstVType = { 698 val vtype = Wire(new InstVType) 699 vtype := extedImm(9, 0).asTypeOf(new InstVType) 700 vtype 701 } 702 703 def getAvl(extedImm: UInt): UInt = { 704 extedImm(14, 10) 705 } 706} 707 708case class Imm_LUI32() extends Imm(32){ 709 override def do_toImm32(minBits: UInt): UInt = minBits(31, 0) 710 711 override def minBitsFromInstr(instr: UInt): UInt = { 712 instr(31, 0) 713 } 714} 715 716case class Imm_VRORVI() extends Imm(6){ 717 override def do_toImm32(minBits: UInt): UInt = ZeroExt(minBits, 32) 718 719 override def minBitsFromInstr(instr: UInt): UInt = { 720 Cat(instr(26), instr(19, 15)) 721 } 722} 723 724object ImmUnion { 725 val I = Imm_I() 726 val S = Imm_S() 727 val B = Imm_B() 728 val U = Imm_U() 729 val J = Imm_J() 730 val Z = Imm_Z() 731 val B6 = Imm_B6() 732 val OPIVIS = Imm_OPIVIS() 733 val OPIVIU = Imm_OPIVIU() 734 val VSETVLI = Imm_VSETVLI() 735 val VSETIVLI = Imm_VSETIVLI() 736 val LUI32 = Imm_LUI32() 737 val VRORVI = Imm_VRORVI() 738 739 // do not add special type lui32 to this, keep ImmUnion max len being 20. 740 val imms = Seq(I, S, B, U, J, Z, B6, OPIVIS, OPIVIU, VSETVLI, VSETIVLI, VRORVI) 741 val maxLen = imms.maxBy(_.len).len 742 val immSelMap = Seq( 743 SelImm.IMM_I, 744 SelImm.IMM_S, 745 SelImm.IMM_SB, 746 SelImm.IMM_U, 747 SelImm.IMM_UJ, 748 SelImm.IMM_Z, 749 SelImm.IMM_B6, 750 SelImm.IMM_OPIVIS, 751 SelImm.IMM_OPIVIU, 752 SelImm.IMM_VSETVLI, 753 SelImm.IMM_VSETIVLI, 754 SelImm.IMM_VRORVI, 755 ).zip(imms) 756 println(s"ImmUnion max len: $maxLen") 757} 758 759case class Imm_LUI_LOAD() { 760 def immFromLuiLoad(lui_imm: UInt, load_imm: UInt): UInt = { 761 val loadImm = load_imm(Imm_I().len - 1, 0) 762 Cat(lui_imm(ImmUnion.maxLen - loadImm.getWidth - 1, 0), loadImm) 763 } 764 def getLuiImm(uop: DynInst): UInt = { 765 val loadImmLen = Imm_I().len 766 val imm_u = Cat(uop.psrc(1), uop.psrc(0), uop.imm(ImmUnion.maxLen - 1, loadImmLen)) 767 Cat(Imm_U().toImm32(imm_u)(31, loadImmLen), uop.imm(loadImmLen - 1, 0)) 768 } 769} 770 771/** 772 * IO bundle for the Decode unit 773 */ 774 775class DecodeUnitEnqIO(implicit p: Parameters) extends XSBundle { 776 val ctrlFlow = Input(new StaticInst) 777 val vtype = Input(new VType) 778 val vstart = Input(Vl()) 779} 780 781class DecodeUnitDeqIO(implicit p: Parameters) extends XSBundle { 782 val decodedInst = Output(new DecodedInst) 783 val isComplex = Output(Bool()) 784 val uopInfo = Output(new UopInfo) 785} 786 787class DecodeUnitIO(implicit p: Parameters) extends XSBundle { 788 val enq = new DecodeUnitEnqIO 789 // val vconfig = Input(UInt(XLEN.W)) 790 val deq = new DecodeUnitDeqIO 791 val csrCtrl = Input(new CustomCSRCtrlIO) 792 val fromCSR = Input(new CSRToDecode) 793} 794 795/** 796 * Decode unit that takes in a single CtrlFlow and generates a CfCtrl. 797 */ 798class DecodeUnit(implicit p: Parameters) extends XSModule with DecodeUnitConstants { 799 val io = IO(new DecodeUnitIO) 800 801 val ctrl_flow = io.enq.ctrlFlow // input with RVC Expanded 802 803 private val inst: XSInstBitFields = io.enq.ctrlFlow.instr.asTypeOf(new XSInstBitFields) 804 805 val decode_table: Array[(BitPat, List[BitPat])] = XDecode.table ++ 806 FpDecode.table ++ 807// FDivSqrtDecode.table ++ 808 BitmanipDecode.table ++ 809 ScalarCryptoDecode.table ++ 810 XSTrapDecode.table ++ 811 CBODecode.table ++ 812 SvinvalDecode.table ++ 813 HypervisorDecode.table ++ 814 VecDecoder.table ++ 815 ZicondDecode.table ++ 816 ZimopDecode.table ++ 817 ZfaDecode.table 818 819 require(decode_table.map(_._2.length == 15).reduce(_ && _), "Decode tables have different column size") 820 // assertion for LUI: only LUI should be assigned `selImm === SelImm.IMM_U && fuType === FuType.alu` 821 val luiMatch = (t: Seq[BitPat]) => t(3).value == FuType.alu.ohid && t.reverse.head.value == SelImm.IMM_U.litValue 822 val luiTable = decode_table.filter(t => luiMatch(t._2)).map(_._1).distinct 823 assert(luiTable.length == 1 && luiTable.head == LUI, "Conflicts: LUI is determined by FuType and SelImm in Dispatch") 824 825 // output 826 val decodedInst: DecodedInst = Wire(new DecodedInst()).decode(ctrl_flow.instr, decode_table) 827 828 val fpDecoder = Module(new FPDecoder) 829 fpDecoder.io.instr := ctrl_flow.instr 830 decodedInst.fpu := fpDecoder.io.fpCtrl 831 decodedInst.fpu.wflags := fpDecoder.io.fpCtrl.wflags || decodedInst.wfflags 832 833 decodedInst.connectStaticInst(io.enq.ctrlFlow) 834 835 decodedInst.uopIdx := 0.U 836 decodedInst.firstUop := true.B 837 decodedInst.lastUop := true.B 838 decodedInst.numUops := 1.U 839 decodedInst.numWB := 1.U 840 841 val isZimop = (BitPat("b1?00??0111??_?????_100_?????_1110011") === ctrl_flow.instr) || 842 (BitPat("b1?00??1?????_?????_100_?????_1110011") === ctrl_flow.instr) 843 844 val isMove = BitPat("b000000000000_?????_000_?????_0010011") === ctrl_flow.instr 845 // temp decode zimop as move 846 decodedInst.isMove := (isMove || isZimop) && ctrl_flow.instr(RD_MSB, RD_LSB) =/= 0.U && !io.csrCtrl.singlestep 847 848 // fmadd - b1000011 849 // fmsub - b1000111 850 // fnmsub- b1001011 851 // fnmadd- b1001111 852 private val isFMA = inst.OPCODE === BitPat("b100??11") 853 private val isVppu = FuType.isVppu(decodedInst.fuType) 854 private val isVecOPF = FuType.isVecOPF(decodedInst.fuType) 855 856 // read src1~3 location 857 decodedInst.lsrc(0) := inst.RS1 858 decodedInst.lsrc(1) := inst.RS2 859 // src(2) of fma is fs3, src(2) of vector inst is old vd 860 decodedInst.lsrc(2) := Mux(isFMA, inst.FS3, inst.VD) 861 decodedInst.lsrc(3) := V0_IDX.U 862 decodedInst.lsrc(4) := Vl_IDX.U 863 864 // read dest location 865 decodedInst.ldest := inst.RD 866 867 // init v0Wen vlWen 868 decodedInst.v0Wen := false.B 869 decodedInst.vlWen := false.B 870 871 private val isCboClean = CBO_CLEAN === io.enq.ctrlFlow.instr 872 private val isCboFlush = CBO_FLUSH === io.enq.ctrlFlow.instr 873 private val isCboInval = CBO_INVAL === io.enq.ctrlFlow.instr 874 private val isCboZero = CBO_ZERO === io.enq.ctrlFlow.instr 875 876 // Note that rnum of aes64ks1i must be in the range 0x0..0xA. The values 0xB..0xF are reserved. 877 private val isAes64ks1iIllegal = 878 FuType.FuTypeOrR(decodedInst.fuType, FuType.bku) && (decodedInst.fuOpType === BKUOpType.aes64ks1i) && inst.isRnumIllegal 879 880 private val isAmocasQ = FuType.FuTypeOrR(decodedInst.fuType, FuType.mou) && decodedInst.fuOpType === LSUOpType.amocas_q 881 private val isAmocasQIllegal = isAmocasQ && (inst.RD(0) === 1.U || inst.RS2(0) === 1.U) 882 883 private val exceptionII = 884 decodedInst.selImm === SelImm.INVALID_INSTR || 885 io.fromCSR.illegalInst.sfenceVMA && FuType.FuTypeOrR(decodedInst.fuType, FuType.fence) && decodedInst.fuOpType === FenceOpType.sfence || 886 io.fromCSR.illegalInst.sfencePart && FuType.FuTypeOrR(decodedInst.fuType, FuType.fence) && decodedInst.fuOpType === FenceOpType.nofence || 887 io.fromCSR.illegalInst.hfenceGVMA && FuType.FuTypeOrR(decodedInst.fuType, FuType.fence) && decodedInst.fuOpType === FenceOpType.hfence_g || 888 io.fromCSR.illegalInst.hfenceVVMA && FuType.FuTypeOrR(decodedInst.fuType, FuType.fence) && decodedInst.fuOpType === FenceOpType.hfence_v || 889 io.fromCSR.illegalInst.hlsv && FuType.FuTypeOrR(decodedInst.fuType, FuType.ldu) && (LSUOpType.isHlv(decodedInst.fuOpType) || LSUOpType.isHlvx(decodedInst.fuOpType)) || 890 io.fromCSR.illegalInst.hlsv && FuType.FuTypeOrR(decodedInst.fuType, FuType.stu) && LSUOpType.isHsv(decodedInst.fuOpType) || 891 io.fromCSR.illegalInst.fsIsOff && ( 892 FuType.FuTypeOrR(decodedInst.fuType, FuType.fpOP ++ Seq(FuType.f2v)) || 893 (FuType.FuTypeOrR(decodedInst.fuType, FuType.ldu) && (decodedInst.fuOpType === LSUOpType.lh || decodedInst.fuOpType === LSUOpType.lw || decodedInst.fuOpType === LSUOpType.ld) || 894 FuType.FuTypeOrR(decodedInst.fuType, FuType.stu) && (decodedInst.fuOpType === LSUOpType.sh || decodedInst.fuOpType === LSUOpType.sw || decodedInst.fuOpType === LSUOpType.sd)) && decodedInst.instr(2) || 895 inst.isOPFVF || inst.isOPFVV 896 ) || 897 io.fromCSR.illegalInst.vsIsOff && FuType.FuTypeOrR(decodedInst.fuType, FuType.vecAll) || 898 io.fromCSR.illegalInst.wfi && FuType.FuTypeOrR(decodedInst.fuType, FuType.csr) && CSROpType.isWfi(decodedInst.fuOpType) || 899 io.fromCSR.illegalInst.wrs_nto && FuType.FuTypeOrR(decodedInst.fuType, FuType.csr) && CSROpType.isWrsNto(decodedInst.fuOpType) || 900 (decodedInst.needFrm.scalaNeedFrm || FuType.isScalaNeedFrm(decodedInst.fuType)) && (((decodedInst.fpu.rm === 5.U) || (decodedInst.fpu.rm === 6.U)) || ((decodedInst.fpu.rm === 7.U) && io.fromCSR.illegalInst.frm)) || 901 (decodedInst.needFrm.vectorNeedFrm || FuType.isVectorNeedFrm(decodedInst.fuType)) && io.fromCSR.illegalInst.frm || 902 (io.fromCSR.illegalInst.cboZ || !HasCMO.B) && isCboZero || 903 (io.fromCSR.illegalInst.cboCF || !HasCMO.B) && (isCboClean || isCboFlush) || 904 (io.fromCSR.illegalInst.cboI || !HasCMO.B) && isCboInval || 905 isAes64ks1iIllegal || 906 isAmocasQIllegal 907 908 private val exceptionVI = 909 io.fromCSR.virtualInst.sfenceVMA && FuType.FuTypeOrR(decodedInst.fuType, FuType.fence) && decodedInst.fuOpType === FenceOpType.sfence || 910 io.fromCSR.virtualInst.sfencePart && FuType.FuTypeOrR(decodedInst.fuType, FuType.fence) && decodedInst.fuOpType === FenceOpType.nofence || 911 io.fromCSR.virtualInst.hfence && FuType.FuTypeOrR(decodedInst.fuType, FuType.fence) && (decodedInst.fuOpType === FenceOpType.hfence_g || decodedInst.fuOpType === FenceOpType.hfence_v) || 912 io.fromCSR.virtualInst.hlsv && FuType.FuTypeOrR(decodedInst.fuType, FuType.ldu) && (LSUOpType.isHlv(decodedInst.fuOpType) || LSUOpType.isHlvx(decodedInst.fuOpType)) || 913 io.fromCSR.virtualInst.hlsv && FuType.FuTypeOrR(decodedInst.fuType, FuType.stu) && LSUOpType.isHsv(decodedInst.fuOpType) || 914 io.fromCSR.virtualInst.wfi && FuType.FuTypeOrR(decodedInst.fuType, FuType.csr) && CSROpType.isWfi(decodedInst.fuOpType) || 915 io.fromCSR.virtualInst.wrs_nto && FuType.FuTypeOrR(decodedInst.fuType, FuType.csr) && CSROpType.isWrsNto(decodedInst.fuOpType) || 916 io.fromCSR.virtualInst.cboZ && isCboZero || 917 io.fromCSR.virtualInst.cboCF && (isCboClean || isCboFlush) || 918 io.fromCSR.virtualInst.cboI && isCboInval 919 920 921 decodedInst.exceptionVec(illegalInstr) := exceptionII || io.enq.ctrlFlow.exceptionVec(EX_II) 922 decodedInst.exceptionVec(virtualInstr) := exceptionVI 923 924 //update exceptionVec: from frontend trigger's breakpoint exception. To reduce 1 bit of overhead in ibuffer entry. 925 decodedInst.exceptionVec(breakPoint) := TriggerAction.isExp(ctrl_flow.trigger) 926 927 decodedInst.imm := LookupTree(decodedInst.selImm, ImmUnion.immSelMap.map( 928 x => { 929 val minBits = x._2.minBitsFromInstr(ctrl_flow.instr) 930 require(minBits.getWidth == x._2.len) 931 x._1 -> minBits 932 } 933 )) 934 935 private val isLs = FuType.isLoadStore(decodedInst.fuType) 936 private val isVls = inst.isVecStore || inst.isVecLoad 937 private val isStore = FuType.isStore(decodedInst.fuType) 938 private val isAMO = FuType.isAMO(decodedInst.fuType) 939 private val isVStore = FuType.isVStore(decodedInst.fuType) 940 private val isBranch = !decodedInst.preDecodeInfo.notCFI || FuType.isJump(decodedInst.fuType) 941 942 decodedInst.commitType := Cat(isLs | isVls, (isStore && !isAMO) | isVStore | isBranch) 943 944 decodedInst.isVset := FuType.isVset(decodedInst.fuType) 945 946 private val needReverseInsts = Seq(VRSUB_VI, VRSUB_VX, VFRDIV_VF, VFRSUB_VF, VFMV_F_S) 947 private val vextInsts = Seq(VZEXT_VF2, VZEXT_VF4, VZEXT_VF8, VSEXT_VF2, VSEXT_VF4, VSEXT_VF8) 948 private val narrowInsts = Seq( 949 VNSRA_WV, VNSRA_WX, VNSRA_WI, VNSRL_WV, VNSRL_WX, VNSRL_WI, 950 VNCLIP_WV, VNCLIP_WX, VNCLIP_WI, VNCLIPU_WV, VNCLIPU_WX, VNCLIPU_WI, 951 ) 952 private val maskDstInsts = Seq( 953 VMADC_VV, VMADC_VX, VMADC_VI, VMADC_VVM, VMADC_VXM, VMADC_VIM, 954 VMSBC_VV, VMSBC_VX, VMSBC_VVM, VMSBC_VXM, 955 VMAND_MM, VMNAND_MM, VMANDN_MM, VMXOR_MM, VMOR_MM, VMNOR_MM, VMORN_MM, VMXNOR_MM, 956 VMSEQ_VV, VMSEQ_VX, VMSEQ_VI, VMSNE_VV, VMSNE_VX, VMSNE_VI, 957 VMSLE_VV, VMSLE_VX, VMSLE_VI, VMSLEU_VV, VMSLEU_VX, VMSLEU_VI, 958 VMSLT_VV, VMSLT_VX, VMSLTU_VV, VMSLTU_VX, 959 VMSGT_VX, VMSGT_VI, VMSGTU_VX, VMSGTU_VI, 960 VMFEQ_VV, VMFEQ_VF, VMFNE_VV, VMFNE_VF, VMFLT_VV, VMFLT_VF, VMFLE_VV, VMFLE_VF, VMFGT_VF, VMFGE_VF, 961 ) 962 private val maskOpInsts = Seq( 963 VMAND_MM, VMNAND_MM, VMANDN_MM, VMXOR_MM, VMOR_MM, VMNOR_MM, VMORN_MM, VMXNOR_MM, 964 ) 965 private val vmaInsts = Seq( 966 VMACC_VV, VMACC_VX, VNMSAC_VV, VNMSAC_VX, VMADD_VV, VMADD_VX, VNMSUB_VV, VNMSUB_VX, 967 VWMACCU_VV, VWMACCU_VX, VWMACC_VV, VWMACC_VX, VWMACCSU_VV, VWMACCSU_VX, VWMACCUS_VX, 968 ) 969 private val wfflagsInsts = Seq( 970 // opfff 971 FADD_S, FSUB_S, FADD_D, FSUB_D, FADD_H, FSUB_H, 972 FEQ_S, FLT_S, FLE_S, FEQ_D, FLT_D, FLE_D, FEQ_H, FLT_H, FLE_H, 973 FMIN_S, FMAX_S, FMIN_D, FMAX_D, FMIN_H, FMAX_H, 974 FMUL_S, FMUL_D, FMUL_H, 975 FDIV_S, FDIV_D, FSQRT_S, FSQRT_D, FDIV_H, FSQRT_H, 976 FMADD_S, FMSUB_S, FNMADD_S, FNMSUB_S, FMADD_D, FMSUB_D, FNMADD_D, FNMSUB_D, FMADD_H, FMSUB_H, FNMADD_H, FNMSUB_H, 977 FSGNJ_S, FSGNJN_S, FSGNJX_S, FSGNJ_H, FSGNJN_H, FSGNJX_H, 978 // opfvv 979 VFADD_VV, VFSUB_VV, VFWADD_VV, VFWSUB_VV, VFWADD_WV, VFWSUB_WV, 980 VFMUL_VV, VFDIV_VV, VFWMUL_VV, 981 VFMACC_VV, VFNMACC_VV, VFMSAC_VV, VFNMSAC_VV, VFMADD_VV, VFNMADD_VV, VFMSUB_VV, VFNMSUB_VV, 982 VFWMACC_VV, VFWNMACC_VV, VFWMSAC_VV, VFWNMSAC_VV, 983 VFSQRT_V, 984 VFMIN_VV, VFMAX_VV, 985 VMFEQ_VV, VMFNE_VV, VMFLT_VV, VMFLE_VV, 986 VFSGNJ_VV, VFSGNJN_VV, VFSGNJX_VV, 987 // opfvf 988 VFADD_VF, VFSUB_VF, VFRSUB_VF, VFWADD_VF, VFWSUB_VF, VFWADD_WF, VFWSUB_WF, 989 VFMUL_VF, VFDIV_VF, VFRDIV_VF, VFWMUL_VF, 990 VFMACC_VF, VFNMACC_VF, VFMSAC_VF, VFNMSAC_VF, VFMADD_VF, VFNMADD_VF, VFMSUB_VF, VFNMSUB_VF, 991 VFWMACC_VF, VFWNMACC_VF, VFWMSAC_VF, VFWNMSAC_VF, 992 VFMIN_VF, VFMAX_VF, 993 VMFEQ_VF, VMFNE_VF, VMFLT_VF, VMFLE_VF, VMFGT_VF, VMFGE_VF, 994 VFSGNJ_VF, VFSGNJN_VF, VFSGNJX_VF, 995 // vfred 996 VFREDOSUM_VS, VFREDUSUM_VS, VFREDMAX_VS, VFREDMIN_VS, VFWREDOSUM_VS, VFWREDUSUM_VS, 997 // fcvt & vfcvt 998 FCVT_S_W, FCVT_S_WU, FCVT_S_L, FCVT_S_LU, 999 FCVT_W_S, FCVT_WU_S, FCVT_L_S, FCVT_LU_S, 1000 FCVT_D_W, FCVT_D_WU, FCVT_D_L, FCVT_D_LU, 1001 FCVT_W_D, FCVT_WU_D, FCVT_L_D, FCVT_LU_D, FCVT_S_D, FCVT_D_S, 1002 FCVT_S_H, FCVT_H_S, FCVT_H_D, FCVT_D_H, 1003 FCVT_H_W, FCVT_H_WU, FCVT_H_L, FCVT_H_LU, 1004 FCVT_W_H, FCVT_WU_H, FCVT_L_H, FCVT_LU_H, 1005 VFCVT_XU_F_V, VFCVT_X_F_V, VFCVT_RTZ_XU_F_V, VFCVT_RTZ_X_F_V, VFCVT_F_XU_V, VFCVT_F_X_V, 1006 VFWCVT_XU_F_V, VFWCVT_X_F_V, VFWCVT_RTZ_XU_F_V, VFWCVT_RTZ_X_F_V, VFWCVT_F_XU_V, VFWCVT_F_X_V, VFWCVT_F_F_V, 1007 VFNCVT_XU_F_W, VFNCVT_X_F_W, VFNCVT_RTZ_XU_F_W, VFNCVT_RTZ_X_F_W, VFNCVT_F_XU_W, VFNCVT_F_X_W, VFNCVT_F_F_W, 1008 VFNCVT_ROD_F_F_W, VFRSQRT7_V, VFREC7_V, 1009 // zfa 1010 FLEQ_H, FLEQ_S, FLEQ_D, FLTQ_H, FLTQ_S, FLTQ_D, 1011 FMINM_H, FMINM_S, FMINM_D, FMAXM_H, FMAXM_S, FMAXM_D, 1012 FROUND_H, FROUND_S, FROUND_D, FROUNDNX_H, FROUNDNX_S, FROUNDNX_D, 1013 FCVTMOD_W_D, 1014 ) 1015 1016 private val scalaNeedFrmInsts = Seq( 1017 FADD_S, FSUB_S, FADD_D, FSUB_D, FADD_H, FSUB_H, 1018 FCVT_W_S, FCVT_WU_S, FCVT_L_S, FCVT_LU_S, 1019 FCVT_W_D, FCVT_WU_D, FCVT_L_D, FCVT_LU_D, FCVT_S_D, FCVT_D_S, 1020 FCVT_W_H, FCVT_WU_H, FCVT_L_H, FCVT_LU_H, 1021 FCVT_S_H, FCVT_H_S, FCVT_H_D, FCVT_D_H, 1022 FROUND_H, FROUND_S, FROUND_D, FROUNDNX_H, FROUNDNX_S, FROUNDNX_D, 1023 ) 1024 1025 private val vectorNeedFrmInsts = Seq ( 1026 VFSLIDE1UP_VF, VFSLIDE1DOWN_VF, 1027 ) 1028 1029 decodedInst.wfflags := wfflagsInsts.map(_ === inst.ALL).reduce(_ || _) 1030 decodedInst.needFrm.scalaNeedFrm := scalaNeedFrmInsts.map(_ === inst.ALL).reduce(_ || _) 1031 decodedInst.needFrm.vectorNeedFrm := vectorNeedFrmInsts.map(_ === inst.ALL).reduce(_ || _) 1032 decodedInst.vpu := 0.U.asTypeOf(decodedInst.vpu) // Todo: Connect vpu decoder 1033 decodedInst.vpu.vill := io.enq.vtype.illegal 1034 decodedInst.vpu.vma := io.enq.vtype.vma 1035 decodedInst.vpu.vta := io.enq.vtype.vta 1036 decodedInst.vpu.vsew := io.enq.vtype.vsew 1037 decodedInst.vpu.vlmul := io.enq.vtype.vlmul 1038 decodedInst.vpu.vm := inst.VM 1039 decodedInst.vpu.nf := inst.NF 1040 decodedInst.vpu.veew := inst.WIDTH 1041 decodedInst.vpu.isReverse := needReverseInsts.map(_ === inst.ALL).reduce(_ || _) 1042 decodedInst.vpu.isExt := vextInsts.map(_ === inst.ALL).reduce(_ || _) 1043 val isNarrow = narrowInsts.map(_ === inst.ALL).reduce(_ || _) 1044 val isDstMask = maskDstInsts.map(_ === inst.ALL).reduce(_ || _) 1045 val isOpMask = maskOpInsts.map(_ === inst.ALL).reduce(_ || _) 1046 val isVload = FuType.isVLoad(decodedInst.fuType) 1047 val isVlx = isVload && (decodedInst.fuOpType === VlduType.vloxe || decodedInst.fuOpType === VlduType.vluxe) 1048 val isVle = isVload && (decodedInst.fuOpType === VlduType.vle || decodedInst.fuOpType === VlduType.vleff || decodedInst.fuOpType === VlduType.vlse) 1049 val isVlm = isVload && (decodedInst.fuOpType === VlduType.vlm) 1050 val isFof = isVload && (decodedInst.fuOpType === VlduType.vleff) 1051 val isWritePartVd = decodedInst.uopSplitType === UopSplitType.VEC_VRED || decodedInst.uopSplitType === UopSplitType.VEC_0XV || decodedInst.uopSplitType === UopSplitType.VEC_VWW 1052 val isVma = vmaInsts.map(_ === inst.ALL).reduce(_ || _) 1053 val emulIsFrac = Cat(~decodedInst.vpu.vlmul(2), decodedInst.vpu.vlmul(1, 0)) +& decodedInst.vpu.veew < 4.U +& decodedInst.vpu.vsew 1054 val vstartIsNotZero = io.enq.vstart =/= 0.U 1055 decodedInst.vpu.isNarrow := isNarrow 1056 decodedInst.vpu.isDstMask := isDstMask 1057 decodedInst.vpu.isOpMask := isOpMask 1058 decodedInst.vpu.isDependOldVd := isVppu || isVecOPF || isVStore || (isDstMask && !isOpMask) || isNarrow || isVlx || isVma || isFof || vstartIsNotZero 1059 decodedInst.vpu.isWritePartVd := isWritePartVd || isVlm || isVle && emulIsFrac 1060 decodedInst.vpu.vstart := io.enq.vstart 1061 decodedInst.vpu.isVleff := isFof && inst.NF === 0.U 1062 decodedInst.vpu.specVill := io.enq.vtype.illegal 1063 decodedInst.vpu.specVma := io.enq.vtype.vma 1064 decodedInst.vpu.specVta := io.enq.vtype.vta 1065 decodedInst.vpu.specVsew := io.enq.vtype.vsew 1066 decodedInst.vpu.specVlmul := io.enq.vtype.vlmul 1067 1068 decodedInst.vlsInstr := isVls 1069 1070 decodedInst.srcType(3) := Mux(inst.VM === 0.U, SrcType.vp, SrcType.DC) // mask src 1071 decodedInst.srcType(4) := SrcType.vp // vconfig 1072 1073 val uopInfoGen = Module(new UopInfoGen) 1074 uopInfoGen.io.in.preInfo.isVecArith := inst.isVecArith 1075 uopInfoGen.io.in.preInfo.isVecMem := inst.isVecStore || inst.isVecLoad 1076 uopInfoGen.io.in.preInfo.isAmoCAS := inst.isAMOCAS 1077 1078 uopInfoGen.io.in.preInfo.typeOfSplit := decodedInst.uopSplitType 1079 uopInfoGen.io.in.preInfo.vsew := decodedInst.vpu.vsew 1080 uopInfoGen.io.in.preInfo.vlmul := decodedInst.vpu.vlmul 1081 uopInfoGen.io.in.preInfo.vwidth := inst.RM 1082 uopInfoGen.io.in.preInfo.vmvn := inst.IMM5_OPIVI(2, 0) 1083 uopInfoGen.io.in.preInfo.nf := inst.NF 1084 uopInfoGen.io.in.preInfo.isVlsr := decodedInst.fuOpType === VlduType.vlr || decodedInst.fuOpType === VstuType.vsr 1085 uopInfoGen.io.in.preInfo.isVlsm := decodedInst.fuOpType === VlduType.vlm || decodedInst.fuOpType === VstuType.vsm 1086 io.deq.isComplex := uopInfoGen.io.out.isComplex 1087 io.deq.uopInfo.numOfUop := uopInfoGen.io.out.uopInfo.numOfUop 1088 io.deq.uopInfo.numOfWB := uopInfoGen.io.out.uopInfo.numOfWB 1089 io.deq.uopInfo.lmul := uopInfoGen.io.out.uopInfo.lmul 1090 1091 val isCsr = inst.OPCODE5Bit === OPCODE5Bit.SYSTEM && inst.FUNCT3(1, 0) =/= 0.U 1092 val isCsrr = isCsr && inst.FUNCT3 === BitPat("b?1?") && inst.RS1 === 0.U 1093 val isCsrw = isCsr && inst.FUNCT3 === BitPat("b?01") && inst.RD === 0.U 1094 dontTouch(isCsrr) 1095 dontTouch(isCsrw) 1096 1097 // for csrr vl instruction, convert to vsetvl 1098 val isCsrrVlenb = isCsrr && inst.CSRIDX === CSRs.vlenb.U 1099 val isCsrrVl = isCsrr && inst.CSRIDX === CSRs.vl.U 1100 1101 // decode for SoftPrefetch instructions (prefetch.w / prefetch.r / prefetch.i) 1102 val isSoftPrefetch = inst.OPCODE === BitPat("b0010011") && inst.FUNCT3 === BitPat("b110") && inst.RD === 0.U 1103 val isPreW = isSoftPrefetch && inst.RS2 === 3.U(5.W) 1104 val isPreR = isSoftPrefetch && inst.RS2 === 1.U(5.W) 1105 val isPreI = isSoftPrefetch && inst.RS2 === 0.U(5.W) 1106 1107 // for fli.s|fli.d instruction 1108 val isFLI = inst.FUNCT7 === BitPat("b11110??") && inst.RS2 === 1.U && inst.RM === 0.U && inst.OPCODE5Bit === OPCODE5Bit.OP_FP 1109 1110 when (isCsrrVl) { 1111 // convert to vsetvl instruction 1112 decodedInst.srcType(0) := SrcType.no 1113 decodedInst.srcType(1) := SrcType.no 1114 decodedInst.srcType(2) := SrcType.no 1115 decodedInst.srcType(3) := SrcType.no 1116 decodedInst.srcType(4) := SrcType.vp 1117 decodedInst.lsrc(4) := Vl_IDX.U 1118 decodedInst.waitForward := false.B 1119 decodedInst.blockBackward := false.B 1120 decodedInst.exceptionVec(illegalInstr) := io.fromCSR.illegalInst.vsIsOff 1121 }.elsewhen (isCsrrVlenb) { 1122 // convert to addi instruction 1123 decodedInst.srcType(0) := SrcType.reg 1124 decodedInst.srcType(1) := SrcType.imm 1125 decodedInst.srcType(2) := SrcType.no 1126 decodedInst.srcType(3) := SrcType.no 1127 decodedInst.srcType(4) := SrcType.no 1128 decodedInst.selImm := SelImm.IMM_I 1129 decodedInst.waitForward := false.B 1130 decodedInst.blockBackward := false.B 1131 decodedInst.canRobCompress := true.B 1132 decodedInst.exceptionVec(illegalInstr) := io.fromCSR.illegalInst.vsIsOff 1133 }.elsewhen (isPreW || isPreR || isPreI) { 1134 decodedInst.selImm := SelImm.IMM_S 1135 decodedInst.fuType := FuType.ldu.U 1136 decodedInst.canRobCompress := false.B 1137 }.elsewhen (isZimop) { 1138 // set srcType for zimop 1139 decodedInst.srcType(0) := SrcType.reg 1140 decodedInst.srcType(1) := SrcType.imm 1141 // use x0 as src1 1142 decodedInst.lsrc(0) := 0.U 1143 } 1144 1145 io.deq.decodedInst := decodedInst 1146 io.deq.decodedInst.rfWen := (decodedInst.ldest =/= 0.U) && decodedInst.rfWen 1147 io.deq.decodedInst.fuType := Mux1H(Seq( 1148 // keep condition 1149 (!FuType.FuTypeOrR(decodedInst.fuType, FuType.vldu, FuType.vstu) && !isCsrrVl && !isCsrrVlenb) -> decodedInst.fuType, 1150 (isCsrrVl) -> FuType.vsetfwf.U, 1151 (isCsrrVlenb) -> FuType.alu.U, 1152 1153 // change vlsu to vseglsu when NF =/= 0.U 1154 ( FuType.FuTypeOrR(decodedInst.fuType, FuType.vldu, FuType.vstu) && inst.NF === 0.U || (inst.NF =/= 0.U && (inst.MOP === "b00".U && inst.SUMOP === "b01000".U))) -> decodedInst.fuType, 1155 // MOP === b00 && SUMOP === b01000: unit-stride whole register store 1156 // MOP =/= b00 : strided and indexed store 1157 ( FuType.FuTypeOrR(decodedInst.fuType, FuType.vstu) && inst.NF =/= 0.U && ((inst.MOP === "b00".U && inst.SUMOP =/= "b01000".U) || inst.MOP =/= "b00".U)) -> FuType.vsegstu.U, 1158 // MOP === b00 && LUMOP === b01000: unit-stride whole register load 1159 // MOP =/= b00 : strided and indexed load 1160 ( FuType.FuTypeOrR(decodedInst.fuType, FuType.vldu) && inst.NF =/= 0.U && ((inst.MOP === "b00".U && inst.LUMOP =/= "b01000".U) || inst.MOP =/= "b00".U)) -> FuType.vsegldu.U, 1161 )) 1162 io.deq.decodedInst.imm := MuxCase(decodedInst.imm, Seq( 1163 isCsrrVlenb -> (VLEN / 8).U, 1164 isZimop -> 0.U, 1165 )) 1166 1167 io.deq.decodedInst.fuOpType := MuxCase(decodedInst.fuOpType, Seq( 1168 isCsrrVl -> VSETOpType.csrrvl, 1169 isCsrrVlenb -> ALUOpType.add, 1170 isFLI -> Cat(1.U, inst.FMT, inst.RS1), 1171 (isPreW || isPreR || isPreI) -> Mux1H(Seq( 1172 isPreW -> LSUOpType.prefetch_w, 1173 isPreR -> LSUOpType.prefetch_r, 1174 isPreI -> LSUOpType.prefetch_i, 1175 )), 1176 (isCboInval && io.fromCSR.special.cboI2F) -> LSUOpType.cbo_flush, 1177 )) 1178 1179 // Don't compress in the same Rob entry when crossing Ftq entry boundary 1180 io.deq.decodedInst.canRobCompress := decodedInst.canRobCompress && !io.enq.ctrlFlow.isLastInFtqEntry 1181 1182 //------------------------------------------------------------- 1183 // Debug Info 1184// XSDebug("in: instr=%x pc=%x excepVec=%b crossPageIPFFix=%d\n", 1185// io.enq.ctrl_flow.instr, io.enq.ctrl_flow.pc, io.enq.ctrl_flow.exceptionVec.asUInt, 1186// io.enq.ctrl_flow.crossPageIPFFix) 1187// XSDebug("out: srcType(0)=%b srcType(1)=%b srcType(2)=%b lsrc(0)=%d lsrc(1)=%d lsrc(2)=%d ldest=%d fuType=%b fuOpType=%b\n", 1188// io.deq.cf_ctrl.ctrl.srcType(0), io.deq.cf_ctrl.ctrl.srcType(1), io.deq.cf_ctrl.ctrl.srcType(2), 1189// io.deq.cf_ctrl.ctrl.lsrc(0), io.deq.cf_ctrl.ctrl.lsrc(1), io.deq.cf_ctrl.ctrl.lsrc(2), 1190// io.deq.cf_ctrl.ctrl.ldest, io.deq.cf_ctrl.ctrl.fuType, io.deq.cf_ctrl.ctrl.fuOpType) 1191// XSDebug("out: rfWen=%d fpWen=%d isXSTrap=%d noSpecExec=%d isBlocked=%d flushPipe=%d imm=%x\n", 1192// io.deq.cf_ctrl.ctrl.rfWen, io.deq.cf_ctrl.ctrl.fpWen, io.deq.cf_ctrl.ctrl.isXSTrap, 1193// io.deq.cf_ctrl.ctrl.noSpecExec, io.deq.cf_ctrl.ctrl.blockBackward, io.deq.cf_ctrl.ctrl.flushPipe, 1194// io.deq.cf_ctrl.ctrl.imm) 1195// XSDebug("out: excepVec=%b\n", io.deq.cf_ctrl.cf.exceptionVec.asUInt) 1196} 1197