xref: /XiangShan/src/main/scala/xiangshan/mem/sbuffer/DatamoduleResultBuffer.scala (revision 8891a219bbc84f568e1d134854d8d5ed86d6d560) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.mem
18
19import org.chipsalliance.cde.config.Parameters
20import chisel3.experimental.{DataMirror, requireIsChiselType}
21import chisel3._
22import chisel3.util._
23import xiangshan._
24import utils._
25import utility._
26import xiangshan.cache._
27import difftest._
28
29class DatamoduleResultBufferIO[T <: Data](gen: T)(implicit p: Parameters) extends XSBundle
30{
31  // val flush = Input(Bool())
32  val enq = Vec(EnsbufferWidth, Flipped(DecoupledIO(gen)))
33  val deq = Vec(EnsbufferWidth, DecoupledIO(gen))
34
35}
36
37class DatamoduleResultBuffer[T <: Data]
38(
39  gen: T,
40)(implicit p: Parameters) extends XSModule {
41
42  val genType = {
43    requireIsChiselType(gen)
44    gen
45  }
46
47  val io = IO(new DatamoduleResultBufferIO[T](gen))
48
49  val data = Reg(Vec(EnsbufferWidth, genType))
50  val valids = RegInit(VecInit(Seq.fill(EnsbufferWidth)(false.B)))
51  val enq_flag = RegInit(0.U(log2Up(EnsbufferWidth).W)) // head is entry 0
52  val deq_flag = RegInit(0.U(log2Up(EnsbufferWidth).W)) // tail is entry 0
53
54  val entry_allowin = Wire(Vec(EnsbufferWidth, Bool()))
55
56  (0 until EnsbufferWidth).foreach(index => {
57    io.deq(index).valid := valids(deq_flag + index.U) && (if (index == 0) 1.B else io.deq(index - 1).valid)
58    io.deq(index).bits := data(deq_flag + index.U)
59  })
60
61  (1 until EnsbufferWidth).foreach(i => {
62    assert(!(io.deq(i).valid && !io.deq(i - 1).valid))
63    assert(!(io.deq(i).ready && !io.deq(i - 1).ready))
64  })
65
66  (0 until EnsbufferWidth).foreach(
67    index => entry_allowin(index) := !valids(index) || (0 until EnsbufferWidth).map(i => io.deq(i).fire && deq_flag + i.U === index.U).reduce(_ || _)
68  )
69
70  (0 until EnsbufferWidth).foreach(
71    index => io.enq(index).ready := entry_allowin(enq_flag + index.U) && (if (index == 0) 1.B else io.enq(index - 1).ready)
72  )
73
74  (1 until EnsbufferWidth).foreach(i => {
75    assert(!(io.enq(i).ready && !io.enq(i - 1).ready))
76    assert(!(io.enq(i).valid && !io.enq(i - 1).valid))
77  })
78
79  (0 until EnsbufferWidth).foreach(index =>
80    when(io.deq(index).fire) {
81      valids(deq_flag + index.U) := 0.B
82      if (EnsbufferWidth > 1) deq_flag := deq_flag + index.U + 1.U
83    }
84  )
85
86  (0 until EnsbufferWidth).foreach(index =>
87    when(io.enq(index).fire) {
88      valids(enq_flag + index.U) := 1.B
89      data(enq_flag + index.U) := io.enq(index).bits
90      if (EnsbufferWidth > 1) enq_flag := enq_flag + index.U + 1.U
91    }
92  )
93}
94