xref: /XiangShan/src/main/scala/xiangshan/mem/prefetch/BasePrefecher.scala (revision 8891a219bbc84f568e1d134854d8d5ed86d6d560) 
1/***************************************************************************************
2  * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3  * Copyright (c) 2020-2021 Peng Cheng Laboratory
4  *
5  * XiangShan is licensed under Mulan PSL v2.
6  * You can use this software according to the terms and conditions of the Mulan PSL v2.
7  * You may obtain a copy of Mulan PSL v2 at:
8  *          http://license.coscl.org.cn/MulanPSL2
9  *
10  * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11  * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12  * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13  *
14  * See the Mulan PSL v2 for more details.
15  ***************************************************************************************/
16
17package xiangshan.mem.prefetch
18
19import chisel3._
20import chisel3.util._
21import org.chipsalliance.cde.config.Parameters
22import utility.MemReqSource
23import xiangshan._
24import xiangshan.cache.mmu.TlbRequestIO
25import xiangshan.mem.{LdPrefetchTrainBundle, StPrefetchTrainBundle, L1PrefetchReq}
26
27class L2PrefetchReq(implicit p: Parameters) extends XSBundle {
28  val addr = UInt(PAddrBits.W)
29  val source = UInt(MemReqSource.reqSourceBits.W)
30}
31
32class PrefetcherIO()(implicit p: Parameters) extends XSBundle {
33  val ld_in = Flipped(Vec(exuParameters.LduCnt, ValidIO(new LdPrefetchTrainBundle())))
34  val st_in = Flipped(Vec(exuParameters.StuCnt, ValidIO(new StPrefetchTrainBundle())))
35  val tlb_req = new TlbRequestIO(nRespDups = 2)
36  val l1_req = DecoupledIO(new L1PrefetchReq())
37  val l2_req = ValidIO(new L2PrefetchReq())
38  val l3_req = ValidIO(UInt(PAddrBits.W)) // TODO: l3 pf source
39  val enable = Input(Bool())
40}
41
42class PrefetchReqBundle()(implicit p: Parameters) extends XSBundle {
43  val vaddr = UInt(VAddrBits.W)
44  val paddr = UInt(PAddrBits.W)
45  val pc    = UInt(VAddrBits.W)
46}
47
48trait PrefetcherParams
49
50abstract class BasePrefecher()(implicit p: Parameters) extends XSModule {
51  val io = IO(new PrefetcherIO())
52
53  io.l3_req.valid := false.B
54  io.l3_req.bits  := DontCare
55}