1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend.icache 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import difftest._ 23import freechips.rocketchip.tilelink.ClientStates 24import xiangshan._ 25import xiangshan.cache.mmu._ 26import utils._ 27import utility._ 28import xiangshan.backend.fu.{PMPReqBundle, PMPRespBundle} 29import xiangshan.frontend.{FtqICacheInfo, FtqToICacheRequestBundle} 30import org.scalatest.tools.SuiteResultHolder 31 32class ICacheMainPipeReq(implicit p: Parameters) extends ICacheBundle 33{ 34 val vaddr = UInt(VAddrBits.W) 35 def vsetIdx = get_idx(vaddr) 36} 37 38class ICacheMainPipeResp(implicit p: Parameters) extends ICacheBundle 39{ 40 val vaddr = UInt(VAddrBits.W) 41 val registerData = UInt(blockBits.W) 42 val sramData = UInt(blockBits.W) 43 val select = Bool() 44 val paddr = UInt(PAddrBits.W) 45 val tlbExcp = new Bundle{ 46 val pageFault = Bool() 47 val accessFault = Bool() 48 val mmio = Bool() 49 } 50} 51 52class ICacheMainPipeBundle(implicit p: Parameters) extends ICacheBundle 53{ 54 val req = Flipped(Decoupled(new FtqToICacheRequestBundle)) 55 val resp = Vec(PortNumber, ValidIO(new ICacheMainPipeResp)) 56 val topdownIcacheMiss = Output(Bool()) 57 val topdownItlbMiss = Output(Bool()) 58} 59 60class ICacheMetaReqBundle(implicit p: Parameters) extends ICacheBundle{ 61 val toIMeta = DecoupledIO(new ICacheReadBundle) 62 val fromIMeta = Input(new ICacheMetaRespBundle) 63} 64 65class ICacheDataReqBundle(implicit p: Parameters) extends ICacheBundle{ 66 val toIData = DecoupledIO(Vec(partWayNum, new ICacheReadBundle)) 67 val fromIData = Input(new ICacheDataRespBundle) 68} 69 70class ICacheMSHRBundle(implicit p: Parameters) extends ICacheBundle{ 71 val toMSHR = Decoupled(new ICacheMissReq) 72 val fromMSHR = Flipped(ValidIO(new ICacheMissResp)) 73} 74 75class ICachePMPBundle(implicit p: Parameters) extends ICacheBundle{ 76 val req = Valid(new PMPReqBundle()) 77 val resp = Input(new PMPRespBundle()) 78} 79 80class ICachePerfInfo(implicit p: Parameters) extends ICacheBundle{ 81 val only_0_hit = Bool() 82 val only_0_miss = Bool() 83 val hit_0_hit_1 = Bool() 84 val hit_0_miss_1 = Bool() 85 val miss_0_hit_1 = Bool() 86 val miss_0_miss_1 = Bool() 87 val hit_0_except_1 = Bool() 88 val miss_0_except_1 = Bool() 89 val except_0 = Bool() 90 val bank_hit = Vec(2,Bool()) 91 val hit = Bool() 92} 93 94class ICacheMainPipeInterface(implicit p: Parameters) extends ICacheBundle { 95 val hartId = Input(UInt(8.W)) 96 /*** internal interface ***/ 97 val metaArray = new ICacheMetaReqBundle 98 val dataArray = new ICacheDataReqBundle 99 /** prefetch io */ 100 val IPFBufferRead = Flipped(new IPFBufferRead) 101 val PIQRead = Flipped(new PIQRead) 102 103 val IPFReplacer = Flipped(new IPFReplacer) 104 // val mainPipeMissInfo = new MainPipeMissInfo() 105 val mainPipeMissInfo = Vec(PortNumber, ValidIO(new MainPipeMissInfo)) 106 107 val mshr = Vec(PortNumber, new ICacheMSHRBundle) 108 val errors = Output(Vec(PortNumber, new L1CacheErrorInfo)) 109 /*** outside interface ***/ 110 //val fetch = Vec(PortNumber, new ICacheMainPipeBundle) 111 /* when ftq.valid is high in T + 1 cycle 112 * the ftq component must be valid in T cycle 113 */ 114 val fetch = new ICacheMainPipeBundle 115 val pmp = Vec(PortNumber, new ICachePMPBundle) 116 val itlb = Vec(PortNumber, new TlbRequestIO) 117 val respStall = Input(Bool()) 118 val perfInfo = Output(new ICachePerfInfo) 119 120 val csr_parity_enable = Input(Bool()) 121} 122 123class ICacheMainPipe(implicit p: Parameters) extends ICacheModule 124{ 125 val io = IO(new ICacheMainPipeInterface) 126 127 /** Input/Output port */ 128 val (fromFtq, toIFU) = (io.fetch.req, io.fetch.resp) 129 val (toMeta, metaResp) = (io.metaArray.toIMeta, io.metaArray.fromIMeta) 130 val (toData, dataResp) = (io.dataArray.toIData, io.dataArray.fromIData) 131 val (toIPF, fromIPF) = (io.IPFBufferRead.req, io.IPFBufferRead.resp) 132 val (toPIQ, fromPIQ) = (io.PIQRead.req, io.PIQRead.resp) 133 val (toMSHR, fromMSHR) = (io.mshr.map(_.toMSHR), io.mshr.map(_.fromMSHR)) 134 val (toITLB, fromITLB) = (io.itlb.map(_.req), io.itlb.map(_.resp)) 135 val (toPMP, fromPMP) = (io.pmp.map(_.req), io.pmp.map(_.resp)) 136 137 val IPFReplacer = io.IPFReplacer 138 val mainPipeMissInfo = io.mainPipeMissInfo 139 // val mainPipeMissInfo = io.mainPipeMissInfo 140 141 //Ftq RegNext Register 142 val fromFtqReq = fromFtq.bits.pcMemRead 143 144 /** pipeline control signal */ 145 val s1_ready, s2_ready = Wire(Bool()) 146 val s0_fire, s1_fire , s2_fire = Wire(Bool()) 147 148 val missSwitchBit = RegInit(false.B) 149 150 /** replacement status register */ 151 val touch_sets = Seq.fill(2)(Wire(Vec(2, UInt(log2Ceil(nSets/2).W)))) 152 val touch_ways = Seq.fill(2)(Wire(Vec(2, Valid(UInt(log2Ceil(nWays).W)))) ) 153 154 /** 155 ****************************************************************************** 156 * ICache Stage 0 157 * - send req to ITLB and wait for tlb miss fixing 158 * - send req to Meta/Data SRAM 159 ****************************************************************************** 160 */ 161 162 /** s0 control */ 163 val s0_valid = fromFtq.valid 164 val s0_req_vaddr = (0 until partWayNum + 1).map(i => VecInit(Seq(fromFtqReq(i).startAddr, fromFtqReq(i).nextlineStart))) 165 val s0_req_vsetIdx = (0 until partWayNum + 1).map(i => VecInit(s0_req_vaddr(i).map(get_idx(_)))) 166 val s0_only_first = (0 until partWayNum + 1).map(i => fromFtq.bits.readValid(i) && !fromFtqReq(i).crossCacheline) 167 val s0_double_line = (0 until partWayNum + 1).map(i => fromFtq.bits.readValid(i) && fromFtqReq(i).crossCacheline) 168 169 val s0_final_valid = s0_valid 170 val s0_final_vaddr = s0_req_vaddr.head 171 val s0_final_vsetIdx = s0_req_vsetIdx.head 172 val s0_final_only_first = s0_only_first.head 173 val s0_final_double_line = s0_double_line.head 174 175 /** SRAM request */ 176 //0 -> metaread, 1,2,3 -> data, 3 -> code 4 -> itlb 177 // TODO: it seems like 0,1,2,3 -> dataArray(data); 3 -> dataArray(code); 0 -> metaArray; 4 -> itlb 178 val ftq_req_to_data_doubleline = s0_double_line.init 179 val ftq_req_to_data_vset_idx = s0_req_vsetIdx.init 180 val ftq_req_to_data_valid = fromFtq.bits.readValid.init 181 182 val ftq_req_to_meta_doubleline = s0_double_line.head 183 val ftq_req_to_meta_vset_idx = s0_req_vsetIdx.head 184 185 val ftq_req_to_itlb_only_first = s0_only_first.last 186 val ftq_req_to_itlb_doubleline = s0_double_line.last 187 val ftq_req_to_itlb_vaddr = s0_req_vaddr.last 188 val ftq_req_to_itlb_vset_idx = s0_req_vsetIdx.last 189 190 /** Data request */ 191 for(i <- 0 until partWayNum) { 192 toData.valid := ftq_req_to_data_valid(i) && !missSwitchBit 193 toData.bits(i).isDoubleLine := ftq_req_to_data_doubleline(i) 194 toData.bits(i).vSetIdx := ftq_req_to_data_vset_idx(i) 195 } 196 197 /** Meta request */ 198 toMeta.valid := s0_valid && !missSwitchBit 199 toMeta.bits.isDoubleLine := ftq_req_to_meta_doubleline 200 toMeta.bits.vSetIdx := ftq_req_to_meta_vset_idx 201 202 val toITLB_s0_valid = VecInit(Seq(s0_valid, s0_valid && ftq_req_to_itlb_doubleline)) 203 val toITLB_s0_size = VecInit(Seq(3.U, 3.U)) // TODO: fix the size 204 val toITLB_s0_vaddr = ftq_req_to_itlb_vaddr 205 val toITLB_s0_debug_pc = ftq_req_to_itlb_vaddr 206 207 val itlb_can_go = toITLB(0).ready && toITLB(1).ready 208 val icache_can_go = toData.ready && toMeta.ready 209 val pipe_can_go = !missSwitchBit && s1_ready 210 val s0_can_go = itlb_can_go && icache_can_go && pipe_can_go 211 s0_fire := s0_valid && s0_can_go 212 213 //TODO: fix GTimer() condition 214 fromFtq.ready := s0_can_go 215 216 /** 217 ****************************************************************************** 218 * ICache Stage 1 219 * - get tlb resp data (exceptiong info and physical addresses) 220 * - get Meta/Data SRAM read responses (latched for pipeline stop) 221 * - tag compare/hit check 222 * - check ipf and piq 223 ****************************************************************************** 224 */ 225 226 /** s1 control */ 227 val s1_valid = generatePipeControl(lastFire = s0_fire, thisFire = s1_fire, thisFlush = false.B, lastFlush = false.B) 228 229 val s1_req_vaddr = RegEnable(s0_final_vaddr, s0_fire) 230 val s1_req_vsetIdx = RegEnable(s0_final_vsetIdx, s0_fire) 231 val s1_only_first = RegEnable(s0_final_only_first, s0_fire) 232 val s1_double_line = RegEnable(s0_final_double_line, s0_fire) 233 234 /** tlb request and response */ 235 fromITLB.foreach(_.ready := true.B) 236 val s1_wait_itlb = RegInit(VecInit(Seq.fill(PortNumber)(false.B))) 237 238 (0 until PortNumber).foreach { i => 239 when(RegNext(s0_fire) && fromITLB(i).bits.miss) { 240 s1_wait_itlb(i) := true.B 241 }.elsewhen(s1_wait_itlb(i) && !fromITLB(i).bits.miss) { 242 s1_wait_itlb(i) := false.B 243 } 244 } 245 246 val s1_need_itlb = Seq((RegNext(s0_fire) || s1_wait_itlb(0)) && fromITLB(0).bits.miss, 247 (RegNext(s0_fire) || s1_wait_itlb(1)) && fromITLB(1).bits.miss && s1_double_line) 248 val toITLB_s1_valid = s1_need_itlb 249 val toITLB_s1_size = VecInit(Seq(3.U, 3.U)) // TODO: fix the size 250 val toITLB_s1_vaddr = s1_req_vaddr 251 val toITLB_s1_debug_pc = s1_req_vaddr 252 253 // chose tlb req between s0 and s1 254 for (i <- 0 until PortNumber) { 255 toITLB(i).valid := Mux(s1_need_itlb(i), toITLB_s1_valid(i), toITLB_s0_valid(i)) 256 toITLB(i).bits.size := Mux(s1_need_itlb(i), toITLB_s1_size(i), toITLB_s0_size(i)) 257 toITLB(i).bits.vaddr := Mux(s1_need_itlb(i), toITLB_s1_vaddr(i), toITLB_s0_vaddr(i)) 258 toITLB(i).bits.debug.pc := Mux(s1_need_itlb(i), toITLB_s1_debug_pc(i), toITLB_s0_debug_pc(i)) 259 } 260 toITLB.map{port => 261 port.bits.cmd := TlbCmd.exec 262 port.bits.memidx := DontCare 263 port.bits.debug.robIdx := DontCare 264 port.bits.no_translate := false.B 265 port.bits.debug.isFirstIssue := DontCare 266 port.bits.kill := DontCare 267 } 268 io.itlb.foreach(_.req_kill := false.B) 269 270 /** tlb response latch for pipeline stop */ 271 // val tlb_valid_tmp = VecInit((0 until PortNumber).map(i => 272 // (RegNext(s0_fire) || s1_wait_itlb(i)) && !fromITLB(i).bits.miss)) 273 val tlb_valid_tmp = VecInit(Seq((RegNext(s0_fire) || s1_wait_itlb(0)) && !fromITLB(0).bits.miss, 274 (RegNext(s0_fire) || s1_wait_itlb(1)) && !fromITLB(1).bits.miss && s1_double_line)) 275 val tlbRespPAddr = VecInit((0 until PortNumber).map(i => 276 ResultHoldBypass(valid = tlb_valid_tmp(i), data = fromITLB(i).bits.paddr(0)))) 277 val tlbExcpPF = VecInit((0 until PortNumber).map(i => 278 ResultHoldBypass(valid = tlb_valid_tmp(i), data = fromITLB(i).bits.excp(0).pf.instr))) 279 val tlbExcpAF = VecInit((0 until PortNumber).map(i => 280 ResultHoldBypass(valid = tlb_valid_tmp(i), data = fromITLB(i).bits.excp(0).af.instr))) 281 val tlbExcp = VecInit((0 until PortNumber).map(i => tlbExcpAF(i) || tlbExcpPF(i))) 282 283 val s1_tlb_valid = VecInit((0 until PortNumber).map(i => ValidHoldBypass(tlb_valid_tmp(i), s1_fire))) 284 val tlbRespAllValid = s1_tlb_valid(0) && (!s1_double_line || s1_double_line && s1_tlb_valid(1)) 285 286 287 def numOfStage = 3 288 val itlbMissStage = RegInit(VecInit(Seq.fill(numOfStage - 1)(0.B))) 289 itlbMissStage(0) := !tlbRespAllValid 290 for (i <- 1 until numOfStage - 1) { 291 itlbMissStage(i) := itlbMissStage(i - 1) 292 } 293 294 295 /** s1 hit check/tag compare */ 296 val s1_req_paddr = tlbRespPAddr 297 val s1_req_ptags = VecInit(s1_req_paddr.map(get_phy_tag(_))) 298 299 val s1_meta_ptags = ResultHoldBypass(data = metaResp.tags, valid = RegNext(s0_fire)) 300 val s1_meta_valids = ResultHoldBypass(data = metaResp.entryValid, valid = RegNext(s0_fire)) 301 val s1_meta_errors = ResultHoldBypass(data = metaResp.errors, valid = RegNext(s0_fire)) 302 303 val s1_data_cacheline = ResultHoldBypass(data = dataResp.datas, valid = RegNext(s0_fire)) 304 val s1_data_errorBits = ResultHoldBypass(data = dataResp.codes, valid = RegNext(s0_fire)) 305 306 val s1_tag_eq_vec = VecInit((0 until PortNumber).map( p => VecInit((0 until nWays).map( w => s1_meta_ptags(p)(w) === s1_req_ptags(p) )))) 307 val s1_tag_match_vec = VecInit((0 until PortNumber).map( k => VecInit(s1_tag_eq_vec(k).zipWithIndex.map{ case(way_tag_eq, w) => way_tag_eq && s1_meta_valids(k)(w) /*s1_meta_cohs(k)(w).isValid()*/}))) 308 val s1_tag_match = VecInit(s1_tag_match_vec.map(vector => ParallelOR(vector))) 309 310 val s1_port_hit = VecInit(Seq(s1_tag_match(0) && s1_valid && !tlbExcp(0), s1_tag_match(1) && s1_valid && s1_double_line && !tlbExcp(1) )) 311 val s1_bank_miss = VecInit(Seq(!s1_tag_match(0) && s1_valid && !tlbExcp(0), !s1_tag_match(1) && s1_valid && s1_double_line && !tlbExcp(1) )) 312 val s1_hit = (s1_port_hit(0) && s1_port_hit(1)) || (!s1_double_line && s1_port_hit(0)) 313 314 /** choose victim cacheline */ 315 val replacers = Seq.fill(PortNumber)(ReplacementPolicy.fromString(cacheParams.replacer,nWays,nSets/PortNumber)) 316 val s1_victim_oh = ResultHoldBypass(data = VecInit(replacers.zipWithIndex.map{case (replacer, i) => UIntToOH(replacer.way(s1_req_vsetIdx(i)(highestIdxBit, 1)))}), valid = RegNext(s0_fire)) 317 318 319// when(s1_fire){ 320// // when (!(PopCount(s1_tag_match_vec(0)) <= 1.U && (PopCount(s1_tag_match_vec(1)) <= 1.U || !s1_double_line))) { 321// // printf("Multiple hit in main pipe\n") 322// // } 323// assert(PopCount(s1_tag_match_vec(0)) <= 1.U && (PopCount(s1_tag_match_vec(1)) <= 1.U || !s1_double_line), 324// "Multiple hit in main pipe, port0:is=%d,ptag=0x%x,vidx=0x%x,vaddr=0x%x port1:is=%d,ptag=0x%x,vidx=0x%x,vaddr=0x%x ", 325// PopCount(s1_tag_match_vec(0)) > 1.U,s1_req_ptags(0), get_idx(s1_req_vaddr(0)), s1_req_vaddr(0), 326// PopCount(s1_tag_match_vec(1)) > 1.U && s1_double_line, s1_req_ptags(1), get_idx(s1_req_vaddr(1)), s1_req_vaddr(1)) 327// } 328 329 ((replacers zip touch_sets) zip touch_ways).map{case ((r, s),w) => r.access(s,w)} 330 IPFReplacer.waymask := UIntToOH(replacers(0).way(IPFReplacer.vsetIdx)) 331 332 /** check ipf, get result at the same cycle */ 333 (0 until PortNumber).foreach { i => 334 toIPF(i).valid := tlb_valid_tmp(i) 335 toIPF(i).bits.paddr := s1_req_paddr(i) 336 } 337 val s1_ipf_hit = VecInit((0 until PortNumber).map(i => toIPF(i).valid && fromIPF(i).ipf_hit)) 338 val s1_ipf_hit_latch = VecInit((0 until PortNumber).map(i => holdReleaseLatch(valid = s1_ipf_hit(i), release = s1_fire, flush = false.B))) 339 val s1_ipf_data = VecInit((0 until PortNumber).map(i => ResultHoldBypass(data = fromIPF(i).cacheline, valid = s1_ipf_hit(i)))) 340 341 /** check in PIQ, if hit, wait until prefetch port hit */ 342 (0 until PortNumber).foreach { i => 343 toPIQ(i).valid := tlb_valid_tmp(i) 344 toPIQ(i).bits.paddr := s1_req_paddr(i) 345 } 346 val s1_piq_hit = VecInit((0 until PortNumber).map(i => toIPF(i).valid && fromPIQ(i).piq_hit)) 347 val s1_piq_hit_latch = VecInit((0 until PortNumber).map(i => holdReleaseLatch(valid = s1_piq_hit(i), release = s1_fire, flush = false.B))) 348 val wait_piq = VecInit((0 until PortNumber).map(i => toIPF(i).valid && fromPIQ(i).piq_hit && !fromPIQ(i).data_valid)) 349 val wait_piq_latch = VecInit((0 until PortNumber).map(i => holdReleaseLatch(valid = wait_piq(i), release = s1_fire || fromPIQ(i).data_valid, flush = false.B))) 350 val s1_piq_data = VecInit((0 until PortNumber).map(i => ResultHoldBypass(data = fromPIQ(i).cacheline, valid = (s1_piq_hit(i) || wait_piq_latch(i)) && fromPIQ(i).data_valid))) 351 352 val s1_wait = (0 until PortNumber).map(i => wait_piq_latch(i) && !fromPIQ(i).data_valid).reduce(_||_) 353 354 val s1_prefetch_hit = VecInit((0 until PortNumber).map(i => s1_ipf_hit_latch(i) || s1_piq_hit_latch(i))) 355 val s1_prefetch_hit_data = VecInit((0 until PortNumber).map(i => Mux(s1_ipf_hit_latch(i), s1_ipf_data(i), s1_piq_data(i)))) 356 357 s1_ready := s2_ready && tlbRespAllValid && !s1_wait || !s1_valid 358 s1_fire := s1_valid && tlbRespAllValid && s2_ready && !s1_wait 359 360 if (env.EnableDifftest) { 361 (0 until PortNumber).foreach { i => 362 val diffPIQ = DifftestModule(new DiffRefillEvent, dontCare = true) 363 diffPIQ.coreid := io.hartId 364 diffPIQ.index := (i + 7).U 365 if (i == 0) diffPIQ.valid := s1_fire && !s1_port_hit(i) && !s1_ipf_hit_latch(i) && s1_piq_hit_latch(i) && !tlbExcp(0) 366 else diffPIQ.valid := s1_fire && !s1_port_hit(i) && !s1_ipf_hit_latch(i) && s1_piq_hit_latch(i) && s1_double_line && !tlbExcp(0) && !tlbExcp(1) 367 diffPIQ.addr := s1_req_paddr(i) 368 diffPIQ.data := s1_piq_data(i).asTypeOf(diffPIQ.data) 369 } 370 } 371 372 /** <PERF> replace victim way number */ 373 374 (0 until nWays).map{ w => 375 XSPerfAccumulate("line_0_hit_way_" + Integer.toString(w, 10), s1_fire && s1_port_hit(0) && OHToUInt(s1_tag_match_vec(0)) === w.U) 376 } 377 378 (0 until nWays).map{ w => 379 XSPerfAccumulate("line_0_victim_way_" + Integer.toString(w, 10), s1_fire && !s1_port_hit(0) && OHToUInt(s1_victim_oh(0)) === w.U) 380 } 381 382 (0 until nWays).map{ w => 383 XSPerfAccumulate("line_1_hit_way_" + Integer.toString(w, 10), s1_fire && s1_double_line && s1_port_hit(1) && OHToUInt(s1_tag_match_vec(1)) === w.U) 384 } 385 386 (0 until nWays).map{ w => 387 XSPerfAccumulate("line_1_victim_way_" + Integer.toString(w, 10), s1_fire && s1_double_line && !s1_port_hit(1) && OHToUInt(s1_victim_oh(1)) === w.U) 388 } 389 390 XSPerfAccumulate("mainPipe_stage1_block_by_piq_cycles", s1_valid && s1_wait) 391 392 /** 393 ****************************************************************************** 394 * ICache Stage 2 395 * - send request to MSHR if ICache miss 396 * - generate secondary miss status/data registers 397 * - response to IFU 398 ****************************************************************************** 399 */ 400 401 /** s2 control */ 402 val s2_fetch_finish = Wire(Bool()) 403 404 val s2_valid = generatePipeControl(lastFire = s1_fire, thisFire = s2_fire, thisFlush = false.B, lastFlush = false.B) 405 val s2_miss_available = Wire(Bool()) 406 407 s2_ready := (s2_valid && s2_fetch_finish && !io.respStall) || (!s2_valid && s2_miss_available) 408 s2_fire := s2_valid && s2_fetch_finish && !io.respStall 409 410 /** s2 data */ 411 // val mmio = fromPMP.map(port => port.mmio) // TODO: handle it 412 val (s2_req_paddr , s2_req_vaddr) = (RegEnable(s1_req_paddr, s1_fire), RegEnable(s1_req_vaddr, s1_fire)) 413 val s2_req_vsetIdx = RegEnable(s1_req_vsetIdx, s1_fire) 414 val s2_req_ptags = RegEnable(s1_req_ptags, s1_fire) 415 val s2_only_first = RegEnable(s1_only_first, s1_fire) 416 val s2_double_line = RegEnable(s1_double_line, s1_fire) 417 val s2_hit = RegEnable(s1_hit , s1_fire) 418 val s2_port_hit = RegEnable(s1_port_hit, s1_fire) 419 val s2_bank_miss = RegEnable(s1_bank_miss, s1_fire) 420 val s2_waymask = RegEnable(s1_victim_oh, s1_fire) 421 val s2_tag_match_vec = RegEnable(s1_tag_match_vec, s1_fire) 422 val s2_prefetch_hit = RegEnable(s1_prefetch_hit, s1_fire) 423 val s2_prefetch_hit_data = RegEnable(s1_prefetch_hit_data, s1_fire) 424 val s2_prefetch_hit_in_ipf = RegEnable(s1_ipf_hit_latch, s1_fire) 425 val s2_prefetch_hit_in_piq = RegEnable(s1_piq_hit_latch, s1_fire) 426 427 val icacheMissStage = RegInit(VecInit(Seq.fill(numOfStage - 2)(0.B))) 428 icacheMissStage(0) := !s2_hit 429 430 assert(RegNext(!s2_valid || s2_req_paddr(0)(11,0) === s2_req_vaddr(0)(11,0), true.B)) 431 432 /** status imply that s2 is a secondary miss (no need to resend miss request) */ 433 val sec_meet_vec = Wire(Vec(2, Bool())) 434 val s2_fixed_hit_vec = VecInit((0 until 2).map(i => s2_port_hit(i) || s2_prefetch_hit(i) || sec_meet_vec(i))) 435 val s2_fixed_hit = (s2_valid && s2_fixed_hit_vec(0) && s2_fixed_hit_vec(1) && s2_double_line) || (s2_valid && s2_fixed_hit_vec(0) && !s2_double_line) 436 437 val s2_meta_errors = RegEnable(s1_meta_errors, s1_fire) 438 val s2_data_errorBits = RegEnable(s1_data_errorBits, s1_fire) 439 val s2_data_cacheline = RegEnable(s1_data_cacheline, s1_fire) 440 441 val s2_data_errors = Wire(Vec(PortNumber,Vec(nWays, Bool()))) 442 443 (0 until PortNumber).map{ i => 444 val read_datas = s2_data_cacheline(i).asTypeOf(Vec(nWays,Vec(dataCodeUnitNum, UInt(dataCodeUnit.W)))) 445 val read_codes = s2_data_errorBits(i).asTypeOf(Vec(nWays,Vec(dataCodeUnitNum, UInt(dataCodeBits.W)))) 446 val data_full_wayBits = VecInit((0 until nWays).map( w => 447 VecInit((0 until dataCodeUnitNum).map(u => 448 Cat(read_codes(w)(u), read_datas(w)(u)))))) 449 val data_error_wayBits = VecInit((0 until nWays).map( w => 450 VecInit((0 until dataCodeUnitNum).map(u => 451 cacheParams.dataCode.decode(data_full_wayBits(w)(u)).error )))) 452 if(i == 0){ 453 (0 until nWays).map{ w => 454 s2_data_errors(i)(w) := RegNext(RegNext(s1_fire)) && RegNext(data_error_wayBits(w)).reduce(_||_) 455 } 456 } else { 457 (0 until nWays).map{ w => 458 s2_data_errors(i)(w) := RegNext(RegNext(s1_fire)) && RegNext(RegNext(s1_double_line)) && RegNext(data_error_wayBits(w)).reduce(_||_) 459 } 460 } 461 } 462 463 val s2_parity_meta_error = VecInit((0 until PortNumber).map(i => s2_meta_errors(i).reduce(_||_) && io.csr_parity_enable)) 464 val s2_parity_data_error = VecInit((0 until PortNumber).map(i => s2_data_errors(i).reduce(_||_) && io.csr_parity_enable)) 465 val s2_parity_error = VecInit((0 until PortNumber).map(i => RegNext(s2_parity_meta_error(i)) || s2_parity_data_error(i))) 466 467 for(i <- 0 until PortNumber){ 468 io.errors(i).valid := RegNext(s2_parity_error(i) && RegNext(RegNext(s1_fire))) 469 io.errors(i).report_to_beu := RegNext(s2_parity_error(i) && RegNext(RegNext(s1_fire))) 470 io.errors(i).paddr := RegNext(RegNext(s2_req_paddr(i))) 471 io.errors(i).source := DontCare 472 io.errors(i).source.tag := RegNext(RegNext(s2_parity_meta_error(i))) 473 io.errors(i).source.data := RegNext(s2_parity_data_error(i)) 474 io.errors(i).source.l2 := false.B 475 io.errors(i).opType := DontCare 476 io.errors(i).opType.fetch := true.B 477 } 478 XSError(s2_parity_error.reduce(_||_) && RegNext(RegNext(s1_fire)), "ICache has parity error in MainPaipe!") 479 480 481 /** exception and pmp logic **/ 482 val s2_tlb_valid = VecInit((0 until PortNumber).map(i => ValidHold(s1_tlb_valid(i) && s1_fire, s2_fire, false.B))) 483 val pmpExcpAF = VecInit(Seq(fromPMP(0).instr && s2_tlb_valid(0), fromPMP(1).instr && s2_double_line && s2_tlb_valid(1))) 484 // exception information and mmio 485 // short delay exception signal 486 val s2_except_tlb_pf = RegEnable(tlbExcpPF, s1_fire) 487 val s2_except_tlb_af = RegEnable(tlbExcpAF, s1_fire) 488 // long delay exception signal 489 val s2_except_pmp_af = DataHoldBypass(pmpExcpAF, RegNext(s1_fire)) 490 491 val s2_except = VecInit(Seq(s2_except_tlb_pf(0) || s2_except_tlb_af(0), s2_double_line && (s2_except_tlb_pf(1) || s2_except_tlb_af(1)))) 492 val s2_has_except = s2_valid && s2_except.reduce(_||_) 493 val s2_mmio = s2_valid && DataHoldBypass(io.pmp(0).resp.mmio && !s2_except(0) && !s2_except_pmp_af(0), RegNext(s1_fire)).asBool() 494 // pmp port 495 io.pmp.zipWithIndex.map { case (p, i) => 496 p.req.valid := s2_valid && !missSwitchBit 497 p.req.bits.addr := s2_req_paddr(i) 498 p.req.bits.size := 3.U // TODO 499 p.req.bits.cmd := TlbCmd.exec 500 } 501 502 /*** cacheline miss logic ***/ 503 val wait_idle :: wait_queue_ready :: wait_send_req :: wait_two_resp :: wait_0_resp :: wait_1_resp :: wait_one_resp ::wait_finish :: wait_pmp_except :: Nil = Enum(9) 504 val wait_state = RegInit(wait_idle) 505 506// val port_miss_fix = VecInit(Seq(fromMSHR(0).fire() && !s2_port_hit(0), fromMSHR(1).fire() && s2_double_line && !s2_port_hit(1) )) 507 508 // secondary miss record registers 509 class MissSlot(implicit p: Parameters) extends ICacheBundle { 510 val m_vSetIdx = UInt(idxBits.W) 511 val m_pTag = UInt(tagBits.W) 512 val m_data = UInt(blockBits.W) 513 val m_corrupt = Bool() 514 } 515 516 val missSlot = Seq.fill(2)(RegInit(0.U.asTypeOf(new MissSlot))) 517 val m_invalid :: m_valid :: m_refilled :: m_flushed :: m_wait_sec_miss :: m_check_final ::Nil = Enum(6) 518 val missStateQueue = RegInit(VecInit(Seq.fill(2)(m_invalid)) ) 519 val reservedRefillData = Wire(Vec(2, UInt(blockBits.W))) 520 521 s2_miss_available := VecInit(missStateQueue.map(entry => entry === m_invalid || entry === m_wait_sec_miss)).reduce(_&&_) 522 523 // check miss slot 524 val fix_sec_miss = Wire(Vec(4, Bool())) 525 val sec_meet_0_miss = fix_sec_miss(0) || fix_sec_miss(2) 526 val sec_meet_1_miss = fix_sec_miss(1) || fix_sec_miss(3) 527 sec_meet_vec := VecInit(Seq(sec_meet_0_miss, sec_meet_1_miss)) 528 529 /*** miss/hit pattern: <Control Signal> only raise at the first cycle of s2_valid ***/ 530 val cacheline_0_hit = (s2_port_hit(0) || s2_prefetch_hit(0) || sec_meet_0_miss) 531 val cacheline_0_miss = !s2_port_hit(0) && !s2_prefetch_hit(0) && !sec_meet_0_miss 532 533 val cacheline_1_hit = (s2_port_hit(1) || s2_prefetch_hit(1) || sec_meet_1_miss) 534 val cacheline_1_miss = !s2_port_hit(1) && !s2_prefetch_hit(1) && !sec_meet_1_miss 535 536 val only_0_miss = RegNext(s1_fire) && cacheline_0_miss && !s2_double_line && !s2_has_except && !s2_mmio 537 val only_0_hit = RegNext(s1_fire) && cacheline_0_hit && !s2_double_line && !s2_mmio 538 val hit_0_hit_1 = RegNext(s1_fire) && cacheline_0_hit && cacheline_1_hit && s2_double_line && !s2_mmio 539 val hit_0_miss_1 = RegNext(s1_fire) && cacheline_0_hit && cacheline_1_miss && s2_double_line && !s2_has_except && !s2_mmio 540 val miss_0_hit_1 = RegNext(s1_fire) && cacheline_0_miss && cacheline_1_hit && s2_double_line && !s2_has_except && !s2_mmio 541 val miss_0_miss_1 = RegNext(s1_fire) && cacheline_0_miss && cacheline_1_miss && s2_double_line && !s2_has_except && !s2_mmio 542 543 val hit_0_except_1 = RegNext(s1_fire) && s2_double_line && !s2_except(0) && s2_except(1) && cacheline_0_hit 544 val miss_0_except_1 = RegNext(s1_fire) && s2_double_line && !s2_except(0) && s2_except(1) && cacheline_0_miss 545 val except_0 = RegNext(s1_fire) && s2_except(0) 546 547 /*** miss/hit pattern latch: <Control Signal> latch the miss/hit patter if pipeline stop ***/ 548 val only_0_miss_latch = holdReleaseLatch(valid = only_0_miss, release = s2_fire, flush = false.B) 549 val only_0_hit_latch = holdReleaseLatch(valid = only_0_hit, release = s2_fire, flush = false.B) 550 val hit_0_hit_1_latch = holdReleaseLatch(valid = hit_0_hit_1, release = s2_fire, flush = false.B) 551 val hit_0_miss_1_latch = holdReleaseLatch(valid = hit_0_miss_1, release = s2_fire, flush = false.B) 552 val miss_0_hit_1_latch = holdReleaseLatch(valid = miss_0_hit_1, release = s2_fire, flush = false.B) 553 val miss_0_miss_1_latch = holdReleaseLatch(valid = miss_0_miss_1, release = s2_fire, flush = false.B) 554 555 val hit_0_except_1_latch = holdReleaseLatch(valid = hit_0_except_1, release = s2_fire, flush = false.B) 556 val miss_0_except_1_latch = holdReleaseLatch(valid = miss_0_except_1, release = s2_fire, flush = false.B) 557 val except_0_latch = holdReleaseLatch(valid = except_0, release = s2_fire, flush = false.B) 558 559 /*** secondary miss judgment ***/ 560 def waitSecondComeIn(missState: UInt): Bool = (missState === m_wait_sec_miss) 561 562 def getMissSituat(slotNum : Int, missNum : Int ) :Bool = { 563 RegNext(s1_fire) && 564 RegNext(missSlot(slotNum).m_vSetIdx === s1_req_vsetIdx(missNum)) && 565 RegNext(missSlot(slotNum).m_pTag === s1_req_ptags(missNum)) && 566 !s2_port_hit(missNum) && !s2_prefetch_hit(missNum) && 567 waitSecondComeIn(missStateQueue(slotNum)) 568 } 569 570 /*** compare new req and last req saved in miss slot ***/ 571 val miss_0_s2_0 = getMissSituat(slotNum = 0, missNum = 0) 572 val miss_0_s2_1 = getMissSituat(slotNum = 0, missNum = 1) 573 val miss_1_s2_0 = getMissSituat(slotNum = 1, missNum = 0) 574 val miss_1_s2_1 = getMissSituat(slotNum = 1, missNum = 1) 575 576 val miss_0_s2_0_latch = holdReleaseLatch(valid = miss_0_s2_0, release = s2_fire, flush = false.B) 577 val miss_0_s2_1_latch = holdReleaseLatch(valid = miss_0_s2_1, release = s2_fire, flush = false.B) 578 val miss_1_s2_0_latch = holdReleaseLatch(valid = miss_1_s2_0, release = s2_fire, flush = false.B) 579 val miss_1_s2_1_latch = holdReleaseLatch(valid = miss_1_s2_1, release = s2_fire, flush = false.B) 580 581 val slot_0_solve = fix_sec_miss(0) || fix_sec_miss(1) 582 val slot_1_solve = fix_sec_miss(2) || fix_sec_miss(3) 583 val slot_slove = VecInit(Seq(slot_0_solve, slot_1_solve)) 584 fix_sec_miss := VecInit(Seq(miss_0_s2_0_latch, miss_0_s2_1_latch, miss_1_s2_0_latch, miss_1_s2_1_latch)) 585 586 /*** reserved data for secondary miss ***/ 587 reservedRefillData(0) := DataHoldBypass(data = missSlot(0).m_data, valid = miss_0_s2_0 || miss_0_s2_1) 588 reservedRefillData(1) := DataHoldBypass(data = missSlot(1).m_data, valid = miss_1_s2_0 || miss_1_s2_1) 589 590 /*** miss state machine ***/ 591 592 //deal with not-cache-hit pmp af 593 val only_pmp_af = Wire(Vec(2, Bool())) 594 only_pmp_af(0) := s2_except_pmp_af(0) && cacheline_0_miss && !s2_except(0) && s2_valid 595 only_pmp_af(1) := s2_except_pmp_af(1) && cacheline_1_miss && !s2_except(1) && s2_valid && s2_double_line 596 597 switch(wait_state){ 598 is(wait_idle){ 599 when(only_pmp_af(0) || only_pmp_af(1) || s2_mmio){ 600 //should not send req to MissUnit when there is an access exception in PMP 601 //But to avoid using pmp exception in control signal (like s2_fire), should delay 1 cycle. 602 //NOTE: pmp exception cache line also could hit in ICache, but the result is meaningless. Just give the exception signals. 603 wait_state := wait_finish 604 }.elsewhen(miss_0_except_1_latch){ 605 wait_state := Mux(toMSHR(0).ready, wait_queue_ready ,wait_idle ) 606 }.elsewhen(only_0_miss_latch || miss_0_hit_1_latch){ 607 wait_state := Mux(toMSHR(0).ready, wait_queue_ready ,wait_idle ) 608 }.elsewhen(hit_0_miss_1_latch){ 609 wait_state := Mux(toMSHR(1).ready, wait_queue_ready ,wait_idle ) 610 }.elsewhen(miss_0_miss_1_latch ){ 611 wait_state := Mux(toMSHR(0).ready && toMSHR(1).ready, wait_queue_ready ,wait_idle) 612 } 613 } 614 615 is(wait_queue_ready){ 616 wait_state := wait_send_req 617 } 618 619 is(wait_send_req) { 620 when(miss_0_except_1_latch || only_0_miss_latch || hit_0_miss_1_latch || miss_0_hit_1_latch){ 621 wait_state := wait_one_resp 622 }.elsewhen( miss_0_miss_1_latch ){ 623 wait_state := wait_two_resp 624 } 625 } 626 627 is(wait_one_resp) { 628 when( (miss_0_except_1_latch ||only_0_miss_latch || miss_0_hit_1_latch) && fromMSHR(0).fire()){ 629 wait_state := wait_finish 630 }.elsewhen( hit_0_miss_1_latch && fromMSHR(1).fire()){ 631 wait_state := wait_finish 632 } 633 } 634 635 is(wait_two_resp) { 636 when(fromMSHR(0).fire() && fromMSHR(1).fire()){ 637 wait_state := wait_finish 638 }.elsewhen( !fromMSHR(0).fire() && fromMSHR(1).fire() ){ 639 wait_state := wait_0_resp 640 }.elsewhen(fromMSHR(0).fire() && !fromMSHR(1).fire()){ 641 wait_state := wait_1_resp 642 } 643 } 644 645 is(wait_0_resp) { 646 when(fromMSHR(0).fire()){ 647 wait_state := wait_finish 648 } 649 } 650 651 is(wait_1_resp) { 652 when(fromMSHR(1).fire()){ 653 wait_state := wait_finish 654 } 655 } 656 657 is(wait_finish) {when(s2_fire) {wait_state := wait_idle } 658 } 659 } 660 661 662 /*** send request to MissUnit ***/ 663 664 (0 until 2).map { i => 665 if(i == 1) toMSHR(i).valid := (hit_0_miss_1_latch || miss_0_miss_1_latch) && wait_state === wait_queue_ready && !s2_mmio 666 else toMSHR(i).valid := (only_0_miss_latch || miss_0_hit_1_latch || miss_0_miss_1_latch || miss_0_except_1_latch) && wait_state === wait_queue_ready && !s2_mmio 667 toMSHR(i).bits.paddr := s2_req_paddr(i) 668 toMSHR(i).bits.vaddr := s2_req_vaddr(i) 669 toMSHR(i).bits.waymask := s2_waymask(i) 670 671 672 when(toMSHR(i).fire() && missStateQueue(i) === m_invalid){ 673 missStateQueue(i) := m_valid 674 missSlot(i).m_vSetIdx := s2_req_vsetIdx(i) 675 missSlot(i).m_pTag := get_phy_tag(s2_req_paddr(i)) 676 } 677 678 when(fromMSHR(i).fire() && missStateQueue(i) === m_valid ){ 679 missStateQueue(i) := m_refilled 680 missSlot(i).m_data := fromMSHR(i).bits.data 681 missSlot(i).m_corrupt := fromMSHR(i).bits.corrupt 682 } 683 684 685 when(s2_fire && missStateQueue(i) === m_refilled){ 686 missStateQueue(i) := m_wait_sec_miss 687 } 688 689 /*** Only the first cycle to check whether meet the secondary miss ***/ 690 when(missStateQueue(i) === m_wait_sec_miss){ 691 /*** The seondary req has been fix by this slot and another also hit || the secondary req for other cacheline and hit ***/ 692 when((slot_slove(i) && s2_fire) || (!slot_slove(i) && s2_fire) ) { 693 missStateQueue(i) := m_invalid 694 } 695 /*** The seondary req has been fix by this slot but another miss/f3 not ready || the seondary req for other cacheline and miss ***/ 696 .elsewhen((slot_slove(i) && !s2_fire && s2_valid) || (s2_valid && !slot_slove(i) && !s2_fire) ){ 697 missStateQueue(i) := m_check_final 698 } 699 } 700 701 when(missStateQueue(i) === m_check_final && toMSHR(i).fire()){ 702 missStateQueue(i) := m_valid 703 missSlot(i).m_vSetIdx := s2_req_vsetIdx(i) 704 missSlot(i).m_pTag := get_phy_tag(s2_req_paddr(i)) 705 }.elsewhen(missStateQueue(i) === m_check_final) { 706 missStateQueue(i) := m_invalid 707 } 708 } 709 710 when(toMSHR.map(_.valid).reduce(_||_)){ 711 missSwitchBit := true.B 712 }.elsewhen(missSwitchBit && s2_fetch_finish){ 713 missSwitchBit := false.B 714 } 715 716 (0 until PortNumber).foreach{ 717 i => 718 mainPipeMissInfo(i).valid := missStateQueue(i) =/= m_invalid 719 mainPipeMissInfo(i).bits.vSetIdx := missSlot(i).m_vSetIdx 720 mainPipeMissInfo(i).bits.ptage := missSlot(i).m_pTag 721 } 722 723 val miss_all_fix = wait_state === wait_finish 724 725 s2_fetch_finish := ((s2_valid && s2_fixed_hit) || miss_all_fix || hit_0_except_1_latch || except_0_latch) 726 727 /** update replacement status register: 0 is hit access/ 1 is miss access */ 728 (touch_ways zip touch_sets).zipWithIndex.map{ case((t_w,t_s), i) => 729 t_s(0) := s2_req_vsetIdx(i)(highestIdxBit, 1) 730 t_w(0).valid := s2_valid && s2_port_hit(i) 731 t_w(0).bits := OHToUInt(s2_tag_match_vec(i)) 732 733 t_s(1) := s2_req_vsetIdx(i)(highestIdxBit, 1) 734 t_w(1).valid := s2_valid && !s2_port_hit(i) 735 t_w(1).bits := OHToUInt(s2_waymask(i)) 736 } 737 738 //** use hit one-hot select data 739 val s2_hit_datas = VecInit(s2_data_cacheline.zipWithIndex.map { case(bank, i) => 740 val port_hit_data = Mux1H(s2_tag_match_vec(i).asUInt, bank) 741 port_hit_data 742 }) 743 744 val s2_register_datas = Wire(Vec(2, UInt(blockBits.W))) 745 746 s2_register_datas.zipWithIndex.map{case(bank,i) => 747 // if(i == 0) bank := Mux(s2_port_hit(i), s2_hit_datas(i), Mux(miss_0_s2_0_latch,reservedRefillData(0), Mux(miss_1_s2_0_latch,reservedRefillData(1), missSlot(0).m_data))) 748 // else bank := Mux(s2_port_hit(i), s2_hit_datas(i), Mux(miss_0_s2_1_latch,reservedRefillData(0), Mux(miss_1_s2_1_latch,reservedRefillData(1), missSlot(1).m_data))) 749 if(i == 0) bank := Mux(miss_0_s2_0_latch,reservedRefillData(0), Mux(miss_1_s2_0_latch,reservedRefillData(1), missSlot(0).m_data)) 750 else bank := Mux(miss_0_s2_1_latch,reservedRefillData(0), Mux(miss_1_s2_1_latch,reservedRefillData(1), missSlot(1).m_data)) 751 } 752 753 /** response to IFU */ 754 755 (0 until PortNumber).map{ i => 756 if(i ==0) toIFU(i).valid := s2_fire 757 else toIFU(i).valid := s2_fire && s2_double_line 758 //when select is high, use sramData. Otherwise, use registerData. 759 toIFU(i).bits.registerData := s2_register_datas(i) 760 toIFU(i).bits.sramData := Mux(s2_port_hit(i), s2_hit_datas(i), s2_prefetch_hit_data(i)) 761 toIFU(i).bits.select := s2_port_hit(i) || s2_prefetch_hit(i) 762 toIFU(i).bits.paddr := s2_req_paddr(i) 763 toIFU(i).bits.vaddr := s2_req_vaddr(i) 764 toIFU(i).bits.tlbExcp.pageFault := s2_except_tlb_pf(i) 765 toIFU(i).bits.tlbExcp.accessFault := s2_except_tlb_af(i) || missSlot(i).m_corrupt || s2_except_pmp_af(i) 766 toIFU(i).bits.tlbExcp.mmio := s2_mmio 767 768 when(RegNext(s2_fire && missSlot(i).m_corrupt)){ 769 io.errors(i).valid := true.B 770 io.errors(i).report_to_beu := false.B // l2 should have report that to bus error unit, no need to do it again 771 io.errors(i).paddr := RegNext(s2_req_paddr(i)) 772 io.errors(i).source.tag := false.B 773 io.errors(i).source.data := false.B 774 io.errors(i).source.l2 := true.B 775 } 776 } 777 io.fetch.topdownIcacheMiss := !s2_hit 778 io.fetch.topdownItlbMiss := itlbMissStage(0) 779 780 (0 until 2).map {i => 781 XSPerfAccumulate("port_" + i + "_only_hit_in_ipf", !s2_port_hit(i) && s2_prefetch_hit(i) && s2_fire) 782 } 783 784 /** s2 mainPipe miss info */ 785 // mainPipeMissInfo.s2_miss_info(0).valid := s2_valid && (miss_0_hit_1_latch || miss_0_miss_1_latch || only_0_miss_latch || miss_0_except_1_latch) && !except_0_latch 786 // mainPipeMissInfo.s2_miss_info(1).valid := s2_valid && (miss_0_miss_1_latch || hit_0_miss_1_latch) 787 // (0 until 2).foreach { i => 788 // mainPipeMissInfo.s2_miss_info(i).bits.vSetIdx := s2_req_vsetIdx(i) 789 // mainPipeMissInfo.s2_miss_info(i).bits.ptage := s2_req_ptags(i) 790 // } 791 792 io.perfInfo.only_0_hit := only_0_hit_latch 793 io.perfInfo.only_0_miss := only_0_miss_latch 794 io.perfInfo.hit_0_hit_1 := hit_0_hit_1_latch 795 io.perfInfo.hit_0_miss_1 := hit_0_miss_1_latch 796 io.perfInfo.miss_0_hit_1 := miss_0_hit_1_latch 797 io.perfInfo.miss_0_miss_1 := miss_0_miss_1_latch 798 io.perfInfo.hit_0_except_1 := hit_0_except_1_latch 799 io.perfInfo.miss_0_except_1 := miss_0_except_1_latch 800 io.perfInfo.except_0 := except_0_latch 801 io.perfInfo.bank_hit(0) := only_0_miss_latch || hit_0_hit_1_latch || hit_0_miss_1_latch || hit_0_except_1_latch 802 io.perfInfo.bank_hit(1) := miss_0_hit_1_latch || hit_0_hit_1_latch 803 io.perfInfo.hit := hit_0_hit_1_latch || only_0_hit_latch || hit_0_except_1_latch || except_0_latch 804 805 /** <PERF> fetch bubble generated by icache miss*/ 806 807 XSPerfAccumulate("icache_bubble_s2_miss", s2_valid && !s2_fetch_finish ) 808 809 // TODO: this perf is wrong! 810 val tlb_miss_vec = VecInit((0 until PortNumber).map(i => toITLB(i).valid && s0_can_go && fromITLB(i).bits.miss)) 811 val tlb_has_miss = tlb_miss_vec.reduce(_ || _) 812 XSPerfAccumulate("icache_bubble_s0_tlb_miss", s0_valid && tlb_has_miss ) 813 814 if (env.EnableDifftest) { 815 val discards = (0 until PortNumber).map { i => 816 val discard = toIFU(i).bits.tlbExcp.pageFault || toIFU(i).bits.tlbExcp.accessFault || toIFU(i).bits.tlbExcp.mmio 817 discard 818 } 819 (0 until PortNumber).map { i => 820 val diffMainPipeOut = DifftestModule(new DiffRefillEvent, dontCare = true) 821 diffMainPipeOut.coreid := io.hartId 822 diffMainPipeOut.index := (4 + i).U 823 if (i == 0) diffMainPipeOut.valid := s2_fire && !discards(0) 824 else diffMainPipeOut.valid := s2_fire && s2_double_line && !discards(0) && !discards(1) 825 diffMainPipeOut.addr := s2_req_paddr(i) 826 when (toIFU(i).bits.select.asBool) { 827 diffMainPipeOut.data := toIFU(i).bits.sramData.asTypeOf(diffMainPipeOut.data) 828 } .otherwise { 829 diffMainPipeOut.data := toIFU(i).bits.registerData.asTypeOf(diffMainPipeOut.data) 830 } 831 // idtfr: 1 -> data from icache 2 -> data from ipf 3 -> data from piq 4 -> data from missUnit 832 when (s2_port_hit(i)) { diffMainPipeOut.idtfr := 1.U } 833 .elsewhen(s2_prefetch_hit(i)) { 834 when (s2_prefetch_hit_in_ipf(i)) { diffMainPipeOut.idtfr := 2.U } 835 .elsewhen(s2_prefetch_hit_in_piq(i)) { diffMainPipeOut.idtfr := 3.U } 836 .otherwise { XSWarn(true.B, "should not in this situation\n")} 837 } 838 .otherwise { diffMainPipeOut.idtfr := 4.U } 839 diffMainPipeOut 840 } 841 } 842} 843