1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.mem 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import utility._ 24import xiangshan.ExceptionNO._ 25import xiangshan._ 26import xiangshan.backend.Bundles.{DynInst, MemExuInput, MemExuOutput} 27import xiangshan.backend.fu.PMPRespBundle 28import xiangshan.backend.fu.FuConfig._ 29import xiangshan.backend.ctrlblock.{DebugLsInfoBundle, LsTopdownInfo} 30import xiangshan.backend.rob.RobPtr 31import xiangshan.cache._ 32import xiangshan.cache.wpu.ReplayCarry 33import xiangshan.cache.mmu.{TlbCmd, TlbReq, TlbRequestIO, TlbResp} 34import xiangshan.mem.mdp._ 35 36class LoadToLsqReplayIO(implicit p: Parameters) extends XSBundle with HasDCacheParameters { 37 // mshr refill index 38 val mshr_id = UInt(log2Up(cfg.nMissEntries).W) 39 // get full data from store queue and sbuffer 40 val full_fwd = Bool() 41 // wait for data from store inst's store queue index 42 val data_inv_sq_idx = new SqPtr 43 // wait for address from store queue index 44 val addr_inv_sq_idx = new SqPtr 45 // replay carry 46 val rep_carry = new ReplayCarry(nWays) 47 // data in last beat 48 val last_beat = Bool() 49 // replay cause 50 val cause = Vec(LoadReplayCauses.allCauses, Bool()) 51 // performance debug information 52 val debug = new PerfDebugInfo 53 54 // alias 55 def mem_amb = cause(LoadReplayCauses.C_MA) 56 def tlb_miss = cause(LoadReplayCauses.C_TM) 57 def fwd_fail = cause(LoadReplayCauses.C_FF) 58 def dcache_rep = cause(LoadReplayCauses.C_DR) 59 def dcache_miss = cause(LoadReplayCauses.C_DM) 60 def wpu_fail = cause(LoadReplayCauses.C_WF) 61 def bank_conflict = cause(LoadReplayCauses.C_BC) 62 def rar_nack = cause(LoadReplayCauses.C_RAR) 63 def raw_nack = cause(LoadReplayCauses.C_RAW) 64 def nuke = cause(LoadReplayCauses.C_NK) 65 def need_rep = cause.asUInt.orR 66} 67 68 69class LoadToLsqIO(implicit p: Parameters) extends XSBundle { 70 val ldin = DecoupledIO(new LqWriteBundle) 71 val uncache = Flipped(DecoupledIO(new MemExuOutput)) 72 val ld_raw_data = Input(new LoadDataFromLQBundle) 73 val forward = new PipeLoadForwardQueryIO 74 val stld_nuke_query = new LoadNukeQueryIO 75 val ldld_nuke_query = new LoadNukeQueryIO 76 val trigger = Flipped(new LqTriggerIO) 77} 78 79class LoadToLoadIO(implicit p: Parameters) extends XSBundle { 80 val valid = Bool() 81 val data = UInt(XLEN.W) // load to load fast path is limited to ld (64 bit) used as vaddr src1 only 82 val dly_ld_err = Bool() 83} 84 85class LoadUnitTriggerIO(implicit p: Parameters) extends XSBundle { 86 val tdata2 = Input(UInt(64.W)) 87 val matchType = Input(UInt(2.W)) 88 val tEnable = Input(Bool()) // timing is calculated before this 89 val addrHit = Output(Bool()) 90 val lastDataHit = Output(Bool()) 91} 92 93class LoadUnit(implicit p: Parameters) extends XSModule 94 with HasLoadHelper 95 with HasPerfEvents 96 with HasDCacheParameters 97 with HasCircularQueuePtrHelper 98 with HasVLSUParameters 99{ 100 val io = IO(new Bundle() { 101 // control 102 val redirect = Flipped(ValidIO(new Redirect)) 103 val csrCtrl = Flipped(new CustomCSRCtrlIO) 104 105 // int issue path 106 val ldin = Flipped(Decoupled(new MemExuInput)) 107 val ldout = Decoupled(new MemExuOutput) 108 109 // vec issue path 110 val vecldin = Flipped(Decoupled(new VecLoadPipeBundle)) 111 val vecldout = Decoupled(new VecExuOutput) 112 val vecReplay = Decoupled(new LsPipelineBundle) 113 114 // data path 115 val tlb = new TlbRequestIO(2) 116 val pmp = Flipped(new PMPRespBundle()) // arrive same to tlb now 117 val dcache = new DCacheLoadIO 118 val sbuffer = new LoadForwardQueryIO 119 val vec_forward = new LoadForwardQueryIO // forward from vec store flow queue 120 val lsq = new LoadToLsqIO 121 val tl_d_channel = Input(new DcacheToLduForwardIO) 122 val forward_mshr = Flipped(new LduToMissqueueForwardIO) 123 val refill = Flipped(ValidIO(new Refill)) 124 val l2_hint = Input(Valid(new L2ToL1Hint)) 125 126 // fast wakeup 127 // TODO: implement vector fast wakeup 128 val fast_uop = ValidIO(new DynInst) // early wakeup signal generated in load_s1, send to RS in load_s2 129 130 // trigger 131 val trigger = Vec(3, new LoadUnitTriggerIO) 132 133 // prefetch 134 val prefetch_train = ValidIO(new LdPrefetchTrainBundle()) // provide prefetch info to sms 135 val prefetch_train_l1 = ValidIO(new LdPrefetchTrainBundle()) // provide prefetch info to stream & stride 136 val prefetch_req = Flipped(ValidIO(new L1PrefetchReq)) // hardware prefetch to l1 cache req 137 val canAcceptLowConfPrefetch = Output(Bool()) 138 val canAcceptHighConfPrefetch = Output(Bool()) 139 140 // load to load fast path 141 val l2l_fwd_in = Input(new LoadToLoadIO) 142 val l2l_fwd_out = Output(new LoadToLoadIO) 143 144 val ld_fast_match = Input(Bool()) 145 val ld_fast_fuOpType = Input(UInt()) 146 val ld_fast_imm = Input(UInt(12.W)) 147 148 // rs feedback 149 val feedback_fast = ValidIO(new RSFeedback) // stage 2 150 val feedback_slow = ValidIO(new RSFeedback) // stage 3 151 val ldCancel = Output(new LoadCancelIO()) // use to cancel the uops waked by this load, and cancel load 152 153 // load ecc error 154 val s3_dly_ld_err = Output(Bool()) // Note that io.s3_dly_ld_err and io.lsq.s3_dly_ld_err is different 155 156 // schedule error query 157 val stld_nuke_query = Flipped(Vec(StorePipelineWidth, Valid(new StoreNukeQueryIO))) 158 159 // queue-based replay 160 val replay = Flipped(Decoupled(new LsPipelineBundle)) 161 val lq_rep_full = Input(Bool()) 162 163 // misc 164 val s2_ptr_chasing = Output(Bool()) // provide right pc for hw prefetch 165 166 // Load fast replay path 167 val fast_rep_in = Flipped(Decoupled(new LqWriteBundle)) 168 val fast_rep_out = Decoupled(new LqWriteBundle) 169 170 // perf 171 val debug_ls = Output(new DebugLsInfoBundle) 172 val lsTopdownInfo = Output(new LsTopdownInfo) 173 val correctMissTrain = Input(Bool()) 174 }) 175 176 val s1_ready, s2_ready, s3_ready = WireInit(false.B) 177 178 // Pipeline 179 // -------------------------------------------------------------------------------- 180 // stage 0 181 // -------------------------------------------------------------------------------- 182 // generate addr, use addr to query DCache and DTLB 183 val s0_valid = Wire(Bool()) 184 val s0_kill = Wire(Bool()) 185 val s0_vaddr = Wire(UInt(VAddrBits.W)) 186 val s0_mask = Wire(UInt((VLEN/8).W)) 187 val s0_uop = Wire(new DynInst) 188 val s0_has_rob_entry = Wire(Bool()) 189 val s0_rsIdx = Wire(UInt(log2Up(MemIQSizeMax).W)) 190 val s0_mshrid = Wire(UInt()) 191 val s0_try_l2l = Wire(Bool()) 192 val s0_rep_carry = Wire(new ReplayCarry(nWays)) 193 val s0_isFirstIssue = Wire(Bool()) 194 val s0_fast_rep = Wire(Bool()) 195 val s0_ld_rep = Wire(Bool()) 196 val s0_l2l_fwd = Wire(Bool()) 197 val s0_sched_idx = Wire(UInt()) 198 // Record the issue port idx of load issue queue. This signal is used by load cancel. 199 val s0_deqPortIdx = Wire(UInt(log2Ceil(LoadPipelineWidth).W)) 200 val s0_can_go = s1_ready 201 val s0_fire = s0_valid && s0_can_go 202 val s0_out = Wire(new LqWriteBundle) 203 204 // vector related ctrl signal 205 val s0_isvec = WireInit(false.B) 206 val s0_is128bit = WireInit(false.B) 207 val s0_uop_unit_stride_fof = WireInit(false.B) 208 // val s0_rob_idx_valid = WireInit(VecInit(Seq.fill(2)(false.B))) 209 // val s0_inner_idx = WireInit(VecInit(Seq.fill(2)(0.U(3.W)))) 210 // val s0_rob_idx = WireInit(VecInit(Seq.fill(2)(0.U.asTypeOf(new RobPtr)))) 211 val s0_reg_offset = WireInit(0.U(vOffsetBits.W)) 212 // val s0_offset = WireInit(VecInit(Seq.fill(2)(0.U(4.W)))) 213 val s0_exp = WireInit(true.B) 214 val s0_is_first_ele = WireInit(false.B) 215 val s0_flowPtr = WireInit(0.U.asTypeOf(new VlflowPtr)) 216 217 // load flow select/gen 218 // src0: super load replayed by LSQ (cache miss replay) (io.replay) 219 // src1: fast load replay (io.fast_rep_in) 220 // src2: load replayed by LSQ (io.replay) 221 // src3: hardware prefetch from prefetchor (high confidence) (io.prefetch) 222 // src4: int read / software prefetch first issue from RS (io.in) 223 // src5: vec read from RS (io.vecldin) 224 // src6: load try pointchaising when no issued or replayed load (io.fastpath) 225 // src7: hardware prefetch from prefetchor (high confidence) (io.prefetch) 226 // priority: high to low 227 val s0_rep_stall = io.ldin.valid && isAfter(io.replay.bits.uop.robIdx, io.ldin.bits.uop.robIdx) 228 val s0_super_ld_rep_valid = io.replay.valid && io.replay.bits.forward_tlDchannel 229 val s0_ld_fast_rep_valid = io.fast_rep_in.valid 230 val s0_ld_rep_valid = io.replay.valid && !io.replay.bits.forward_tlDchannel && !s0_rep_stall 231 val s0_high_conf_prf_valid = io.prefetch_req.valid && io.prefetch_req.bits.confidence > 0.U 232 val s0_int_iss_valid = io.ldin.valid // int flow first issue or software prefetch 233 val s0_vec_iss_valid = io.vecldin.valid 234 val s0_l2l_fwd_valid = io.l2l_fwd_in.valid && io.ld_fast_match 235 val s0_low_conf_prf_valid = io.prefetch_req.valid && io.prefetch_req.bits.confidence === 0.U 236 dontTouch(s0_super_ld_rep_valid) 237 dontTouch(s0_ld_fast_rep_valid) 238 dontTouch(s0_ld_rep_valid) 239 dontTouch(s0_high_conf_prf_valid) 240 dontTouch(s0_int_iss_valid) 241 dontTouch(s0_vec_iss_valid) 242 dontTouch(s0_l2l_fwd_valid) 243 dontTouch(s0_low_conf_prf_valid) 244 245 // load flow source ready 246 val s0_super_ld_rep_ready = WireInit(true.B) 247 val s0_ld_fast_rep_ready = !s0_super_ld_rep_valid 248 val s0_ld_rep_ready = !s0_super_ld_rep_valid && 249 !s0_ld_fast_rep_valid 250 val s0_high_conf_prf_ready = !s0_super_ld_rep_valid && 251 !s0_ld_fast_rep_valid && 252 !s0_ld_rep_valid 253 254 val s0_int_iss_ready = !s0_super_ld_rep_valid && 255 !s0_ld_fast_rep_valid && 256 !s0_ld_rep_valid && 257 !s0_high_conf_prf_valid 258 259 val s0_vec_iss_ready = !s0_super_ld_rep_valid && 260 !s0_ld_fast_rep_valid && 261 !s0_ld_rep_valid && 262 !s0_high_conf_prf_valid && 263 !s0_int_iss_valid 264 265 val s0_l2l_fwd_ready = !s0_super_ld_rep_valid && 266 !s0_ld_fast_rep_valid && 267 !s0_ld_rep_valid && 268 !s0_high_conf_prf_valid && 269 !s0_int_iss_valid && 270 !s0_vec_iss_valid 271 272 val s0_low_conf_prf_ready = !s0_super_ld_rep_valid && 273 !s0_ld_fast_rep_valid && 274 !s0_ld_rep_valid && 275 !s0_high_conf_prf_valid && 276 !s0_int_iss_valid && 277 !s0_vec_iss_valid && 278 !s0_l2l_fwd_valid 279 dontTouch(s0_super_ld_rep_ready) 280 dontTouch(s0_ld_fast_rep_ready) 281 dontTouch(s0_ld_rep_ready) 282 dontTouch(s0_high_conf_prf_ready) 283 dontTouch(s0_int_iss_ready) 284 dontTouch(s0_vec_iss_ready) 285 dontTouch(s0_l2l_fwd_ready) 286 dontTouch(s0_low_conf_prf_ready) 287 288 // load flow source select (OH) 289 val s0_super_ld_rep_select = s0_super_ld_rep_valid && s0_super_ld_rep_ready 290 val s0_ld_fast_rep_select = s0_ld_fast_rep_valid && s0_ld_fast_rep_ready 291 val s0_ld_rep_select = s0_ld_rep_valid && s0_ld_rep_ready 292 val s0_hw_prf_select = s0_high_conf_prf_ready && s0_high_conf_prf_valid || 293 s0_low_conf_prf_ready && s0_low_conf_prf_valid 294 val s0_int_iss_select = s0_int_iss_ready && s0_int_iss_valid 295 val s0_vec_iss_select = s0_vec_iss_ready && s0_vec_iss_valid 296 val s0_l2l_fwd_select = s0_l2l_fwd_ready && s0_l2l_fwd_valid 297 dontTouch(s0_super_ld_rep_select) 298 dontTouch(s0_ld_fast_rep_select) 299 dontTouch(s0_ld_rep_select) 300 dontTouch(s0_hw_prf_select) 301 dontTouch(s0_int_iss_select) 302 dontTouch(s0_vec_iss_select) 303 dontTouch(s0_l2l_fwd_select) 304 305 s0_valid := (s0_super_ld_rep_valid || 306 s0_ld_fast_rep_valid || 307 s0_ld_rep_valid || 308 s0_high_conf_prf_valid || 309 s0_int_iss_valid || 310 s0_vec_iss_valid || 311 s0_l2l_fwd_valid || 312 s0_low_conf_prf_valid) && io.dcache.req.ready && !s0_kill 313 314 // which is S0's out is ready and dcache is ready 315 val s0_try_ptr_chasing = s0_l2l_fwd_select 316 val s0_do_try_ptr_chasing = s0_try_ptr_chasing && s0_can_go && io.dcache.req.ready 317 val s0_ptr_chasing_vaddr = io.l2l_fwd_in.data(5, 0) +& io.ld_fast_imm(5, 0) 318 val s0_ptr_chasing_canceled = WireInit(false.B) 319 s0_kill := s0_ptr_chasing_canceled || (s0_out.uop.robIdx.needFlush(io.redirect) && !s0_try_ptr_chasing) 320 321 // prefetch related ctrl signal 322 val s0_prf = Wire(Bool()) 323 val s0_prf_rd = Wire(Bool()) 324 val s0_prf_wr = Wire(Bool()) 325 val s0_hw_prf = s0_hw_prf_select 326 327 io.canAcceptLowConfPrefetch := s0_low_conf_prf_ready 328 io.canAcceptHighConfPrefetch := s0_high_conf_prf_ready 329 330 // query DTLB 331 io.tlb.req.valid := s0_valid 332 io.tlb.req.bits.cmd := Mux(s0_prf, 333 Mux(s0_prf_wr, TlbCmd.write, TlbCmd.read), 334 TlbCmd.read 335 ) 336 io.tlb.req.bits.vaddr := Mux(s0_hw_prf_select, io.prefetch_req.bits.paddr, s0_vaddr) 337 io.tlb.req.bits.size := Mux(s0_isvec, io.vecldin.bits.alignedType, LSUOpType.size(s0_uop.fuOpType)) 338 io.tlb.req.bits.kill := s0_kill 339 io.tlb.req.bits.memidx.is_ld := true.B 340 io.tlb.req.bits.memidx.is_st := false.B 341 io.tlb.req.bits.memidx.idx := s0_uop.lqIdx.value 342 io.tlb.req.bits.debug.robIdx := s0_uop.robIdx 343 io.tlb.req.bits.no_translate := s0_hw_prf_select // hw b.reqetch addr does not need to be translated 344 io.tlb.req.bits.debug.pc := s0_uop.pc 345 io.tlb.req.bits.debug.isFirstIssue := s0_isFirstIssue 346 347 // query DCache 348 io.dcache.req.valid := s0_valid 349 io.dcache.req.bits.cmd := Mux(s0_prf_rd, 350 MemoryOpConstants.M_PFR, 351 Mux(s0_prf_wr, MemoryOpConstants.M_PFW, MemoryOpConstants.M_XRD) 352 ) 353 io.dcache.req.bits.vaddr := s0_vaddr 354 io.dcache.req.bits.mask := s0_mask 355 io.dcache.req.bits.data := DontCare 356 io.dcache.req.bits.isFirstIssue := s0_isFirstIssue 357 io.dcache.req.bits.instrtype := Mux(s0_prf, DCACHE_PREFETCH_SOURCE.U, LOAD_SOURCE.U) 358 io.dcache.req.bits.debug_robIdx := s0_uop.robIdx.value 359 io.dcache.req.bits.replayCarry := s0_rep_carry 360 // io.dcache.req.bits.is128bit := s0_is128bit 361 io.dcache.req.bits.id := DontCare // TODO: update cache meta 362 io.dcache.pf_source := Mux(s0_hw_prf_select, io.prefetch_req.bits.pf_source.value, L1_HW_PREFETCH_NULL) 363 364 // load flow priority mux 365 def fromNullSource() = { 366 s0_vaddr := 0.U 367 s0_mask := 0.U 368 s0_uop := 0.U.asTypeOf(new DynInst) 369 s0_try_l2l := false.B 370 s0_has_rob_entry := false.B 371 s0_rsIdx := 0.U 372 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 373 s0_mshrid := 0.U 374 s0_isFirstIssue := false.B 375 s0_fast_rep := false.B 376 s0_ld_rep := false.B 377 s0_l2l_fwd := false.B 378 s0_prf := false.B 379 s0_prf_rd := false.B 380 s0_prf_wr := false.B 381 s0_sched_idx := 0.U 382 s0_deqPortIdx := 0.U 383 } 384 385 def fromFastReplaySource(src: LqWriteBundle) = { 386 s0_vaddr := src.vaddr 387 s0_mask := src.mask 388 s0_uop := src.uop 389 s0_try_l2l := false.B 390 s0_has_rob_entry := src.hasROBEntry 391 s0_rep_carry := src.rep_info.rep_carry 392 s0_mshrid := src.rep_info.mshr_id 393 s0_rsIdx := src.rsIdx 394 s0_isFirstIssue := false.B 395 s0_fast_rep := true.B 396 s0_ld_rep := src.isLoadReplay 397 s0_l2l_fwd := false.B 398 s0_prf := LSUOpType.isPrefetch(src.uop.fuOpType) 399 s0_prf_rd := src.uop.fuOpType === LSUOpType.prefetch_r 400 s0_prf_wr := src.uop.fuOpType === LSUOpType.prefetch_w 401 s0_sched_idx := src.schedIndex 402 s0_deqPortIdx := src.deqPortIdx 403 } 404 405 def fromNormalReplaySource(src: LsPipelineBundle) = { 406 s0_vaddr := src.vaddr 407 s0_mask := genVWmask(src.vaddr, src.uop.fuOpType(1, 0)) 408 s0_uop := src.uop 409 s0_try_l2l := false.B 410 s0_has_rob_entry := true.B 411 s0_rsIdx := src.rsIdx 412 s0_rep_carry := src.replayCarry 413 s0_mshrid := src.mshrid 414 s0_isFirstIssue := false.B 415 s0_fast_rep := false.B 416 s0_ld_rep := true.B 417 s0_l2l_fwd := false.B 418 s0_prf := LSUOpType.isPrefetch(src.uop.fuOpType) 419 s0_prf_rd := src.uop.fuOpType === LSUOpType.prefetch_r 420 s0_prf_wr := src.uop.fuOpType === LSUOpType.prefetch_w 421 s0_sched_idx := src.schedIndex 422 s0_deqPortIdx := src.deqPortIdx 423 } 424 425 def fromPrefetchSource(src: L1PrefetchReq) = { 426 s0_vaddr := src.getVaddr() 427 s0_mask := 0.U 428 s0_uop := DontCare 429 s0_try_l2l := false.B 430 s0_has_rob_entry := false.B 431 s0_rsIdx := 0.U 432 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 433 s0_mshrid := 0.U 434 s0_isFirstIssue := false.B 435 s0_fast_rep := false.B 436 s0_ld_rep := false.B 437 s0_l2l_fwd := false.B 438 s0_prf := true.B 439 s0_prf_rd := !src.is_store 440 s0_prf_wr := src.is_store 441 s0_sched_idx := 0.U 442 s0_deqPortIdx := 0.U 443 } 444 445 def fromIntIssueSource(src: MemExuInput) = { 446 s0_vaddr := src.src(0) + SignExt(src.uop.imm(11, 0), VAddrBits) 447 s0_mask := genVWmask(s0_vaddr, src.uop.fuOpType(1,0)) 448 s0_uop := src.uop 449 s0_try_l2l := false.B 450 s0_has_rob_entry := true.B 451 s0_rsIdx := src.iqIdx 452 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 453 s0_mshrid := 0.U 454 s0_isFirstIssue := true.B 455 s0_fast_rep := false.B 456 s0_ld_rep := false.B 457 s0_l2l_fwd := false.B 458 s0_prf := LSUOpType.isPrefetch(src.uop.fuOpType) 459 s0_prf_rd := src.uop.fuOpType === LSUOpType.prefetch_r 460 s0_prf_wr := src.uop.fuOpType === LSUOpType.prefetch_w 461 s0_sched_idx := 0.U 462 s0_deqPortIdx := src.deqPortIdx 463 } 464 465 def fromVecIssueSource(src: VecLoadPipeBundle) = { 466 s0_vaddr := src.vaddr 467 s0_mask := src.mask 468 s0_uop := src.uop 469 s0_try_l2l := false.B 470 s0_has_rob_entry := true.B 471 // TODO: VLSU, implement vector feedback 472 s0_rsIdx := 0.U 473 // TODO: VLSU, implement replay carry 474 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 475 s0_mshrid := 0.U 476 // TODO: VLSU, implement first issue 477 s0_isFirstIssue := src.isFirstIssue 478 s0_fast_rep := false.B 479 s0_ld_rep := false.B 480 s0_l2l_fwd := false.B 481 s0_prf := false.B 482 s0_prf_rd := false.B 483 s0_prf_wr := false.B 484 s0_sched_idx := 0.U 485 // Vector load interface 486 s0_isvec := true.B 487 // vector loads only access a single element at a time, so 128-bit path is not used for now 488 s0_is128bit := false.B 489 s0_uop_unit_stride_fof := src.uop_unit_stride_fof 490 // s0_rob_idx_valid := src.rob_idx_valid 491 // s0_inner_idx := src.inner_idx 492 // s0_rob_idx := src.rob_idx 493 s0_reg_offset := src.reg_offset 494 // s0_offset := src.offset 495 s0_exp := src.exp 496 s0_is_first_ele := src.is_first_ele 497 s0_flowPtr := src.flowPtr 498 s0_deqPortIdx := 0.U 499 } 500 501 def fromLoadToLoadSource(src: LoadToLoadIO) = { 502 s0_vaddr := Cat(src.data(XLEN-1, 6), s0_ptr_chasing_vaddr(5,0)) 503 s0_mask := genVWmask(s0_vaddr, io.ld_fast_fuOpType(1, 0)) 504 // When there's no valid instruction from RS and LSQ, we try the load-to-load forwarding. 505 // Assume the pointer chasing is always ld. 506 s0_uop.fuOpType := io.ld_fast_fuOpType 507 s0_try_l2l := true.B 508 // we dont care s0_isFirstIssue and s0_rsIdx and s0_sqIdx and s0_deqPortIdx in S0 when trying pointchasing 509 // because these signals will be updated in S1 510 s0_has_rob_entry := false.B 511 s0_rsIdx := 0.U 512 s0_mshrid := 0.U 513 s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) 514 s0_isFirstIssue := true.B 515 s0_fast_rep := false.B 516 s0_ld_rep := false.B 517 s0_l2l_fwd := true.B 518 s0_prf := false.B 519 s0_prf_rd := false.B 520 s0_prf_wr := false.B 521 s0_sched_idx := 0.U 522 s0_deqPortIdx := 0.U 523 } 524 525 // set default 526 s0_uop := DontCare 527 when (s0_super_ld_rep_select) { fromNormalReplaySource(io.replay.bits) } 528 .elsewhen (s0_ld_fast_rep_select) { fromFastReplaySource(io.fast_rep_in.bits) } 529 .elsewhen (s0_ld_rep_select) { fromNormalReplaySource(io.replay.bits) } 530 .elsewhen (s0_hw_prf_select) { fromPrefetchSource(io.prefetch_req.bits) } 531 .elsewhen (s0_int_iss_select) { fromIntIssueSource(io.ldin.bits) } 532 .elsewhen (s0_vec_iss_select) { fromVecIssueSource(io.vecldin.bits) } 533 .otherwise { 534 if (EnableLoadToLoadForward) { 535 fromLoadToLoadSource(io.l2l_fwd_in) 536 } else { 537 fromNullSource() 538 } 539 } 540 541 // address align check 542 val s0_addr_aligned = LookupTree(Mux(s0_isvec, io.vecldin.bits.alignedType, s0_uop.fuOpType(1, 0)), List( 543 "b00".U -> true.B, //b 544 "b01".U -> (s0_vaddr(0) === 0.U), //h 545 "b10".U -> (s0_vaddr(1, 0) === 0.U), //w 546 "b11".U -> (s0_vaddr(2, 0) === 0.U) //d 547 )) 548 549 // accept load flow if dcache ready (tlb is always ready) 550 // TODO: prefetch need writeback to loadQueueFlag 551 s0_out := DontCare 552 s0_out.rsIdx := s0_rsIdx 553 s0_out.vaddr := s0_vaddr 554 s0_out.mask := s0_mask 555 s0_out.uop := s0_uop 556 s0_out.isFirstIssue := s0_isFirstIssue 557 s0_out.hasROBEntry := s0_has_rob_entry 558 s0_out.isPrefetch := s0_prf 559 s0_out.isHWPrefetch := s0_hw_prf 560 s0_out.isFastReplay := s0_fast_rep 561 s0_out.isLoadReplay := s0_ld_rep 562 s0_out.isFastPath := s0_l2l_fwd 563 s0_out.mshrid := s0_mshrid 564 s0_out.isvec := s0_isvec 565 s0_out.is128bit := s0_is128bit 566 s0_out.uop_unit_stride_fof := s0_uop_unit_stride_fof 567 // s0_out.rob_idx_valid := s0_rob_idx_valid 568 // s0_out.inner_idx := s0_inner_idx 569 // s0_out.rob_idx := s0_rob_idx 570 s0_out.reg_offset := s0_reg_offset 571 // s0_out.offset := s0_offset 572 s0_out.exp := s0_exp 573 s0_out.is_first_ele := s0_is_first_ele 574 s0_out.flowPtr := s0_flowPtr 575 s0_out.uop.exceptionVec(loadAddrMisaligned) := !s0_addr_aligned && s0_exp 576 s0_out.forward_tlDchannel := s0_super_ld_rep_select 577 when(io.tlb.req.valid && s0_isFirstIssue) { 578 s0_out.uop.debugInfo.tlbFirstReqTime := GTimer() 579 }.otherwise{ 580 s0_out.uop.debugInfo.tlbFirstReqTime := s0_uop.debugInfo.tlbFirstReqTime 581 } 582 s0_out.schedIndex := s0_sched_idx 583 s0_out.deqPortIdx := s0_deqPortIdx 584 585 // load fast replay 586 io.fast_rep_in.ready := (s0_can_go && io.dcache.req.ready && s0_ld_fast_rep_ready) 587 588 // load flow source ready 589 // cache missed load has highest priority 590 // always accept cache missed load flow from load replay queue 591 io.replay.ready := (s0_can_go && io.dcache.req.ready && (s0_ld_rep_ready && !s0_rep_stall || s0_super_ld_rep_select)) 592 593 // accept load flow from rs when: 594 // 1) there is no lsq-replayed load 595 // 2) there is no fast replayed load 596 // 3) there is no high confidence prefetch request 597 io.ldin.ready := s0_can_go && io.dcache.req.ready && s0_int_iss_ready 598 io.vecldin.ready := s0_can_go && io.dcache.req.ready && s0_vec_iss_ready 599 600 // for hw prefetch load flow feedback, to be added later 601 // io.prefetch_in.ready := s0_hw_prf_select 602 603 // dcache replacement extra info 604 // TODO: should prefetch load update replacement? 605 io.dcache.replacementUpdated := Mux(s0_ld_rep_select || s0_super_ld_rep_select, io.replay.bits.replacementUpdated, false.B) 606 607 XSDebug(io.dcache.req.fire, 608 p"[DCACHE LOAD REQ] pc ${Hexadecimal(s0_uop.pc)}, vaddr ${Hexadecimal(s0_vaddr)}\n" 609 ) 610 XSDebug(s0_valid, 611 p"S0: pc ${Hexadecimal(s0_out.uop.pc)}, lId ${Hexadecimal(s0_out.uop.lqIdx.asUInt)}, " + 612 p"vaddr ${Hexadecimal(s0_out.vaddr)}, mask ${Hexadecimal(s0_out.mask)}\n") 613 614 // Pipeline 615 // -------------------------------------------------------------------------------- 616 // stage 1 617 // -------------------------------------------------------------------------------- 618 // TLB resp (send paddr to dcache) 619 val s1_valid = RegInit(false.B) 620 val s1_in = Wire(new LqWriteBundle) 621 val s1_out = Wire(new LqWriteBundle) 622 val s1_kill = Wire(Bool()) 623 val s1_can_go = s2_ready 624 val s1_fire = s1_valid && !s1_kill && s1_can_go 625 val s1_exp = RegEnable(s0_out.exp, true.B, s0_fire) 626 val s1_isvec = RegEnable(s0_out.isvec, false.B, s0_fire) 627 val s1_vec_alignedType = RegEnable(io.vecldin.bits.alignedType, s0_fire) 628 629 s1_ready := !s1_valid || s1_kill || s2_ready 630 when (s0_fire) { s1_valid := true.B } 631 .elsewhen (s1_fire) { s1_valid := false.B } 632 .elsewhen (s1_kill) { s1_valid := false.B } 633 s1_in := RegEnable(s0_out, s0_fire) 634 635 val s1_fast_rep_dly_err = RegNext(io.fast_rep_in.bits.delayedLoadError) 636 val s1_fast_rep_kill = s1_fast_rep_dly_err && s1_in.isFastReplay 637 val s1_l2l_fwd_dly_err = RegNext(io.l2l_fwd_in.dly_ld_err) 638 val s1_l2l_fwd_kill = s1_l2l_fwd_dly_err && s1_in.isFastPath 639 val s1_late_kill = s1_fast_rep_kill || s1_l2l_fwd_kill 640 val s1_vaddr_hi = Wire(UInt()) 641 val s1_vaddr_lo = Wire(UInt()) 642 val s1_vaddr = Wire(UInt()) 643 val s1_paddr_dup_lsu = Wire(UInt()) 644 val s1_paddr_dup_dcache = Wire(UInt()) 645 val s1_exception = ExceptionNO.selectByFu(s1_out.uop.exceptionVec, LduCfg).asUInt.orR // af & pf exception were modified below. 646 val s1_tlb_miss = io.tlb.resp.bits.miss 647 val s1_prf = s1_in.isPrefetch 648 val s1_hw_prf = s1_in.isHWPrefetch 649 val s1_sw_prf = s1_prf && !s1_hw_prf 650 val s1_tlb_memidx = io.tlb.resp.bits.memidx 651 652 s1_vaddr_hi := s1_in.vaddr(VAddrBits - 1, 6) 653 s1_vaddr_lo := s1_in.vaddr(5, 0) 654 s1_vaddr := Cat(s1_vaddr_hi, s1_vaddr_lo) 655 s1_paddr_dup_lsu := io.tlb.resp.bits.paddr(0) 656 s1_paddr_dup_dcache := io.tlb.resp.bits.paddr(1) 657 658 when (s1_tlb_memidx.is_ld && io.tlb.resp.valid && !s1_tlb_miss && s1_tlb_memidx.idx === s1_in.uop.lqIdx.value) { 659 // printf("load idx = %d\n", s1_tlb_memidx.idx) 660 s1_out.uop.debugInfo.tlbRespTime := GTimer() 661 } 662 663 io.tlb.req_kill := s1_kill 664 io.tlb.resp.ready := true.B 665 666 io.dcache.s1_paddr_dup_lsu <> s1_paddr_dup_lsu 667 io.dcache.s1_paddr_dup_dcache <> s1_paddr_dup_dcache 668 io.dcache.s1_kill := s1_kill || s1_tlb_miss || s1_exception 669 670 // store to load forwarding 671 io.sbuffer.valid := s1_valid && !(s1_exception || s1_tlb_miss || s1_kill || s1_prf) 672 io.sbuffer.vaddr := s1_vaddr 673 io.sbuffer.paddr := s1_paddr_dup_lsu 674 io.sbuffer.uop := s1_in.uop 675 io.sbuffer.sqIdx := s1_in.uop.sqIdx 676 io.sbuffer.mask := s1_in.mask 677 io.sbuffer.pc := s1_in.uop.pc // FIXME: remove it 678 679 io.vec_forward.valid := s1_valid && !(s1_exception || s1_tlb_miss || s1_kill || s1_prf) 680 io.vec_forward.vaddr := s1_vaddr 681 io.vec_forward.paddr := s1_paddr_dup_lsu 682 io.vec_forward.uop := s1_in.uop 683 io.vec_forward.sqIdx := s1_in.uop.sqIdx 684 io.vec_forward.mask := s1_in.mask 685 io.vec_forward.pc := s1_in.uop.pc // FIXME: remove it 686 687 io.lsq.forward.valid := s1_valid && !(s1_exception || s1_tlb_miss || s1_kill || s1_prf) 688 io.lsq.forward.vaddr := s1_vaddr 689 io.lsq.forward.paddr := s1_paddr_dup_lsu 690 io.lsq.forward.uop := s1_in.uop 691 io.lsq.forward.sqIdx := s1_in.uop.sqIdx 692 io.lsq.forward.sqIdxMask := 0.U 693 io.lsq.forward.mask := s1_in.mask 694 io.lsq.forward.pc := s1_in.uop.pc // FIXME: remove it 695 696 // st-ld violation query 697 // val s1_nuke_paddr_match = VecInit((0 until StorePipelineWidth).map(w => {Mux(s1_isvec && s1_in.is128bit, 698 // s1_paddr_dup_lsu(PAddrBits-1, 4) === io.stld_nuke_query(w).bits.paddr(PAddrBits-1, 4), 699 // s1_paddr_dup_lsu(PAddrBits-1, 3) === io.stld_nuke_query(w).bits.paddr(PAddrBits-1, 3))})) 700 val s1_nuke = VecInit((0 until StorePipelineWidth).map(w => { 701 io.stld_nuke_query(w).valid && // query valid 702 isAfter(s1_in.uop.robIdx, io.stld_nuke_query(w).bits.robIdx) && // older store 703 (s1_paddr_dup_lsu(PAddrBits-1, 3) === io.stld_nuke_query(w).bits.paddr(PAddrBits-1, 3)) && // paddr match 704 (s1_in.mask & io.stld_nuke_query(w).bits.mask).orR // data mask contain 705 })).asUInt.orR && !s1_tlb_miss 706 707 s1_out := s1_in 708 s1_out.vaddr := s1_vaddr 709 s1_out.paddr := s1_paddr_dup_lsu 710 s1_out.tlbMiss := s1_tlb_miss 711 s1_out.ptwBack := io.tlb.resp.bits.ptwBack 712 s1_out.rsIdx := s1_in.rsIdx 713 s1_out.rep_info.debug := s1_in.uop.debugInfo 714 s1_out.rep_info.nuke := s1_nuke && !s1_sw_prf 715 s1_out.lateKill := s1_late_kill 716 717 when (!s1_late_kill) { 718 // current ori test will cause the case of ldest == 0, below will be modifeid in the future. 719 // af & pf exception were modified 720 s1_out.uop.exceptionVec(loadPageFault) := io.tlb.resp.bits.excp(0).pf.ld && s1_exp 721 s1_out.uop.exceptionVec(loadAccessFault) := io.tlb.resp.bits.excp(0).af.ld && s1_exp 722 } .otherwise { 723 s1_out.uop.exceptionVec(loadAddrMisaligned) := false.B && s1_exp 724 s1_out.uop.exceptionVec(loadAccessFault) := s1_late_kill && s1_exp 725 } 726 727 // pointer chasing 728 val s1_try_ptr_chasing = RegNext(s0_do_try_ptr_chasing, false.B) 729 val s1_ptr_chasing_vaddr = RegEnable(s0_ptr_chasing_vaddr, s0_do_try_ptr_chasing) 730 val s1_fu_op_type_not_ld = WireInit(false.B) 731 val s1_not_fast_match = WireInit(false.B) 732 val s1_addr_mismatch = WireInit(false.B) 733 val s1_addr_misaligned = WireInit(false.B) 734 val s1_ptr_chasing_canceled = WireInit(false.B) 735 val s1_cancel_ptr_chasing = WireInit(false.B) 736 737 s1_kill := s1_late_kill || 738 s1_cancel_ptr_chasing || 739 s1_in.uop.robIdx.needFlush(io.redirect) || 740 RegEnable(s0_kill, false.B, io.ldin.valid || io.replay.valid || io.l2l_fwd_in.valid || io.fast_rep_in.valid || io.vecldin.valid) 741 742 if (EnableLoadToLoadForward) { 743 // Sometimes, we need to cancel the load-load forwarding. 744 // These can be put at S0 if timing is bad at S1. 745 // Case 0: CACHE_SET(base + offset) != CACHE_SET(base) (lowest 6-bit addition has an overflow) 746 s1_addr_mismatch := s1_ptr_chasing_vaddr(6) || RegEnable(io.ld_fast_imm(11, 6).orR, s0_do_try_ptr_chasing) 747 // Case 1: the address is misaligned, kill s1 748 s1_addr_misaligned := LookupTree(s1_in.uop.fuOpType(1, 0), List( 749 "b00".U -> false.B, //b 750 "b01".U -> (s1_vaddr(0) =/= 0.U), //h 751 "b10".U -> (s1_vaddr(1, 0) =/= 0.U), //w 752 "b11".U -> (s1_vaddr(2, 0) =/= 0.U) //d 753 )) 754 // Case 2: this load-load uop is cancelled 755 s1_ptr_chasing_canceled := !io.ldin.valid 756 757 when (s1_try_ptr_chasing) { 758 s1_cancel_ptr_chasing := s1_addr_mismatch || s1_addr_misaligned || s1_ptr_chasing_canceled 759 760 s1_in.uop := io.ldin.bits.uop 761 s1_in.rsIdx := io.ldin.bits.iqIdx 762 s1_in.isFirstIssue := io.ldin.bits.isFirstIssue 763 s1_in.deqPortIdx := io.ldin.bits.deqPortIdx 764 s1_vaddr_lo := s1_ptr_chasing_vaddr(5, 0) 765 s1_paddr_dup_lsu := Cat(io.tlb.resp.bits.paddr(0)(PAddrBits - 1, 6), s1_vaddr_lo) 766 s1_paddr_dup_dcache := Cat(io.tlb.resp.bits.paddr(0)(PAddrBits - 1, 6), s1_vaddr_lo) 767 768 // recored tlb time when get the data to ensure the correctness of the latency calculation (although it should not record in here, because it does not use tlb) 769 s1_in.uop.debugInfo.tlbFirstReqTime := GTimer() 770 s1_in.uop.debugInfo.tlbRespTime := GTimer() 771 } 772 when (!s1_cancel_ptr_chasing) { 773 s0_ptr_chasing_canceled := s1_try_ptr_chasing && !io.replay.fire && !io.fast_rep_in.fire 774 when (s1_try_ptr_chasing) { 775 io.ldin.ready := true.B 776 } 777 } 778 } 779 780 // pre-calcuate sqIdx mask in s0, then send it to lsq in s1 for forwarding 781 val s1_sqIdx_mask = RegNext(UIntToMask(s0_out.uop.sqIdx.value, StoreQueueSize)) 782 // to enable load-load, sqIdxMask must be calculated based on ldin.uop 783 // If the timing here is not OK, load-load forwarding has to be disabled. 784 // Or we calculate sqIdxMask at RS?? 785 io.lsq.forward.sqIdxMask := s1_sqIdx_mask 786 if (EnableLoadToLoadForward) { 787 when (s1_try_ptr_chasing) { 788 io.lsq.forward.sqIdxMask := UIntToMask(io.ldin.bits.uop.sqIdx.value, StoreQueueSize) 789 } 790 } 791 792 io.forward_mshr.valid := s1_valid && s1_out.forward_tlDchannel 793 io.forward_mshr.mshrid := s1_out.mshrid 794 io.forward_mshr.paddr := s1_out.paddr 795 796 XSDebug(s1_valid, 797 p"S1: pc ${Hexadecimal(s1_out.uop.pc)}, lId ${Hexadecimal(s1_out.uop.lqIdx.asUInt)}, tlb_miss ${io.tlb.resp.bits.miss}, " + 798 p"paddr ${Hexadecimal(s1_out.paddr)}, mmio ${s1_out.mmio}\n") 799 800 // Pipeline 801 // -------------------------------------------------------------------------------- 802 // stage 2 803 // -------------------------------------------------------------------------------- 804 // s2: DCache resp 805 val s2_valid = RegInit(false.B) 806 val s2_in = Wire(new LqWriteBundle) 807 val s2_out = Wire(new LqWriteBundle) 808 val s2_kill = Wire(Bool()) 809 val s2_can_go = s3_ready 810 val s2_fire = s2_valid && !s2_kill && s2_can_go 811 val s2_exp = RegEnable(s1_out.exp, true.B, s1_fire) 812 val s2_isvec = RegEnable(s1_out.isvec, false.B, s1_fire) 813 val s2_vec_alignedType = RegEnable(s1_vec_alignedType, s1_fire) 814 815 s2_kill := s2_in.uop.robIdx.needFlush(io.redirect) 816 s2_ready := !s2_valid || s2_kill || s3_ready 817 when (s1_fire) { s2_valid := true.B } 818 .elsewhen (s2_fire) { s2_valid := false.B } 819 .elsewhen (s2_kill) { s2_valid := false.B } 820 s2_in := RegEnable(s1_out, s1_fire) 821 822 val s2_pmp = WireInit(io.pmp) 823 824 val s2_prf = s2_in.isPrefetch 825 val s2_hw_prf = s2_in.isHWPrefetch 826 827 // exception that may cause load addr to be invalid / illegal 828 // if such exception happen, that inst and its exception info 829 // will be force writebacked to rob 830 val s2_exception_vec = WireInit(s2_in.uop.exceptionVec) 831 when (!s2_in.lateKill) { 832 s2_exception_vec(loadAccessFault) := (s2_in.uop.exceptionVec(loadAccessFault) || s2_pmp.ld) && s2_exp 833 // soft prefetch will not trigger any exception (but ecc error interrupt may be triggered) 834 when (s2_prf || s2_in.tlbMiss) { 835 s2_exception_vec := 0.U.asTypeOf(s2_exception_vec.cloneType) 836 } 837 } 838 val s2_exception = ExceptionNO.selectByFu(s2_exception_vec, LduCfg).asUInt.orR && s2_exp 839 840 val (s2_fwd_frm_d_chan, s2_fwd_data_frm_d_chan) = io.tl_d_channel.forward(s1_valid && s1_out.forward_tlDchannel, s1_out.mshrid, s1_out.paddr) 841 val (s2_fwd_data_valid, s2_fwd_frm_mshr, s2_fwd_data_frm_mshr) = io.forward_mshr.forward() 842 val s2_fwd_frm_d_chan_or_mshr = s2_fwd_data_valid && (s2_fwd_frm_d_chan || s2_fwd_frm_mshr) 843 844 // writeback access fault caused by ecc error / bus error 845 // * ecc data error is slow to generate, so we will not use it until load stage 3 846 // * in load stage 3, an extra signal io.load_error will be used to 847 val s2_actually_mmio = s2_pmp.mmio 848 val s2_mmio = !s2_prf && 849 s2_actually_mmio && 850 !s2_exception && 851 !s2_in.tlbMiss 852 853 val s2_full_fwd = Wire(Bool()) 854 val s2_mem_amb = s2_in.uop.storeSetHit && 855 io.lsq.forward.addrInvalid 856 857 val s2_tlb_miss = s2_in.tlbMiss 858 val s2_fwd_fail = io.lsq.forward.dataInvalid || io.vec_forward.dataInvalid 859 val s2_dcache_miss = io.dcache.resp.bits.miss && 860 !s2_fwd_frm_d_chan_or_mshr && 861 !s2_full_fwd 862 863 val s2_mq_nack = io.dcache.s2_mq_nack && 864 !s2_fwd_frm_d_chan_or_mshr && 865 !s2_full_fwd 866 867 val s2_bank_conflict = io.dcache.s2_bank_conflict && 868 !s2_fwd_frm_d_chan_or_mshr && 869 !s2_full_fwd 870 871 val s2_wpu_pred_fail = io.dcache.s2_wpu_pred_fail && 872 !s2_fwd_frm_d_chan_or_mshr && 873 !s2_full_fwd 874 875 val s2_rar_nack = io.lsq.ldld_nuke_query.req.valid && 876 !io.lsq.ldld_nuke_query.req.ready 877 878 val s2_raw_nack = io.lsq.stld_nuke_query.req.valid && 879 !io.lsq.stld_nuke_query.req.ready 880 // st-ld violation query 881 // NeedFastRecovery Valid when 882 // 1. Fast recovery query request Valid. 883 // 2. Load instruction is younger than requestors(store instructions). 884 // 3. Physical address match. 885 // 4. Data contains. 886 val s2_nuke = VecInit((0 until StorePipelineWidth).map(w => { 887 io.stld_nuke_query(w).valid && // query valid 888 isAfter(s2_in.uop.robIdx, io.stld_nuke_query(w).bits.robIdx) && // older store 889 // TODO: Fix me when vector instruction 890 (s2_in.paddr(PAddrBits-1, 3) === io.stld_nuke_query(w).bits.paddr(PAddrBits-1, 3)) && // paddr match 891 (s2_in.mask & io.stld_nuke_query(w).bits.mask).orR // data mask contain 892 })).asUInt.orR && !s2_tlb_miss || s2_in.rep_info.nuke 893 894 val s2_cache_handled = io.dcache.resp.bits.handled 895 val s2_cache_tag_error = RegNext(io.csrCtrl.cache_error_enable) && 896 io.dcache.resp.bits.tag_error 897 898 val s2_troublem = !s2_exception && 899 !s2_mmio && 900 !s2_prf && 901 !s2_in.lateKill 902 903 io.dcache.resp.ready := true.B 904 val s2_dcache_should_resp = !(s2_in.tlbMiss || s2_exception || s2_mmio || s2_prf || s2_in.lateKill) 905 assert(!(s2_valid && (s2_dcache_should_resp && !io.dcache.resp.valid)), "DCache response got lost") 906 907 // fast replay require 908 val s2_dcache_fast_rep = (s2_mq_nack || !s2_dcache_miss && (s2_bank_conflict || s2_wpu_pred_fail)) 909 val s2_nuke_fast_rep = !s2_mq_nack && 910 !s2_dcache_miss && 911 !s2_bank_conflict && 912 !s2_wpu_pred_fail && 913 !s2_rar_nack && 914 !s2_raw_nack && 915 s2_nuke 916 917 val s2_fast_rep = !s2_mem_amb && 918 !s2_tlb_miss && 919 !s2_fwd_fail && 920 (s2_dcache_fast_rep || s2_nuke_fast_rep) && 921 s2_troublem 922 923 // need allocate new entry 924 val s2_can_query = !s2_mem_amb && 925 !s2_tlb_miss && 926 !s2_fwd_fail && 927 !s2_dcache_fast_rep && 928 s2_troublem 929 930 val s2_data_fwded = s2_dcache_miss && (s2_full_fwd || s2_cache_tag_error) 931 932 // ld-ld violation require 933 io.lsq.ldld_nuke_query.req.valid := s2_valid && s2_can_query 934 io.lsq.ldld_nuke_query.req.bits.uop := s2_in.uop 935 io.lsq.ldld_nuke_query.req.bits.mask := s2_in.mask 936 io.lsq.ldld_nuke_query.req.bits.paddr := s2_in.paddr 937 io.lsq.ldld_nuke_query.req.bits.data_valid := Mux(s2_full_fwd || s2_fwd_data_valid, true.B, !s2_dcache_miss) 938 939 // st-ld violation require 940 io.lsq.stld_nuke_query.req.valid := s2_valid && s2_can_query 941 io.lsq.stld_nuke_query.req.bits.uop := s2_in.uop 942 io.lsq.stld_nuke_query.req.bits.mask := s2_in.mask 943 io.lsq.stld_nuke_query.req.bits.paddr := s2_in.paddr 944 io.lsq.stld_nuke_query.req.bits.data_valid := Mux(s2_full_fwd || s2_fwd_data_valid, true.B, !s2_dcache_miss) 945 946 // merge forward result 947 // lsq has higher priority than sbuffer 948 val s2_fwd_mask = Wire(Vec((VLEN/8), Bool())) 949 val s2_fwd_data = Wire(Vec((VLEN/8), UInt(8.W))) 950 s2_full_fwd := ((~s2_fwd_mask.asUInt).asUInt & s2_in.mask) === 0.U && !io.lsq.forward.dataInvalid && !io.vec_forward.dataInvalid 951 // generate XLEN/8 Muxs 952 for (i <- 0 until VLEN / 8) { 953 s2_fwd_mask(i) := io.lsq.forward.forwardMask(i) || io.sbuffer.forwardMask(i) || io.vec_forward.forwardMask(i) 954 s2_fwd_data(i) := Mux( 955 io.lsq.forward.forwardMask(i), 956 io.lsq.forward.forwardData(i), 957 Mux( 958 io.vec_forward.forwardMask(i), 959 io.vec_forward.forwardData(i), 960 io.sbuffer.forwardData(i) 961 ) 962 ) 963 } 964 965 XSDebug(s2_fire, "[FWD LOAD RESP] pc %x fwd %x(%b) + %x(%b)\n", 966 s2_in.uop.pc, 967 io.lsq.forward.forwardData.asUInt, io.lsq.forward.forwardMask.asUInt, 968 s2_in.forwardData.asUInt, s2_in.forwardMask.asUInt 969 ) 970 971 // 972 s2_out := s2_in 973 s2_out.data := 0.U // data will be generated in load s3 974 s2_out.uop.fpWen := s2_in.uop.fpWen && !s2_exception 975 s2_out.mmio := s2_mmio 976 s2_out.uop.flushPipe := false.B 977 s2_out.uop.exceptionVec := s2_exception_vec 978 s2_out.forwardMask := s2_fwd_mask 979 s2_out.forwardData := s2_fwd_data 980 s2_out.handledByMSHR := s2_cache_handled 981 s2_out.miss := s2_dcache_miss && s2_troublem 982 s2_out.feedbacked := io.feedback_fast.valid 983 984 // Generate replay signal caused by: 985 // * st-ld violation check 986 // * tlb miss 987 // * dcache replay 988 // * forward data invalid 989 // * dcache miss 990 s2_out.rep_info.mem_amb := s2_mem_amb && s2_troublem 991 s2_out.rep_info.tlb_miss := s2_tlb_miss && s2_troublem 992 s2_out.rep_info.fwd_fail := s2_fwd_fail && s2_troublem 993 s2_out.rep_info.dcache_rep := s2_mq_nack && s2_troublem 994 s2_out.rep_info.dcache_miss := s2_dcache_miss && s2_troublem 995 s2_out.rep_info.bank_conflict := s2_bank_conflict && s2_troublem 996 s2_out.rep_info.wpu_fail := s2_wpu_pred_fail && s2_troublem 997 s2_out.rep_info.rar_nack := s2_rar_nack && s2_troublem 998 s2_out.rep_info.raw_nack := s2_raw_nack && s2_troublem 999 s2_out.rep_info.nuke := s2_nuke && s2_troublem 1000 s2_out.rep_info.full_fwd := s2_data_fwded 1001 s2_out.rep_info.data_inv_sq_idx := Mux(io.vec_forward.dataInvalid, s2_out.uop.sqIdx, io.lsq.forward.dataInvalidSqIdx) 1002 s2_out.rep_info.addr_inv_sq_idx := Mux(io.vec_forward.addrInvalid, s2_out.uop.sqIdx, io.lsq.forward.addrInvalidSqIdx) 1003 s2_out.rep_info.rep_carry := io.dcache.resp.bits.replayCarry 1004 s2_out.rep_info.mshr_id := io.dcache.resp.bits.mshr_id 1005 s2_out.rep_info.last_beat := s2_in.paddr(log2Up(refillBytes)) 1006 s2_out.rep_info.debug := s2_in.uop.debugInfo 1007 1008 // if forward fail, replay this inst from fetch 1009 val debug_fwd_fail_rep = s2_fwd_fail && !s2_troublem && !s2_in.tlbMiss 1010 // if ld-ld violation is detected, replay from this inst from fetch 1011 val debug_ldld_nuke_rep = false.B // s2_ldld_violation && !s2_mmio && !s2_is_prefetch && !s2_in.tlbMiss 1012 // io.out.bits.uop.replayInst := false.B 1013 1014 // to be removed 1015 io.feedback_fast.valid := s2_valid && // inst is valid 1016 !s2_in.isLoadReplay && // already feedbacked 1017 io.lq_rep_full && // LoadQueueReplay is full 1018 s2_out.rep_info.need_rep && // need replay 1019 !s2_exception && // no exception is triggered 1020 !s2_hw_prf && // not hardware prefetch 1021 !s2_isvec // not vector 1022 io.feedback_fast.bits.hit := false.B 1023 io.feedback_fast.bits.flushState := s2_in.ptwBack 1024 io.feedback_fast.bits.robIdx := s2_in.uop.robIdx 1025 io.feedback_fast.bits.sourceType := RSFeedbackType.lrqFull 1026 io.feedback_fast.bits.dataInvalidSqIdx := DontCare 1027 1028 io.ldCancel.ld1Cancel.valid := s2_valid && ( 1029 (s2_out.rep_info.need_rep && s2_out.isFirstIssue) || // exe fail and issued from IQ 1030 s2_mmio // is mmio 1031 ) 1032 io.ldCancel.ld1Cancel.bits := s2_out.deqPortIdx 1033 1034 // fast wakeup 1035 io.fast_uop.valid := RegNext( 1036 !io.dcache.s1_disable_fast_wakeup && 1037 s1_valid && 1038 !s1_kill && 1039 !io.tlb.resp.bits.miss && 1040 !io.lsq.forward.dataInvalidFast 1041 ) && (s2_valid && !s2_out.rep_info.need_rep && !s2_mmio) && !s2_isvec 1042 io.fast_uop.bits := RegNext(s1_out.uop) 1043 1044 // 1045 io.s2_ptr_chasing := RegEnable(s1_try_ptr_chasing && !s1_cancel_ptr_chasing, false.B, s1_fire) 1046 1047 io.prefetch_train.valid := s2_valid && !s2_actually_mmio && !s2_in.tlbMiss 1048 io.prefetch_train.bits.fromLsPipelineBundle(s2_in) 1049 io.prefetch_train.bits.miss := io.dcache.resp.bits.miss // TODO: use trace with bank conflict? 1050 io.prefetch_train.bits.meta_prefetch := io.dcache.resp.bits.meta_prefetch 1051 io.prefetch_train.bits.meta_access := io.dcache.resp.bits.meta_access 1052 1053 1054 io.prefetch_train_l1.valid := s2_valid && !s2_actually_mmio 1055 io.prefetch_train_l1.bits.fromLsPipelineBundle(s2_in) 1056 io.prefetch_train_l1.bits.miss := io.dcache.resp.bits.miss 1057 io.prefetch_train_l1.bits.meta_prefetch := io.dcache.resp.bits.meta_prefetch 1058 io.prefetch_train_l1.bits.meta_access := io.dcache.resp.bits.meta_access 1059 if (env.FPGAPlatform){ 1060 io.dcache.s0_pc := DontCare 1061 io.dcache.s1_pc := DontCare 1062 io.dcache.s2_pc := DontCare 1063 }else{ 1064 io.dcache.s0_pc := s0_out.uop.pc 1065 io.dcache.s1_pc := s1_out.uop.pc 1066 io.dcache.s2_pc := s2_out.uop.pc 1067 } 1068 io.dcache.s2_kill := s2_pmp.ld || s2_actually_mmio || s2_kill 1069 1070 val s1_ld_left_fire = s1_valid && !s1_kill && s2_ready 1071 val s2_ld_valid_dup = RegInit(0.U(6.W)) 1072 s2_ld_valid_dup := 0x0.U(6.W) 1073 when (s1_ld_left_fire && !s1_out.isHWPrefetch) { s2_ld_valid_dup := 0x3f.U(6.W) } 1074 when (s1_kill || s1_out.isHWPrefetch) { s2_ld_valid_dup := 0x0.U(6.W) } 1075 assert(RegNext((s2_valid === s2_ld_valid_dup(0)) || RegNext(s1_out.isHWPrefetch))) 1076 1077 // Pipeline 1078 // -------------------------------------------------------------------------------- 1079 // stage 3 1080 // -------------------------------------------------------------------------------- 1081 // writeback and update load queue 1082 val s3_valid = RegNext(s2_valid && !s2_out.isHWPrefetch && !s2_out.uop.robIdx.needFlush(io.redirect)) 1083 val s3_in = RegEnable(s2_out, s2_fire) 1084 val s3_out = Wire(Valid(new MemExuOutput)) 1085 val s3_dcache_rep = RegEnable(s2_dcache_fast_rep && s2_troublem, false.B, s2_fire) 1086 val s3_ld_valid_dup = RegEnable(s2_ld_valid_dup, s2_fire) 1087 val s3_fast_rep = Wire(Bool()) 1088 val s3_troublem = RegNext(s2_troublem) 1089 val s3_kill = s3_in.uop.robIdx.needFlush(io.redirect) 1090 val s3_vecout = Wire(new OnlyVecExuOutput) 1091 val s3_exp = RegEnable(s2_out.exp, true.B, s2_fire) 1092 val s3_isvec = RegEnable(s2_out.isvec, false.B, s2_fire) 1093 val s3_vec_alignedType = RegEnable(s2_vec_alignedType, s2_fire) 1094 s3_ready := !s3_valid || s3_kill || io.ldout.ready 1095 1096 // forwrad last beat 1097 val (s3_fwd_frm_d_chan, s3_fwd_data_frm_d_chan) = io.tl_d_channel.forward(s2_valid && s2_out.forward_tlDchannel, s2_out.mshrid, s2_out.paddr) 1098 val s3_fwd_data_valid = RegEnable(s2_fwd_data_valid, false.B, s2_valid) 1099 val s3_fwd_frm_d_chan_valid = (s3_fwd_frm_d_chan && s3_fwd_data_valid && s3_in.handledByMSHR) 1100 val s3_nuke = VecInit((0 until StorePipelineWidth).map(w => { 1101 io.stld_nuke_query(w).valid && // query valid 1102 isAfter(s3_in.uop.robIdx, io.stld_nuke_query(w).bits.robIdx) && // older store 1103 // TODO: Fix me when vector instruction 1104 (s3_in.paddr(PAddrBits-1, 3) === io.stld_nuke_query(w).bits.paddr(PAddrBits-1, 3)) && // paddr match 1105 (s3_in.mask & io.stld_nuke_query(w).bits.mask).orR // data mask contain 1106 })).asUInt.orR && !s3_in.tlbMiss || s3_in.rep_info.nuke 1107 1108 1109 // s3 load fast replay 1110 io.fast_rep_out.valid := s3_valid && s3_fast_rep && !s3_in.uop.robIdx.needFlush(io.redirect) && !s3_isvec 1111 io.fast_rep_out.bits := s3_in 1112 1113 io.lsq.ldin.valid := s3_valid && (!s3_fast_rep || !io.fast_rep_out.ready) && !s3_in.feedbacked && !s3_in.lateKill && !s3_isvec 1114 io.lsq.ldin.bits := s3_in 1115 io.lsq.ldin.bits.miss := s3_in.miss && !s3_fwd_frm_d_chan_valid 1116 1117 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 1118 io.lsq.ldin.bits.data_wen_dup := s3_ld_valid_dup.asBools 1119 io.lsq.ldin.bits.replacementUpdated := io.dcache.resp.bits.replacementUpdated 1120 io.lsq.ldin.bits.missDbUpdated := RegNext(s2_fire && s2_in.hasROBEntry && !s2_in.tlbMiss && !s2_in.missDbUpdated) 1121 1122 val s3_dly_ld_err = 1123 if (EnableAccurateLoadError) { 1124 (s3_in.lateKill || io.dcache.resp.bits.error_delayed) && RegNext(io.csrCtrl.cache_error_enable) 1125 } else { 1126 WireInit(false.B) 1127 } 1128 io.s3_dly_ld_err := false.B // s3_dly_ld_err && s3_valid 1129 io.fast_rep_out.bits.delayedLoadError := s3_dly_ld_err 1130 io.lsq.ldin.bits.dcacheRequireReplay := s3_dcache_rep 1131 1132 val s3_vp_match_fail = RegNext(io.lsq.forward.matchInvalid || io.sbuffer.matchInvalid) && s3_troublem 1133 val s3_ldld_rep_inst = 1134 io.lsq.ldld_nuke_query.resp.valid && 1135 io.lsq.ldld_nuke_query.resp.bits.rep_frm_fetch && 1136 RegNext(io.csrCtrl.ldld_vio_check_enable) 1137 1138 val s3_rep_info = WireInit(s3_in.rep_info) 1139 s3_rep_info.dcache_miss := s3_in.rep_info.dcache_miss && !s3_fwd_frm_d_chan_valid && s3_troublem 1140 val s3_rep_frm_fetch = s3_vp_match_fail || s3_ldld_rep_inst 1141 val s3_sel_rep_cause = PriorityEncoderOH(s3_rep_info.cause.asUInt) 1142 val s3_force_rep = s3_sel_rep_cause(LoadReplayCauses.C_TM) && 1143 !s3_in.uop.exceptionVec(loadAddrMisaligned) && 1144 s3_troublem 1145 1146 val s3_exception = ExceptionNO.selectByFu(s3_in.uop.exceptionVec, LduCfg).asUInt.orR && s3_exp 1147 when ((s3_exception || s3_dly_ld_err || s3_rep_frm_fetch) && !s3_force_rep) { 1148 io.lsq.ldin.bits.rep_info.cause := 0.U.asTypeOf(s3_rep_info.cause.cloneType) 1149 } .otherwise { 1150 io.lsq.ldin.bits.rep_info.cause := VecInit(s3_sel_rep_cause.asBools) 1151 } 1152 1153 // Int load, if hit, will be writebacked at s3 1154 s3_out.valid := s3_valid && !io.lsq.ldin.bits.rep_info.need_rep && !s3_in.mmio 1155 s3_out.bits.uop := s3_in.uop 1156 s3_out.bits.uop.exceptionVec(loadAccessFault) := (s3_dly_ld_err || s3_in.uop.exceptionVec(loadAccessFault)) && s3_exp 1157 s3_out.bits.uop.replayInst := s3_rep_frm_fetch 1158 s3_out.bits.data := s3_in.data 1159 s3_out.bits.debug.isMMIO := s3_in.mmio 1160 s3_out.bits.debug.isPerfCnt := false.B 1161 s3_out.bits.debug.paddr := s3_in.paddr 1162 s3_out.bits.debug.vaddr := s3_in.vaddr 1163 // Vector load 1164 s3_vecout.isvec := s3_isvec 1165 s3_vecout.vecdata := 0.U // Data will be assigned later 1166 s3_vecout.mask := s3_in.mask 1167 // s3_vecout.rob_idx_valid := s3_in.rob_idx_valid 1168 // s3_vecout.inner_idx := s3_in.inner_idx 1169 // s3_vecout.rob_idx := s3_in.rob_idx 1170 // s3_vecout.offset := s3_in.offset 1171 s3_vecout.reg_offset := s3_in.reg_offset 1172 s3_vecout.exp := s3_exp 1173 s3_vecout.is_first_ele := s3_in.is_first_ele 1174 s3_vecout.uopQueuePtr := DontCare // uopQueuePtr is already saved in flow queue 1175 s3_vecout.flowPtr := s3_in.flowPtr 1176 s3_vecout.elemIdx := DontCare // elemIdx is already saved in flow queue 1177 s3_vecout.elemIdxInsideVd := DontCare 1178 1179 when (s3_force_rep) { 1180 s3_out.bits.uop.exceptionVec := 0.U.asTypeOf(s3_in.uop.exceptionVec.cloneType) 1181 } 1182 1183 /* <------- DANGEROUS: Don't change sequence here ! -------> */ 1184 1185 io.lsq.ldin.bits.uop := s3_out.bits.uop 1186 1187 val s3_revoke = s3_exception || io.lsq.ldin.bits.rep_info.need_rep 1188 io.lsq.ldld_nuke_query.revoke := s3_revoke 1189 io.lsq.stld_nuke_query.revoke := s3_revoke 1190 1191 // feedback slow 1192 s3_fast_rep := RegNext(s2_fast_rep) && 1193 !s3_in.feedbacked && 1194 !s3_in.lateKill && 1195 !s3_rep_frm_fetch && 1196 !s3_exception 1197 1198 val s3_fb_no_waiting = !s3_in.isLoadReplay && !(s3_fast_rep && io.fast_rep_out.ready) && !s3_in.feedbacked 1199 1200 // 1201 io.feedback_slow.valid := s3_valid && !s3_in.uop.robIdx.needFlush(io.redirect) && s3_fb_no_waiting 1202 io.feedback_slow.bits.hit := !io.lsq.ldin.bits.rep_info.need_rep || io.lsq.ldin.ready 1203 io.feedback_slow.bits.flushState := s3_in.ptwBack 1204 io.feedback_slow.bits.robIdx := s3_in.uop.robIdx 1205 io.feedback_slow.bits.sourceType := RSFeedbackType.lrqFull 1206 io.feedback_slow.bits.dataInvalidSqIdx := DontCare 1207 1208 io.ldCancel.ld2Cancel.valid := s3_valid && ( 1209 (io.lsq.ldin.bits.rep_info.need_rep && s3_in.isFirstIssue) || 1210 s3_in.mmio 1211 ) 1212 io.ldCancel.ld2Cancel.bits := s3_in.deqPortIdx 1213 1214 val s3_ld_wb_meta = Mux(s3_out.valid, s3_out.bits, io.lsq.uncache.bits) 1215 1216 // data from load queue refill 1217 val s3_ld_raw_data_frm_uncache = io.lsq.ld_raw_data 1218 val s3_merged_data_frm_uncache = s3_ld_raw_data_frm_uncache.mergedData() 1219 val s3_picked_data_frm_uncache = LookupTree(s3_ld_raw_data_frm_uncache.addrOffset, List( 1220 "b000".U -> s3_merged_data_frm_uncache(63, 0), 1221 "b001".U -> s3_merged_data_frm_uncache(63, 8), 1222 "b010".U -> s3_merged_data_frm_uncache(63, 16), 1223 "b011".U -> s3_merged_data_frm_uncache(63, 24), 1224 "b100".U -> s3_merged_data_frm_uncache(63, 32), 1225 "b101".U -> s3_merged_data_frm_uncache(63, 40), 1226 "b110".U -> s3_merged_data_frm_uncache(63, 48), 1227 "b111".U -> s3_merged_data_frm_uncache(63, 56) 1228 )) 1229 val s3_ld_data_frm_uncache = rdataHelper(s3_ld_raw_data_frm_uncache.uop, s3_picked_data_frm_uncache) 1230 1231 // data from dcache hit 1232 val s3_ld_raw_data_frm_cache = Wire(new LoadDataFromDcacheBundle) 1233 s3_ld_raw_data_frm_cache.respDcacheData := io.dcache.resp.bits.data_delayed 1234 s3_ld_raw_data_frm_cache.forwardMask := RegEnable(s2_fwd_mask, s2_valid) 1235 s3_ld_raw_data_frm_cache.forwardData := RegEnable(s2_fwd_data, s2_valid) 1236 s3_ld_raw_data_frm_cache.uop := RegEnable(s2_out.uop, s2_valid) 1237 s3_ld_raw_data_frm_cache.addrOffset := RegEnable(s2_out.paddr(3, 0), s2_valid) 1238 s3_ld_raw_data_frm_cache.forward_D := RegEnable(s2_fwd_frm_d_chan, false.B, s2_valid) || s3_fwd_frm_d_chan_valid 1239 s3_ld_raw_data_frm_cache.forwardData_D := Mux(s3_fwd_frm_d_chan_valid, s3_fwd_data_frm_d_chan, RegEnable(s2_fwd_data_frm_d_chan, s2_valid)) 1240 s3_ld_raw_data_frm_cache.forward_mshr := RegEnable(s2_fwd_frm_mshr, false.B, s2_valid) 1241 s3_ld_raw_data_frm_cache.forwardData_mshr := RegEnable(s2_fwd_data_frm_mshr, s2_valid) 1242 s3_ld_raw_data_frm_cache.forward_result_valid := RegEnable(s2_fwd_data_valid, false.B, s2_valid) 1243 1244 val s3_merged_data_frm_cache = s3_ld_raw_data_frm_cache.mergedData() 1245 val s3_picked_data_frm_cache = LookupTree(s3_ld_raw_data_frm_cache.addrOffset, List( 1246 "b0000".U -> s3_merged_data_frm_cache(63, 0), 1247 "b0001".U -> s3_merged_data_frm_cache(63, 8), 1248 "b0010".U -> s3_merged_data_frm_cache(63, 16), 1249 "b0011".U -> s3_merged_data_frm_cache(63, 24), 1250 "b0100".U -> s3_merged_data_frm_cache(63, 32), 1251 "b0101".U -> s3_merged_data_frm_cache(63, 40), 1252 "b0110".U -> s3_merged_data_frm_cache(63, 48), 1253 "b0111".U -> s3_merged_data_frm_cache(63, 56), 1254 "b1000".U -> s3_merged_data_frm_cache(127, 64), 1255 "b1001".U -> s3_merged_data_frm_cache(127, 72), 1256 "b1010".U -> s3_merged_data_frm_cache(127, 80), 1257 "b1011".U -> s3_merged_data_frm_cache(127, 88), 1258 "b1100".U -> s3_merged_data_frm_cache(127, 96), 1259 "b1101".U -> s3_merged_data_frm_cache(127, 104), 1260 "b1110".U -> s3_merged_data_frm_cache(127, 112), 1261 "b1111".U -> s3_merged_data_frm_cache(127, 120) 1262 )) 1263 val s3_ld_data_frm_cache = rdataHelper(s3_ld_raw_data_frm_cache.uop, s3_picked_data_frm_cache) 1264 1265 // FIXME: add 1 cycle delay ? 1266 io.lsq.uncache.ready := !s3_out.valid 1267 io.ldout.bits := s3_ld_wb_meta 1268 io.ldout.bits.data := Mux(s3_out.valid, s3_ld_data_frm_cache, s3_ld_data_frm_uncache) 1269 io.ldout.valid := !s3_vecout.isvec && 1270 (s3_out.valid && !s3_out.bits.uop.robIdx.needFlush(io.redirect) || 1271 io.lsq.uncache.valid && !io.lsq.uncache.bits.uop.robIdx.needFlush(io.redirect) && !s3_out.valid) 1272 1273 // vector output 1274 io.vecldout.bits.vec := s3_vecout 1275 // TODO: VLSU, uncache data logic 1276 val vecdata = rdataVecHelper(s3_vec_alignedType, s3_picked_data_frm_cache) 1277 io.vecldout.bits.vec.vecdata := vecdata 1278 io.vecldout.bits.data := 0.U 1279 // io.vecldout.bits.fflags := s3_out.bits.fflags 1280 // io.vecldout.bits.redirectValid := s3_out.bits.redirectValid 1281 // io.vecldout.bits.redirect := s3_out.bits.redirect 1282 io.vecldout.bits.debug := s3_out.bits.debug 1283 io.vecldout.bits.uop := s3_out.bits.uop 1284 io.vecldout.valid := s3_vecout.isvec && 1285 (s3_valid && !s3_out.bits.uop.robIdx.needFlush(io.redirect) || 1286 io.lsq.uncache.valid && !io.lsq.uncache.bits.uop.robIdx.needFlush(io.redirect) && !s3_out.valid) && 1287 !io.lsq.ldin.bits.rep_info.need_rep 1288 1289 io.vecReplay.valid := s3_vecout.isvec && s3_valid && !s3_out.bits.uop.robIdx.needFlush(io.redirect) && 1290 io.lsq.ldin.bits.rep_info.need_rep 1291 io.vecReplay.bits := DontCare 1292 io.vecReplay.bits.uop := s3_in.uop 1293 io.vecReplay.bits.vaddr := s3_in.vaddr 1294 io.vecReplay.bits.paddr := s3_in.paddr 1295 io.vecReplay.bits.mask := s3_in.mask 1296 io.vecReplay.bits.isvec := true.B 1297 io.vecReplay.bits.uop_unit_stride_fof := s3_in.uop_unit_stride_fof 1298 io.vecReplay.bits.reg_offset := s3_in.reg_offset 1299 io.vecReplay.bits.exp := s3_in.exp 1300 io.vecReplay.bits.is_first_ele := s3_in.is_first_ele 1301 io.vecReplay.bits.flowPtr := s3_in.flowPtr 1302 1303 // fast load to load forward 1304 io.l2l_fwd_out.valid := s3_out.valid && !s3_in.lateKill 1305 io.l2l_fwd_out.data := s3_ld_data_frm_cache 1306 io.l2l_fwd_out.dly_ld_err := s3_dly_ld_err // ecc delayed error 1307 1308 // trigger 1309 val last_valid_data = RegNext(RegEnable(io.ldout.bits.data, io.ldout.fire)) 1310 val hit_ld_addr_trig_hit_vec = Wire(Vec(3, Bool())) 1311 val lq_ld_addr_trig_hit_vec = io.lsq.trigger.lqLoadAddrTriggerHitVec 1312 (0 until 3).map{i => { 1313 val tdata2 = RegNext(io.trigger(i).tdata2) 1314 val matchType = RegNext(io.trigger(i).matchType) 1315 val tEnable = RegNext(io.trigger(i).tEnable) 1316 1317 hit_ld_addr_trig_hit_vec(i) := TriggerCmp(RegNext(s2_out.vaddr), tdata2, matchType, tEnable) 1318 io.trigger(i).addrHit := Mux(s3_out.valid, hit_ld_addr_trig_hit_vec(i), lq_ld_addr_trig_hit_vec(i)) 1319 io.trigger(i).lastDataHit := TriggerCmp(last_valid_data, tdata2, matchType, tEnable) 1320 }} 1321 io.lsq.trigger.hitLoadAddrTriggerHitVec := hit_ld_addr_trig_hit_vec 1322 1323 // FIXME: please move this part to LoadQueueReplay 1324 io.debug_ls := DontCare 1325 1326 // Topdown 1327 io.lsTopdownInfo.s1.robIdx := s1_in.uop.robIdx.value 1328 io.lsTopdownInfo.s1.vaddr_valid := s1_valid && s1_in.hasROBEntry 1329 io.lsTopdownInfo.s1.vaddr_bits := s1_vaddr 1330 io.lsTopdownInfo.s2.robIdx := s2_in.uop.robIdx.value 1331 io.lsTopdownInfo.s2.paddr_valid := s2_fire && s2_in.hasROBEntry && !s2_in.tlbMiss 1332 io.lsTopdownInfo.s2.paddr_bits := s2_in.paddr 1333 io.lsTopdownInfo.s2.first_real_miss := io.dcache.resp.bits.real_miss 1334 io.lsTopdownInfo.s2.cache_miss_en := s2_fire && s2_in.hasROBEntry && !s2_in.tlbMiss && !s2_in.missDbUpdated 1335 1336 // perf cnt 1337 XSPerfAccumulate("s0_in_valid", io.ldin.valid) 1338 XSPerfAccumulate("s0_in_block", io.ldin.valid && !io.ldin.fire) 1339 XSPerfAccumulate("s0_in_fire_first_issue", s0_valid && s0_isFirstIssue) 1340 XSPerfAccumulate("s0_lsq_fire_first_issue", io.replay.fire) 1341 XSPerfAccumulate("s0_ldu_fire_first_issue", io.ldin.fire && s0_isFirstIssue) 1342 XSPerfAccumulate("s0_fast_replay_issue", io.fast_rep_in.fire) 1343 XSPerfAccumulate("s0_stall_out", s0_valid && !s0_can_go) 1344 XSPerfAccumulate("s0_stall_dcache", s0_valid && !io.dcache.req.ready) 1345 XSPerfAccumulate("s0_addr_spec_success", s0_fire && s0_vaddr(VAddrBits-1, 12) === io.ldin.bits.src(0)(VAddrBits-1, 12)) 1346 XSPerfAccumulate("s0_addr_spec_failed", s0_fire && s0_vaddr(VAddrBits-1, 12) =/= io.ldin.bits.src(0)(VAddrBits-1, 12)) 1347 XSPerfAccumulate("s0_addr_spec_success_once", s0_fire && s0_vaddr(VAddrBits-1, 12) === io.ldin.bits.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 1348 XSPerfAccumulate("s0_addr_spec_failed_once", s0_fire && s0_vaddr(VAddrBits-1, 12) =/= io.ldin.bits.src(0)(VAddrBits-1, 12) && s0_isFirstIssue) 1349 XSPerfAccumulate("s0_forward_tl_d_channel", s0_out.forward_tlDchannel) 1350 XSPerfAccumulate("s0_hardware_prefetch_fire", s0_fire && s0_hw_prf_select) 1351 XSPerfAccumulate("s0_software_prefetch_fire", s0_fire && s0_prf && s0_int_iss_select) 1352 XSPerfAccumulate("s0_hardware_prefetch_blocked", io.prefetch_req.valid && !s0_hw_prf_select) 1353 XSPerfAccumulate("s0_hardware_prefetch_total", io.prefetch_req.valid) 1354 1355 XSPerfAccumulate("s1_in_valid", s1_valid) 1356 XSPerfAccumulate("s1_in_fire", s1_fire) 1357 XSPerfAccumulate("s1_in_fire_first_issue", s1_fire && s1_in.isFirstIssue) 1358 XSPerfAccumulate("s1_tlb_miss", s1_fire && s1_tlb_miss) 1359 XSPerfAccumulate("s1_tlb_miss_first_issue", s1_fire && s1_tlb_miss && s1_in.isFirstIssue) 1360 XSPerfAccumulate("s1_stall_out", s1_valid && !s1_can_go) 1361 XSPerfAccumulate("s1_late_kill", s1_valid && s1_fast_rep_kill) 1362 1363 XSPerfAccumulate("s2_in_valid", s2_valid) 1364 XSPerfAccumulate("s2_in_fire", s2_fire) 1365 XSPerfAccumulate("s2_in_fire_first_issue", s2_fire && s2_in.isFirstIssue) 1366 XSPerfAccumulate("s2_dcache_miss", s2_fire && io.dcache.resp.bits.miss) 1367 XSPerfAccumulate("s2_dcache_miss_first_issue", s2_fire && io.dcache.resp.bits.miss && s2_in.isFirstIssue) 1368 XSPerfAccumulate("s2_dcache_real_miss_first_issue", s2_fire && io.dcache.resp.bits.miss && s2_in.isFirstIssue) 1369 XSPerfAccumulate("s2_full_forward", s2_fire && s2_full_fwd) 1370 XSPerfAccumulate("s2_dcache_miss_full_forward", s2_fire && s2_dcache_miss) 1371 XSPerfAccumulate("s2_fwd_frm_d_can", s2_valid && s2_fwd_frm_d_chan) 1372 XSPerfAccumulate("s2_fwd_frm_d_chan_or_mshr", s2_valid && s2_fwd_frm_d_chan_or_mshr) 1373 XSPerfAccumulate("s2_stall_out", s2_fire && !s2_can_go) 1374 XSPerfAccumulate("s2_prefetch", s2_fire && s2_prf) 1375 XSPerfAccumulate("s2_prefetch_ignored", s2_fire && s2_prf && s2_mq_nack) // ignore prefetch for mshr full / miss req port conflict 1376 XSPerfAccumulate("s2_prefetch_miss", s2_fire && s2_prf && io.dcache.resp.bits.miss) // prefetch req miss in l1 1377 XSPerfAccumulate("s2_prefetch_hit", s2_fire && s2_prf && !io.dcache.resp.bits.miss) // prefetch req hit in l1 1378 XSPerfAccumulate("s2_prefetch_accept", s2_fire && s2_prf && io.dcache.resp.bits.miss && !s2_mq_nack) // prefetch a missed line in l1, and l1 accepted it 1379 XSPerfAccumulate("s2_forward_req", s2_fire && s2_in.forward_tlDchannel) 1380 XSPerfAccumulate("s2_successfully_forward_channel_D", s2_fire && s2_fwd_frm_d_chan && s2_fwd_data_valid) 1381 XSPerfAccumulate("s2_successfully_forward_mshr", s2_fire && s2_fwd_frm_mshr && s2_fwd_data_valid) 1382 1383 XSPerfAccumulate("s3_fwd_frm_d_chan", s3_valid && s3_fwd_frm_d_chan_valid) 1384 1385 XSPerfAccumulate("load_to_load_forward", s1_try_ptr_chasing && !s1_ptr_chasing_canceled) 1386 XSPerfAccumulate("load_to_load_forward_try", s1_try_ptr_chasing) 1387 XSPerfAccumulate("load_to_load_forward_fail", s1_cancel_ptr_chasing) 1388 XSPerfAccumulate("load_to_load_forward_fail_cancelled", s1_cancel_ptr_chasing && s1_ptr_chasing_canceled) 1389 XSPerfAccumulate("load_to_load_forward_fail_wakeup_mismatch", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && s1_not_fast_match) 1390 XSPerfAccumulate("load_to_load_forward_fail_op_not_ld", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && s1_fu_op_type_not_ld) 1391 XSPerfAccumulate("load_to_load_forward_fail_addr_align", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && !s1_fu_op_type_not_ld && s1_addr_misaligned) 1392 XSPerfAccumulate("load_to_load_forward_fail_set_mismatch", s1_cancel_ptr_chasing && !s1_ptr_chasing_canceled && !s1_not_fast_match && !s1_fu_op_type_not_ld && !s1_addr_misaligned && s1_addr_mismatch) 1393 1394 // bug lyq: some signals in perfEvents are no longer suitable for the current MemBlock design 1395 // hardware performance counter 1396 val perfEvents = Seq( 1397 ("load_s0_in_fire ", s0_fire ), 1398 ("load_to_load_forward ", s1_fire && s1_try_ptr_chasing && !s1_ptr_chasing_canceled ), 1399 ("stall_dcache ", s0_valid && s0_can_go && !io.dcache.req.ready ), 1400 ("load_s1_in_fire ", s0_fire ), 1401 ("load_s1_tlb_miss ", s1_fire && io.tlb.resp.bits.miss ), 1402 ("load_s2_in_fire ", s1_fire ), 1403 ("load_s2_dcache_miss ", s2_fire && io.dcache.resp.bits.miss ), 1404 ) 1405 generatePerfEvent() 1406 1407 when(io.ldout.fire){ 1408 XSDebug("ldout %x\n", io.ldout.bits.uop.pc) 1409 } 1410 // end 1411}