1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend 18 19import chipsalliance.rocketchip.config.Parameters 20import freechips.rocketchip.rocket.{RVCDecoder, ExpandedInstruction} 21import chisel3.{util, _} 22import chisel3.util._ 23import utils._ 24import utility._ 25import xiangshan._ 26import xiangshan.frontend.icache._ 27import xiangshan.backend.decode.isa.predecode.PreDecodeInst 28 29trait HasPdConst extends HasXSParameter with HasICacheParameters with HasIFUConst{ 30 def isRVC(inst: UInt) = (inst(1,0) =/= 3.U) 31 def isLink(reg:UInt) = reg === 1.U || reg === 5.U 32 def brInfo(instr: UInt) = { 33 val brType::Nil = ListLookup(instr, List(BrType.notCFI), PreDecodeInst.brTable) 34 val rd = Mux(isRVC(instr), instr(12), instr(11,7)) 35 val rs = Mux(isRVC(instr), Mux(brType === BrType.jal, 0.U, instr(11, 7)), instr(19, 15)) 36 val isCall = (brType === BrType.jal && !isRVC(instr) || brType === BrType.jalr) && isLink(rd) // Only for RV64 37 val isRet = brType === BrType.jalr && isLink(rs) && !isCall 38 List(brType, isCall, isRet) 39 } 40 def jal_offset(inst: UInt, rvc: Bool): UInt = { 41 val rvc_offset = Cat(inst(12), inst(8), inst(10, 9), inst(6), inst(7), inst(2), inst(11), inst(5, 3), 0.U(1.W)) 42 val rvi_offset = Cat(inst(31), inst(19, 12), inst(20), inst(30, 21), 0.U(1.W)) 43 val max_width = rvi_offset.getWidth 44 SignExt(Mux(rvc, SignExt(rvc_offset, max_width), SignExt(rvi_offset, max_width)), XLEN) 45 } 46 def br_offset(inst: UInt, rvc: Bool): UInt = { 47 val rvc_offset = Cat(inst(12), inst(6, 5), inst(2), inst(11, 10), inst(4, 3), 0.U(1.W)) 48 val rvi_offset = Cat(inst(31), inst(7), inst(30, 25), inst(11, 8), 0.U(1.W)) 49 val max_width = rvi_offset.getWidth 50 SignExt(Mux(rvc, SignExt(rvc_offset, max_width), SignExt(rvi_offset, max_width)), XLEN) 51 } 52 53 def NOP = "h4501".U(16.W) 54} 55 56object BrType { 57 def notCFI = "b00".U 58 def branch = "b01".U 59 def jal = "b10".U 60 def jalr = "b11".U 61 def apply() = UInt(2.W) 62} 63 64object ExcType { //TODO:add exctype 65 def notExc = "b000".U 66 def apply() = UInt(3.W) 67} 68 69class PreDecodeInfo extends Bundle { // 8 bit 70 val valid = Bool() 71 val isRVC = Bool() 72 val brType = UInt(2.W) 73 val isCall = Bool() 74 val isRet = Bool() 75 //val excType = UInt(3.W) 76 def isBr = brType === BrType.branch 77 def isJal = brType === BrType.jal 78 def isJalr = brType === BrType.jalr 79 def notCFI = brType === BrType.notCFI 80} 81 82class PreDecodeResp(implicit p: Parameters) extends XSBundle with HasPdConst { 83 val pd = Vec(PredictWidth, new PreDecodeInfo) 84 val hasHalfValid = Vec(PredictWidth, Bool()) 85 //val expInstr = Vec(PredictWidth, UInt(32.W)) 86 val instr = Vec(PredictWidth, UInt(32.W)) 87 val jumpOffset = Vec(PredictWidth, UInt(XLEN.W)) 88// val hasLastHalf = Bool() 89 val triggered = Vec(PredictWidth, new TriggerCf) 90} 91 92class PreDecode(implicit p: Parameters) extends XSModule with HasPdConst{ 93 val io = IO(new Bundle() { 94 val in = Input(new IfuToPreDecode) 95 val out = Output(new PreDecodeResp) 96 }) 97 98 val data = io.in.data 99// val lastHalfMatch = io.in.lastHalfMatch 100 val validStart, validEnd = Wire(Vec(PredictWidth, Bool())) 101 val h_validStart, h_validEnd = Wire(Vec(PredictWidth, Bool())) 102 103 val rawInsts = if (HasCExtension) VecInit((0 until PredictWidth).map(i => Cat(data(i+1), data(i)))) 104 else VecInit((0 until PredictWidth).map(i => data(i))) 105 106 for (i <- 0 until PredictWidth) { 107 val inst =WireInit(rawInsts(i)) 108 //val expander = Module(new RVCExpander) 109 val currentIsRVC = isRVC(inst) 110 val currentPC = io.in.pc(i) 111 //expander.io.in := inst 112 113 val brType::isCall::isRet::Nil = brInfo(inst) 114 val jalOffset = jal_offset(inst, currentIsRVC) 115 val brOffset = br_offset(inst, currentIsRVC) 116 117 //val lastIsValidEnd = if (i == 0) { !lastHalfMatch } else { validEnd(i-1) || !HasCExtension.B } 118 val lastIsValidEnd = if (i == 0) { true.B } else { validEnd(i-1) || !HasCExtension.B } 119 validStart(i) := (lastIsValidEnd || !HasCExtension.B) 120 validEnd(i) := validStart(i) && currentIsRVC || !validStart(i) || !HasCExtension.B 121 122 //prepared for last half match 123 //TODO if HasCExtension 124 val h_lastIsValidEnd = if (i == 0) { false.B } else { h_validEnd(i-1) || !HasCExtension.B } 125 h_validStart(i) := (h_lastIsValidEnd || !HasCExtension.B) 126 h_validEnd(i) := h_validStart(i) && currentIsRVC || !h_validStart(i) || !HasCExtension.B 127 128 io.out.hasHalfValid(i) := h_validStart(i) 129 130 io.out.triggered(i) := DontCare//VecInit(Seq.fill(10)(false.B)) 131 132 133 io.out.pd(i).valid := validStart(i) 134 io.out.pd(i).isRVC := currentIsRVC 135 io.out.pd(i).brType := brType 136 io.out.pd(i).isCall := isCall 137 io.out.pd(i).isRet := isRet 138 139 //io.out.expInstr(i) := expander.io.out.bits 140 io.out.instr(i) :=inst 141 io.out.jumpOffset(i) := Mux(io.out.pd(i).isBr, brOffset, jalOffset) 142 } 143 144// io.out.hasLastHalf := !io.out.pd(PredictWidth - 1).isRVC && io.out.pd(PredictWidth - 1).valid 145 146 for (i <- 0 until PredictWidth) { 147 XSDebug(true.B, 148 p"instr ${Hexadecimal(io.out.instr(i))}, " + 149 p"validStart ${Binary(validStart(i))}, " + 150 p"validEnd ${Binary(validEnd(i))}, " + 151 p"isRVC ${Binary(io.out.pd(i).isRVC)}, " + 152 p"brType ${Binary(io.out.pd(i).brType)}, " + 153 p"isRet ${Binary(io.out.pd(i).isRet)}, " + 154 p"isCall ${Binary(io.out.pd(i).isCall)}\n" 155 ) 156 } 157} 158 159class RVCExpander(implicit p: Parameters) extends XSModule { 160 val io = IO(new Bundle { 161 val in = Input(UInt(32.W)) 162 val out = Output(new ExpandedInstruction) 163 }) 164 165 if (HasCExtension) { 166 io.out := new RVCDecoder(io.in, XLEN).decode 167 } else { 168 io.out := new RVCDecoder(io.in, XLEN).passthrough 169 } 170} 171 172/* --------------------------------------------------------------------- 173 * Predict result check 174 * 175 * --------------------------------------------------------------------- 176 */ 177 178object FaultType { 179 def noFault = "b000".U 180 def jalFault = "b001".U //not CFI taken or invalid instruction taken 181 def retFault = "b010".U //not CFI taken or invalid instruction taken 182 def targetFault = "b011".U 183 def notCFIFault = "b100".U //not CFI taken or invalid instruction taken 184 def invalidTaken = "b101".U 185 def apply() = UInt(3.W) 186} 187 188class CheckInfo extends Bundle { // 8 bit 189 val value = UInt(3.W) 190 def isjalFault = value === FaultType.jalFault 191 def isRetFault = value === FaultType.retFault 192 def istargetFault = value === FaultType.targetFault 193 def invalidTakenFault = value === FaultType.invalidTaken 194 def notCFIFault = value === FaultType.notCFIFault 195} 196 197class PredCheckerResp(implicit p: Parameters) extends XSBundle with HasPdConst { 198 //to Ibuffer write port (stage 1) 199 val stage1Out = new Bundle{ 200 val fixedRange = Vec(PredictWidth, Bool()) 201 val fixedTaken = Vec(PredictWidth, Bool()) 202 } 203 //to Ftq write back port (stage 2) 204 val stage2Out = new Bundle{ 205 val fixedTarget = Vec(PredictWidth, UInt(VAddrBits.W)) 206 val jalTarget = Vec(PredictWidth, UInt(VAddrBits.W)) 207 val fixedMissPred = Vec(PredictWidth, Bool()) 208 val faultType = Vec(PredictWidth, new CheckInfo) 209 } 210} 211 212 213class PredChecker(implicit p: Parameters) extends XSModule with HasPdConst { 214 val io = IO( new Bundle{ 215 val in = Input(new IfuToPredChecker) 216 val out = Output(new PredCheckerResp) 217 }) 218 219 val (takenIdx, predTaken) = (io.in.ftqOffset.bits, io.in.ftqOffset.valid) 220 val predTarget = (io.in.target) 221 val (instrRange, instrValid) = (io.in.instrRange, io.in.instrValid) 222 val (pds, pc, jumpOffset) = (io.in.pds, io.in.pc, io.in.jumpOffset) 223 224 val jalFaultVec, retFaultVec, targetFault, notCFITaken, invalidTaken = Wire(Vec(PredictWidth, Bool())) 225 226 /** remask fault may appear together with other faults, but other faults are exclusive 227 * so other f ault mast use fixed mask to keep only one fault would be found and redirect to Ftq 228 * we first detecct remask fault and then use fixedRange to do second check 229 **/ 230 231 //Stage 1: detect remask fault 232 /** first check: remask Fault */ 233 jalFaultVec := VecInit(pds.zipWithIndex.map{case(pd, i) => pd.isJal && instrRange(i) && instrValid(i) && (takenIdx > i.U && predTaken || !predTaken) }) 234 retFaultVec := VecInit(pds.zipWithIndex.map{case(pd, i) => pd.isRet && instrRange(i) && instrValid(i) && (takenIdx > i.U && predTaken || !predTaken) }) 235 val remaskFault = VecInit((0 until PredictWidth).map(i => jalFaultVec(i) || retFaultVec(i))) 236 val remaskIdx = ParallelPriorityEncoder(remaskFault.asUInt) 237 val needRemask = ParallelOR(remaskFault) 238 val fixedRange = instrRange.asUInt & (Fill(PredictWidth, !needRemask) | Fill(PredictWidth, 1.U(1.W)) >> ~remaskIdx) 239 240 io.out.stage1Out.fixedRange := fixedRange.asTypeOf((Vec(PredictWidth, Bool()))) 241 242 io.out.stage1Out.fixedTaken := VecInit(pds.zipWithIndex.map{case(pd, i) => instrValid (i) && fixedRange(i) && (pd.isRet || pd.isJal || takenIdx === i.U && predTaken && !pd.notCFI) }) 243 244 /** second check: faulse prediction fault and target fault */ 245 notCFITaken := VecInit(pds.zipWithIndex.map{case(pd, i) => fixedRange(i) && instrValid(i) && i.U === takenIdx && pd.notCFI && predTaken }) 246 invalidTaken := VecInit(pds.zipWithIndex.map{case(pd, i) => fixedRange(i) && !instrValid(i) && i.U === takenIdx && predTaken }) 247 248 val jumpTargets = VecInit(pds.zipWithIndex.map{case(pd,i) => (pc(i) + jumpOffset(i)).asTypeOf(UInt(VAddrBits.W))}) 249 val seqTargets = VecInit((0 until PredictWidth).map(i => pc(i) + Mux(pds(i).isRVC || !instrValid(i), 2.U, 4.U ) )) 250 251 //Stage 2: detect target fault 252 /** target calculation: in the next stage */ 253 val fixedRangeNext = RegNext(fixedRange) 254 val instrValidNext = RegNext(instrValid) 255 val takenIdxNext = RegNext(takenIdx) 256 val predTakenNext = RegNext(predTaken) 257 val predTargetNext = RegNext(predTarget) 258 val jumpTargetsNext = RegNext(jumpTargets) 259 val seqTargetsNext = RegNext(seqTargets) 260 val pdsNext = RegNext(pds) 261 val jalFaultVecNext = RegNext(jalFaultVec) 262 val retFaultVecNext = RegNext(retFaultVec) 263 val notCFITakenNext = RegNext(notCFITaken) 264 val invalidTakenNext = RegNext(invalidTaken) 265 266 targetFault := VecInit(pdsNext.zipWithIndex.map{case(pd,i) => fixedRangeNext(i) && instrValidNext(i) && (pd.isJal || pd.isBr) && takenIdxNext === i.U && predTakenNext && (predTargetNext =/= jumpTargetsNext(i))}) 267 268 269 io.out.stage2Out.faultType.zipWithIndex.map{case(faultType, i) => faultType.value := Mux(jalFaultVecNext(i) , FaultType.jalFault , 270 Mux(retFaultVecNext(i), FaultType.retFault , 271 Mux(targetFault(i), FaultType.targetFault , 272 Mux(notCFITakenNext(i) , FaultType.notCFIFault, 273 Mux(invalidTakenNext(i), FaultType.invalidTaken, FaultType.noFault)))))} 274 275 io.out.stage2Out.fixedMissPred.zipWithIndex.map{case(missPred, i ) => missPred := jalFaultVecNext(i) || retFaultVecNext(i) || notCFITakenNext(i) || invalidTakenNext(i) || targetFault(i)} 276 io.out.stage2Out.fixedTarget.zipWithIndex.map{case(target, i) => target := Mux(jalFaultVecNext(i) || targetFault(i), jumpTargetsNext(i), seqTargetsNext(i) )} 277 io.out.stage2Out.jalTarget.zipWithIndex.map{case(target, i) => target := jumpTargetsNext(i) } 278 279} 280 281class FrontendTrigger(implicit p: Parameters) extends XSModule { 282 val io = IO(new Bundle(){ 283 val frontendTrigger = Input(new FrontendTdataDistributeIO) 284 val csrTriggerEnable = Input(Vec(4, Bool())) 285 val triggered = Output(Vec(PredictWidth, new TriggerCf)) 286 287 val pds = Input(Vec(PredictWidth, new PreDecodeInfo)) 288 val pc = Input(Vec(PredictWidth, UInt(VAddrBits.W))) 289 val data = if(HasCExtension) Input(Vec(PredictWidth + 1, UInt(16.W))) 290 else Input(Vec(PredictWidth, UInt(32.W))) 291 }) 292 293 val data = io.data 294 295 val rawInsts = if (HasCExtension) VecInit((0 until PredictWidth).map(i => Cat(data(i+1), data(i)))) 296 else VecInit((0 until PredictWidth).map(i => data(i))) 297 298 val tdata = RegInit(VecInit(Seq.fill(4)(0.U.asTypeOf(new MatchTriggerIO)))) 299 when(io.frontendTrigger.t.valid) { 300 tdata(io.frontendTrigger.t.bits.addr) := io.frontendTrigger.t.bits.tdata 301 } 302 io.triggered.map{i => i := 0.U.asTypeOf(new TriggerCf)} 303 val triggerEnable = RegInit(VecInit(Seq.fill(4)(false.B))) // From CSR, controlled by priv mode, etc. 304 triggerEnable := io.csrTriggerEnable 305 XSDebug(triggerEnable.asUInt.orR, "Debug Mode: At least one frontend trigger is enabled\n") 306 307 for (i <- 0 until 4) {PrintTriggerInfo(triggerEnable(i), tdata(i))} 308 309 for (i <- 0 until PredictWidth) { 310 val currentPC = io.pc(i) 311 val currentIsRVC = io.pds(i).isRVC 312 val inst = WireInit(rawInsts(i)) 313 val triggerHitVec = Wire(Vec(4, Bool())) 314 315 for (j <- 0 until 4) { 316 triggerHitVec(j) := Mux(tdata(j).select, TriggerCmp(Mux(currentIsRVC, inst(15, 0), inst), tdata(j).tdata2, tdata(j).matchType, triggerEnable(j)), 317 TriggerCmp(currentPC, tdata(j).tdata2, tdata(j).matchType, triggerEnable(j))) 318 } 319 320 // fix chains this could be moved further into the pipeline 321 io.triggered(i).frontendHit := triggerHitVec 322 val enableChain = tdata(0).chain 323 when(enableChain){ 324 io.triggered(i).frontendHit(0) := triggerHitVec(0) && triggerHitVec(1) && (tdata(0).timing === tdata(1).timing) 325 io.triggered(i).frontendHit(1) := triggerHitVec(0) && triggerHitVec(1) && (tdata(0).timing === tdata(1).timing) 326 } 327 for(j <- 0 until 2) { 328 io.triggered(i).backendEn(j) := Mux(tdata(j+2).chain, triggerHitVec(j+2), true.B) 329 io.triggered(i).frontendHit(j+2) := !tdata(j+2).chain && triggerHitVec(j+2) // temporary workaround 330 } 331 XSDebug(io.triggered(i).getHitFrontend, p"Debug Mode: Predecode Inst No. ${i} has trigger hit vec ${io.triggered(i).frontendHit}" + 332 p"and backend en ${io.triggered(i).backendEn}\n") 333 } 334} 335