xref: /XiangShan/src/main/scala/xiangshan/frontend/FrontendBundle.scala (revision a0c65233389cccd2fdffe58236fb0a7dedf6d54f)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16package xiangshan.frontend
17
18import chipsalliance.rocketchip.config.Parameters
19import chisel3._
20import chisel3.util._
21import chisel3.experimental.chiselName
22import xiangshan._
23import xiangshan.frontend.icache._
24import utils._
25import utility._
26import scala.math._
27import java.util.ResourceBundle.Control
28
29class FrontendTopDownBundle(implicit p: Parameters) extends XSBundle {
30  val reasons = Vec(TopDownCounters.NumStallReasons.id, Bool())
31  val stallWidth = UInt(log2Ceil(PredictWidth).W)
32}
33
34@chiselName
35class FetchRequestBundle(implicit p: Parameters) extends XSBundle with HasICacheParameters {
36
37  //fast path: Timing critical
38  val startAddr       = UInt(VAddrBits.W)
39  val nextlineStart   = UInt(VAddrBits.W)
40  val nextStartAddr   = UInt(VAddrBits.W)
41  //slow path
42  val ftqIdx          = new FtqPtr
43  val ftqOffset       = ValidUndirectioned(UInt(log2Ceil(PredictWidth).W))
44
45  val topdown_info    = new FrontendTopDownBundle
46
47  def crossCacheline =  startAddr(blockOffBits - 1) === 1.U
48
49  def fromFtqPcBundle(b: Ftq_RF_Components) = {
50    this.startAddr := b.startAddr
51    this.nextlineStart := b.nextLineAddr
52    when (b.fallThruError) {
53      val nextBlockHigherTemp = Mux(startAddr(log2Ceil(PredictWidth)+instOffsetBits), b.startAddr, b.nextLineAddr)
54      val nextBlockHigher = nextBlockHigherTemp(VAddrBits-1, log2Ceil(PredictWidth)+instOffsetBits+1)
55      this.nextStartAddr :=
56        Cat(nextBlockHigher,
57          startAddr(log2Ceil(PredictWidth)+instOffsetBits) ^ 1.U(1.W),
58          startAddr(log2Ceil(PredictWidth)+instOffsetBits-1, instOffsetBits),
59          0.U(instOffsetBits.W)
60        )
61    }
62    this
63  }
64  override def toPrintable: Printable = {
65    p"[start] ${Hexadecimal(startAddr)} [next] ${Hexadecimal(nextlineStart)}" +
66      p"[tgt] ${Hexadecimal(nextStartAddr)} [ftqIdx] $ftqIdx [jmp] v:${ftqOffset.valid}" +
67      p" offset: ${ftqOffset.bits}\n"
68  }
69}
70
71class FtqICacheInfo(implicit p: Parameters)extends XSBundle with HasICacheParameters{
72  val startAddr           = UInt(VAddrBits.W)
73  val nextlineStart       = UInt(VAddrBits.W)
74  def crossCacheline =  startAddr(blockOffBits - 1) === 1.U
75  def fromFtqPcBundle(b: Ftq_RF_Components) = {
76    this.startAddr := b.startAddr
77    this.nextlineStart := b.nextLineAddr
78    this
79  }
80}
81
82class IFUICacheIO(implicit p: Parameters)extends XSBundle with HasICacheParameters{
83  val icacheReady       = Output(Bool())
84  val resp              = Vec(PortNumber, ValidIO(new ICacheMainPipeResp))
85  val topdownIcacheMiss = Output(Bool())
86  val topdownItlbMiss = Output(Bool())
87}
88
89class FtqToICacheRequestBundle(implicit p: Parameters)extends XSBundle with HasICacheParameters{
90  val pcMemRead           = Vec(5, new FtqICacheInfo)
91  val readValid           = Vec(5, Bool())
92}
93
94
95class PredecodeWritebackBundle(implicit p:Parameters) extends XSBundle {
96  val pc           = Vec(PredictWidth, UInt(VAddrBits.W))
97  val pd           = Vec(PredictWidth, new PreDecodeInfo) // TODO: redefine Predecode
98  val ftqIdx       = new FtqPtr
99  val ftqOffset    = UInt(log2Ceil(PredictWidth).W)
100  val misOffset    = ValidUndirectioned(UInt(log2Ceil(PredictWidth).W))
101  val cfiOffset    = ValidUndirectioned(UInt(log2Ceil(PredictWidth).W))
102  val target       = UInt(VAddrBits.W)
103  val jalTarget    = UInt(VAddrBits.W)
104  val instrRange   = Vec(PredictWidth, Bool())
105}
106
107// Ftq send req to Prefetch
108class PrefetchRequest(implicit p:Parameters) extends XSBundle {
109  val target          = UInt(VAddrBits.W)
110}
111
112class FtqPrefechBundle(implicit p:Parameters) extends XSBundle {
113  val req = DecoupledIO(new PrefetchRequest)
114}
115
116class mmioCommitRead(implicit p: Parameters) extends XSBundle {
117  val mmioFtqPtr = Output(new FtqPtr)
118  val mmioLastCommit = Input(Bool())
119}
120
121class FetchToIBuffer(implicit p: Parameters) extends XSBundle {
122  val instrs    = Vec(PredictWidth, UInt(32.W))
123  val valid     = UInt(PredictWidth.W)
124  val enqEnable = UInt(PredictWidth.W)
125  val pd        = Vec(PredictWidth, new PreDecodeInfo)
126  val pc        = Vec(PredictWidth, UInt(VAddrBits.W))
127  val foldpc    = Vec(PredictWidth, UInt(MemPredPCWidth.W))
128  val ftqPtr       = new FtqPtr
129  val ftqOffset    = Vec(PredictWidth, ValidUndirectioned(UInt(log2Ceil(PredictWidth).W)))
130  val ipf          = Vec(PredictWidth, Bool())
131  val acf          = Vec(PredictWidth, Bool())
132  val crossPageIPFFix = Vec(PredictWidth, Bool())
133  val triggered    = Vec(PredictWidth, new TriggerCf)
134
135  val topdown_info = new FrontendTopDownBundle
136}
137
138// class BitWiseUInt(val width: Int, val init: UInt) extends Module {
139//   val io = IO(new Bundle {
140//     val set
141//   })
142// }
143// Move from BPU
144abstract class GlobalHistory(implicit p: Parameters) extends XSBundle with HasBPUConst {
145  def update(br_valids: Vec[Bool], real_taken_mask: Vec[Bool]): GlobalHistory
146}
147
148class ShiftingGlobalHistory(implicit p: Parameters) extends GlobalHistory {
149  val predHist = UInt(HistoryLength.W)
150
151  def update(shift: UInt, taken: Bool, hist: UInt = this.predHist): ShiftingGlobalHistory = {
152    val g = Wire(new ShiftingGlobalHistory)
153    g.predHist := (hist << shift) | taken
154    g
155  }
156
157  def update(br_valids: Vec[Bool], real_taken_mask: Vec[Bool]): ShiftingGlobalHistory = {
158    require(br_valids.length == numBr)
159    require(real_taken_mask.length == numBr)
160    val last_valid_idx = PriorityMux(
161      br_valids.reverse :+ true.B,
162      (numBr to 0 by -1).map(_.U(log2Ceil(numBr+1).W))
163    )
164    val first_taken_idx = PriorityEncoder(false.B +: real_taken_mask)
165    val smaller = Mux(last_valid_idx < first_taken_idx,
166      last_valid_idx,
167      first_taken_idx
168    )
169    val shift = smaller
170    val taken = real_taken_mask.reduce(_||_)
171    update(shift, taken, this.predHist)
172  }
173
174  // static read
175  def read(n: Int): Bool = predHist.asBools()(n)
176
177  final def === (that: ShiftingGlobalHistory): Bool = {
178    predHist === that.predHist
179  }
180
181  final def =/= (that: ShiftingGlobalHistory): Bool = !(this === that)
182}
183
184// circular global history pointer
185class CGHPtr(implicit p: Parameters) extends CircularQueuePtr[CGHPtr](
186  p => p(XSCoreParamsKey).HistoryLength
187){
188}
189
190object CGHPtr {
191  def apply(f: Bool, v: UInt)(implicit p: Parameters): CGHPtr = {
192    val ptr = Wire(new CGHPtr)
193    ptr.flag := f
194    ptr.value := v
195    ptr
196  }
197  def inverse(ptr: CGHPtr)(implicit p: Parameters): CGHPtr = {
198    apply(!ptr.flag, ptr.value)
199  }
200}
201
202class CircularGlobalHistory(implicit p: Parameters) extends GlobalHistory {
203  val buffer = Vec(HistoryLength, Bool())
204  type HistPtr = UInt
205  def update(br_valids: Vec[Bool], real_taken_mask: Vec[Bool]): CircularGlobalHistory = {
206    this
207  }
208}
209
210class FoldedHistory(val len: Int, val compLen: Int, val max_update_num: Int)(implicit p: Parameters)
211  extends XSBundle with HasBPUConst {
212  require(compLen >= 1)
213  require(len > 0)
214  // require(folded_len <= len)
215  require(compLen >= max_update_num)
216  val folded_hist = UInt(compLen.W)
217
218  def need_oldest_bits = len > compLen
219  def info = (len, compLen)
220  def oldest_bit_to_get_from_ghr = (0 until max_update_num).map(len - _ - 1)
221  def oldest_bit_pos_in_folded = oldest_bit_to_get_from_ghr map (_ % compLen)
222  def oldest_bit_wrap_around = oldest_bit_to_get_from_ghr map (_ / compLen > 0)
223  def oldest_bit_start = oldest_bit_pos_in_folded.head
224
225  def get_oldest_bits_from_ghr(ghr: Vec[Bool], histPtr: CGHPtr) = {
226    // TODO: wrap inc for histPtr value
227    oldest_bit_to_get_from_ghr.map(i => ghr((histPtr + (i+1).U).value))
228  }
229
230  def circular_shift_left(src: UInt, shamt: Int) = {
231    val srcLen = src.getWidth
232    val src_doubled = Cat(src, src)
233    val shifted = src_doubled(srcLen*2-1-shamt, srcLen-shamt)
234    shifted
235  }
236
237  // slow path, read bits from ghr
238  def update(ghr: Vec[Bool], histPtr: CGHPtr, num: Int, taken: Bool): FoldedHistory = {
239    val oldest_bits = VecInit(get_oldest_bits_from_ghr(ghr, histPtr))
240    update(oldest_bits, num, taken)
241  }
242
243
244  // fast path, use pre-read oldest bits
245  def update(ob: Vec[Bool], num: Int, taken: Bool): FoldedHistory = {
246    // do xors for several bitsets at specified bits
247    def bitsets_xor(len: Int, bitsets: Seq[Seq[Tuple2[Int, Bool]]]) = {
248      val res = Wire(Vec(len, Bool()))
249      // println(f"num bitsets: ${bitsets.length}")
250      // println(f"bitsets $bitsets")
251      val resArr = Array.fill(len)(List[Bool]())
252      for (bs <- bitsets) {
253        for ((n, b) <- bs) {
254          resArr(n) = b :: resArr(n)
255        }
256      }
257      // println(f"${resArr.mkString}")
258      // println(f"histLen: ${this.len}, foldedLen: $folded_len")
259      for (i <- 0 until len) {
260        // println(f"bit[$i], ${resArr(i).mkString}")
261        if (resArr(i).length > 2) {
262          println(f"[warning] update logic of foldest history has two or more levels of xor gates! " +
263            f"histlen:${this.len}, compLen:$compLen, at bit $i")
264        }
265        if (resArr(i).length == 0) {
266          println(f"[error] bits $i is not assigned in folded hist update logic! histlen:${this.len}, compLen:$compLen")
267        }
268        res(i) := resArr(i).foldLeft(false.B)(_^_)
269      }
270      res.asUInt
271    }
272
273    val new_folded_hist = if (need_oldest_bits) {
274      val oldest_bits = ob
275      require(oldest_bits.length == max_update_num)
276      // mask off bits that do not update
277      val oldest_bits_masked = oldest_bits.zipWithIndex.map{
278        case (ob, i) => ob && (i < num).B
279      }
280      // if a bit does not wrap around, it should not be xored when it exits
281      val oldest_bits_set = (0 until max_update_num).filter(oldest_bit_wrap_around).map(i => (oldest_bit_pos_in_folded(i), oldest_bits_masked(i)))
282
283      // println(f"old bits pos ${oldest_bits_set.map(_._1)}")
284
285      // only the last bit could be 1, as we have at most one taken branch at a time
286      val newest_bits_masked = VecInit((0 until max_update_num).map(i => taken && ((i+1) == num).B)).asUInt
287      // if a bit does not wrap around, newest bits should not be xored onto it either
288      val newest_bits_set = (0 until max_update_num).map(i => (compLen-1-i, newest_bits_masked(i)))
289
290      // println(f"new bits set ${newest_bits_set.map(_._1)}")
291      //
292      val original_bits_masked = VecInit(folded_hist.asBools.zipWithIndex.map{
293        case (fb, i) => fb && !(num >= (len-i)).B
294      })
295      val original_bits_set = (0 until compLen).map(i => (i, original_bits_masked(i)))
296
297      // do xor then shift
298      val xored = bitsets_xor(compLen, Seq(original_bits_set, oldest_bits_set, newest_bits_set))
299      circular_shift_left(xored, num)
300    } else {
301      // histLen too short to wrap around
302      ((folded_hist << num) | taken)(compLen-1,0)
303    }
304
305    val fh = WireInit(this)
306    fh.folded_hist := new_folded_hist
307    fh
308  }
309}
310
311class AheadFoldedHistoryOldestBits(val len: Int, val max_update_num: Int)(implicit p: Parameters) extends XSBundle {
312  val bits = Vec(max_update_num*2, Bool())
313  // def info = (len, compLen)
314  def getRealOb(brNumOH: UInt): Vec[Bool] = {
315    val ob = Wire(Vec(max_update_num, Bool()))
316    for (i <- 0 until max_update_num) {
317      ob(i) := Mux1H(brNumOH, bits.drop(i).take(numBr+1))
318    }
319    ob
320  }
321}
322
323class AllAheadFoldedHistoryOldestBits(val gen: Seq[Tuple2[Int, Int]])(implicit p: Parameters) extends XSBundle with HasBPUConst {
324  val afhob = MixedVec(gen.filter(t => t._1 > t._2).map{_._1}
325    .toSet.toList.map(l => new AheadFoldedHistoryOldestBits(l, numBr))) // remove duplicates
326  require(gen.toSet.toList.equals(gen))
327  def getObWithInfo(info: Tuple2[Int, Int]) = {
328    val selected = afhob.filter(_.len == info._1)
329    require(selected.length == 1)
330    selected(0)
331  }
332  def read(ghv: Vec[Bool], ptr: CGHPtr) = {
333    val hisLens = afhob.map(_.len)
334    val bitsToRead = hisLens.flatMap(l => (0 until numBr*2).map(i => l-i-1)).toSet // remove duplicates
335    val bitsWithInfo = bitsToRead.map(pos => (pos, ghv((ptr+(pos+1).U).value)))
336    for (ob <- afhob) {
337      for (i <- 0 until numBr*2) {
338        val pos = ob.len - i - 1
339        val bit_found = bitsWithInfo.filter(_._1 == pos).toList
340        require(bit_found.length == 1)
341        ob.bits(i) := bit_found(0)._2
342      }
343    }
344  }
345}
346
347class AllFoldedHistories(val gen: Seq[Tuple2[Int, Int]])(implicit p: Parameters) extends XSBundle with HasBPUConst {
348  val hist = MixedVec(gen.map{case (l, cl) => new FoldedHistory(l, cl, numBr)})
349  // println(gen.mkString)
350  require(gen.toSet.toList.equals(gen))
351  def getHistWithInfo(info: Tuple2[Int, Int]) = {
352    val selected = hist.filter(_.info.equals(info))
353    require(selected.length == 1)
354    selected(0)
355  }
356  def autoConnectFrom(that: AllFoldedHistories) = {
357    require(this.hist.length <= that.hist.length)
358    for (h <- this.hist) {
359      h := that.getHistWithInfo(h.info)
360    }
361  }
362  def update(ghv: Vec[Bool], ptr: CGHPtr, shift: Int, taken: Bool): AllFoldedHistories = {
363    val res = WireInit(this)
364    for (i <- 0 until this.hist.length) {
365      res.hist(i) := this.hist(i).update(ghv, ptr, shift, taken)
366    }
367    res
368  }
369  def update(afhob: AllAheadFoldedHistoryOldestBits, lastBrNumOH: UInt, shift: Int, taken: Bool): AllFoldedHistories = {
370    val res = WireInit(this)
371    for (i <- 0 until this.hist.length) {
372      val fh = this.hist(i)
373      if (fh.need_oldest_bits) {
374        val info = fh.info
375        val selectedAfhob = afhob.getObWithInfo(info)
376        val ob = selectedAfhob.getRealOb(lastBrNumOH)
377        res.hist(i) := this.hist(i).update(ob, shift, taken)
378      } else {
379        val dumb = Wire(Vec(numBr, Bool())) // not needed
380        dumb := DontCare
381        res.hist(i) := this.hist(i).update(dumb, shift, taken)
382      }
383    }
384    res
385  }
386
387  def display(cond: Bool) = {
388    for (h <- hist) {
389      XSDebug(cond, p"hist len ${h.len}, folded len ${h.compLen}, value ${Binary(h.folded_hist)}\n")
390    }
391  }
392}
393
394class TableAddr(val idxBits: Int, val banks: Int)(implicit p: Parameters) extends XSBundle{
395  def tagBits = VAddrBits - idxBits - instOffsetBits
396
397  val tag = UInt(tagBits.W)
398  val idx = UInt(idxBits.W)
399  val offset = UInt(instOffsetBits.W)
400
401  def fromUInt(x: UInt) = x.asTypeOf(UInt(VAddrBits.W)).asTypeOf(this)
402  def getTag(x: UInt) = fromUInt(x).tag
403  def getIdx(x: UInt) = fromUInt(x).idx
404  def getBank(x: UInt) = if (banks > 1) getIdx(x)(log2Up(banks) - 1, 0) else 0.U
405  def getBankIdx(x: UInt) = if (banks > 1) getIdx(x)(idxBits - 1, log2Up(banks)) else getIdx(x)
406}
407
408trait BasicPrediction extends HasXSParameter {
409  def cfiIndex: ValidUndirectioned[UInt]
410  def target(pc: UInt): UInt
411  def lastBrPosOH: Vec[Bool]
412  def brTaken: Bool
413  def shouldShiftVec: Vec[Bool]
414  def fallThruError: Bool
415}
416@chiselName
417class FullBranchPrediction(implicit p: Parameters) extends XSBundle with HasBPUConst with BasicPrediction {
418  val br_taken_mask = Vec(numBr, Bool())
419
420  val slot_valids = Vec(totalSlot, Bool())
421
422  val targets = Vec(totalSlot, UInt(VAddrBits.W))
423  val jalr_target = UInt(VAddrBits.W) // special path for indirect predictors
424  val offsets = Vec(totalSlot, UInt(log2Ceil(PredictWidth).W))
425  val fallThroughAddr = UInt(VAddrBits.W)
426  val fallThroughErr = Bool()
427
428  val is_jal = Bool()
429  val is_jalr = Bool()
430  val is_call = Bool()
431  val is_ret = Bool()
432  val last_may_be_rvi_call = Bool()
433  val is_br_sharing = Bool()
434
435  // val call_is_rvc = Bool()
436  val hit = Bool()
437
438  val predCycle = if (!env.FPGAPlatform) Some(UInt(64.W)) else None
439
440  def br_slot_valids = slot_valids.init
441  def tail_slot_valid = slot_valids.last
442
443  def br_valids = {
444    VecInit(br_slot_valids :+ (tail_slot_valid && is_br_sharing))
445  }
446
447  def taken_mask_on_slot = {
448    VecInit(
449      (br_slot_valids zip br_taken_mask.init).map{ case (t, v) => t && v } :+ (
450        tail_slot_valid && (
451          is_br_sharing && br_taken_mask.last || !is_br_sharing
452        )
453      )
454    )
455  }
456
457  def real_slot_taken_mask(): Vec[Bool] = {
458    VecInit(taken_mask_on_slot.map(_ && hit))
459  }
460
461  // len numBr
462  def real_br_taken_mask(): Vec[Bool] = {
463    VecInit(
464      taken_mask_on_slot.map(_ && hit).init :+
465      (br_taken_mask.last && tail_slot_valid && is_br_sharing && hit)
466    )
467  }
468
469  // the vec indicating if ghr should shift on each branch
470  def shouldShiftVec =
471    VecInit(br_valids.zipWithIndex.map{ case (v, i) =>
472      v && !real_br_taken_mask.take(i).reduceOption(_||_).getOrElse(false.B)})
473
474  def lastBrPosOH =
475    VecInit((!hit || !br_valids.reduce(_||_)) +: // not hit or no brs in entry
476      (0 until numBr).map(i =>
477        br_valids(i) &&
478        !real_br_taken_mask.take(i).reduceOption(_||_).getOrElse(false.B) && // no brs taken in front it
479        (real_br_taken_mask()(i) || !br_valids.drop(i+1).reduceOption(_||_).getOrElse(false.B)) && // no brs behind it
480        hit
481      )
482    )
483
484  def brTaken = (br_valids zip br_taken_mask).map{ case (a, b) => a && b && hit}.reduce(_||_)
485
486  def target(pc: UInt): UInt = {
487    val targetVec = targets :+ fallThroughAddr :+ (pc + (FetchWidth * 4).U)
488    val tm = taken_mask_on_slot
489    val selVecOH =
490      tm.zipWithIndex.map{ case (t, i) => !tm.take(i).fold(false.B)(_||_) && t && hit} :+
491      (!tm.asUInt.orR && hit) :+ !hit
492    Mux1H(selVecOH, targetVec)
493  }
494
495  def fallThruError: Bool = hit && fallThroughErr
496
497  def hit_taken_on_jmp =
498    !real_slot_taken_mask().init.reduce(_||_) &&
499    real_slot_taken_mask().last && !is_br_sharing
500  def hit_taken_on_call = hit_taken_on_jmp && is_call
501  def hit_taken_on_ret  = hit_taken_on_jmp && is_ret
502  def hit_taken_on_jalr = hit_taken_on_jmp && is_jalr
503
504  def cfiIndex = {
505    val cfiIndex = Wire(ValidUndirectioned(UInt(log2Ceil(PredictWidth).W)))
506    cfiIndex.valid := real_slot_taken_mask().asUInt.orR
507    // when no takens, set cfiIndex to PredictWidth-1
508    cfiIndex.bits :=
509      ParallelPriorityMux(real_slot_taken_mask(), offsets) |
510      Fill(log2Ceil(PredictWidth), (!real_slot_taken_mask().asUInt.orR).asUInt)
511    cfiIndex
512  }
513
514  def taken = br_taken_mask.reduce(_||_) || slot_valids.last // || (is_jal || is_jalr)
515
516  def fromFtbEntry(
517                    entry: FTBEntry,
518                    pc: UInt,
519                    last_stage_pc: Option[Tuple2[UInt, Bool]] = None,
520                    last_stage_entry: Option[Tuple2[FTBEntry, Bool]] = None
521                  ) = {
522    slot_valids := entry.brSlots.map(_.valid) :+ entry.tailSlot.valid
523    targets := entry.getTargetVec(pc, last_stage_pc) // Use previous stage pc for better timing
524    jalr_target := targets.last
525    offsets := entry.getOffsetVec
526    is_jal := entry.tailSlot.valid && entry.isJal
527    is_jalr := entry.tailSlot.valid && entry.isJalr
528    is_call := entry.tailSlot.valid && entry.isCall
529    is_ret := entry.tailSlot.valid && entry.isRet
530    last_may_be_rvi_call := entry.last_may_be_rvi_call
531    is_br_sharing := entry.tailSlot.valid && entry.tailSlot.sharing
532    predCycle.map(_ := GTimer())
533
534    val startLower        = Cat(0.U(1.W),    pc(instOffsetBits+log2Ceil(PredictWidth)-1, instOffsetBits))
535    val endLowerwithCarry = Cat(entry.carry, entry.pftAddr)
536    fallThroughErr := startLower >= endLowerwithCarry
537    fallThroughAddr := Mux(fallThroughErr, pc + (FetchWidth * 4).U, entry.getFallThrough(pc, last_stage_entry))
538  }
539
540  def display(cond: Bool): Unit = {
541    XSDebug(cond, p"[taken_mask] ${Binary(br_taken_mask.asUInt)} [hit] $hit\n")
542  }
543}
544
545class SpeculativeInfo(implicit p: Parameters) extends XSBundle
546  with HasBPUConst with BPUUtils {
547  val folded_hist = new AllFoldedHistories(foldedGHistInfos)
548  val afhob = new AllAheadFoldedHistoryOldestBits(foldedGHistInfos)
549  val lastBrNumOH = UInt((numBr+1).W)
550  val histPtr = new CGHPtr
551  val ssp = UInt(log2Up(RasSize).W)
552  val sctr = UInt(log2Up(RasCtrSize).W)
553  val TOSW = new RASPtr
554  val TOSR = new RASPtr
555  val NOS = new RASPtr
556  val topAddr = UInt(VAddrBits.W)
557}
558
559@chiselName
560class BranchPredictionBundle(implicit p: Parameters) extends XSBundle
561  with HasBPUConst with BPUUtils {
562  val pc    = Vec(numDup, UInt(VAddrBits.W))
563  val valid = Vec(numDup, Bool())
564  val hasRedirect  = Vec(numDup, Bool())
565  val ftq_idx = new FtqPtr
566  val full_pred    = Vec(numDup, new FullBranchPrediction)
567
568
569  def target(pc: UInt) = VecInit(full_pred.map(_.target(pc)))
570  def targets(pc: Vec[UInt]) = VecInit(pc.zipWithIndex.map{case (a, i) => full_pred(i).target(a)})
571  def cfiIndex         = VecInit(full_pred.map(_.cfiIndex))
572  def lastBrPosOH      = VecInit(full_pred.map(_.lastBrPosOH))
573  def brTaken          = VecInit(full_pred.map(_.brTaken))
574  def shouldShiftVec   = VecInit(full_pred.map(_.shouldShiftVec))
575  def fallThruError    = VecInit(full_pred.map(_.fallThruError))
576
577  def taken = VecInit(cfiIndex.map(_.valid))
578
579  def getTarget = targets(pc)
580
581  def display(cond: Bool): Unit = {
582    XSDebug(cond, p"[pc] ${Hexadecimal(pc(0))}\n")
583    full_pred(0).display(cond)
584  }
585}
586
587@chiselName
588class BranchPredictionResp(implicit p: Parameters) extends XSBundle with HasBPUConst {
589  // val valids = Vec(3, Bool())
590  val s1 = new BranchPredictionBundle
591  val s2 = new BranchPredictionBundle
592  val s3 = new BranchPredictionBundle
593
594  val last_stage_meta = UInt(MaxMetaLength.W)
595  val last_stage_spec_info = new SpeculativeInfo
596  val last_stage_ftb_entry = new FTBEntry
597
598  val topdown_info = new FrontendTopDownBundle
599
600  def selectedResp ={
601    val res =
602      PriorityMux(Seq(
603        ((s3.valid(3) && s3.hasRedirect(3)) -> s3),
604        ((s2.valid(3) && s2.hasRedirect(3)) -> s2),
605        (s1.valid(3) -> s1)
606      ))
607    res
608  }
609  def selectedRespIdxForFtq =
610    PriorityMux(Seq(
611      ((s3.valid(3) && s3.hasRedirect(3)) -> BP_S3),
612      ((s2.valid(3) && s2.hasRedirect(3)) -> BP_S2),
613      (s1.valid(3) -> BP_S1)
614    ))
615  def lastStage = s3
616}
617
618class BpuToFtqBundle(implicit p: Parameters) extends BranchPredictionResp {}
619
620class BranchPredictionUpdate(implicit p: Parameters) extends XSBundle with HasBPUConst {
621  val pc = UInt(VAddrBits.W)
622  val spec_info = new SpeculativeInfo
623  val ftb_entry = new FTBEntry()
624
625  val cfi_idx = ValidUndirectioned(UInt(log2Ceil(PredictWidth).W))
626  val br_taken_mask = Vec(numBr, Bool())
627  val br_committed = Vec(numBr, Bool()) // High only when br valid && br committed
628  val jmp_taken = Bool()
629  val mispred_mask = Vec(numBr+1, Bool())
630  val pred_hit = Bool()
631  val false_hit = Bool()
632  val new_br_insert_pos = Vec(numBr, Bool())
633  val old_entry = Bool()
634  val meta = UInt(MaxMetaLength.W)
635  val full_target = UInt(VAddrBits.W)
636  val from_stage = UInt(2.W)
637  val ghist = UInt(HistoryLength.W)
638
639  def is_jal = ftb_entry.tailSlot.valid && ftb_entry.isJal
640  def is_jalr = ftb_entry.tailSlot.valid && ftb_entry.isJalr
641  def is_call = ftb_entry.tailSlot.valid && ftb_entry.isCall
642  def is_ret = ftb_entry.tailSlot.valid && ftb_entry.isRet
643
644  def is_call_taken = is_call && jmp_taken && cfi_idx.valid && cfi_idx.bits === ftb_entry.tailSlot.offset
645  def is_ret_taken = is_ret && jmp_taken && cfi_idx.valid && cfi_idx.bits === ftb_entry.tailSlot.offset
646
647  def display(cond: Bool) = {
648    XSDebug(cond, p"-----------BranchPredictionUpdate-----------\n")
649    XSDebug(cond, p"[mispred_mask] ${Binary(mispred_mask.asUInt)} [false_hit] $false_hit\n")
650    XSDebug(cond, p"[new_br_insert_pos] ${Binary(new_br_insert_pos.asUInt)}\n")
651    XSDebug(cond, p"--------------------------------------------\n")
652  }
653}
654
655class BranchPredictionRedirect(implicit p: Parameters) extends Redirect with HasBPUConst {
656  // override def toPrintable: Printable = {
657  //   p"-----------BranchPredictionRedirect----------- " +
658  //     p"-----------cfiUpdate----------- " +
659  //     p"[pc] ${Hexadecimal(cfiUpdate.pc)} " +
660  //     p"[predTaken] ${cfiUpdate.predTaken}, [taken] ${cfiUpdate.taken}, [isMisPred] ${cfiUpdate.isMisPred} " +
661  //     p"[target] ${Hexadecimal(cfiUpdate.target)} " +
662  //     p"------------------------------- " +
663  //     p"[robPtr] f=${robIdx.flag} v=${robIdx.value} " +
664  //     p"[ftqPtr] f=${ftqIdx.flag} v=${ftqIdx.value} " +
665  //     p"[ftqOffset] ${ftqOffset} " +
666  //     p"[level] ${level}, [interrupt] ${interrupt} " +
667  //     p"[stFtqIdx] f=${stFtqIdx.flag} v=${stFtqIdx.value} " +
668  //     p"[stFtqOffset] ${stFtqOffset} " +
669  //     p"\n"
670
671  // }
672
673  // TODO: backend should pass topdown signals here
674  // must not change its parent since BPU has used asTypeOf(this type) from its parent class
675  require(isInstanceOf[Redirect])
676  val BTBMissBubble = Bool()
677  def ControlRedirectBubble = debugIsCtrl
678  // if mispred br not in ftb, count as BTB miss
679  def ControlBTBMissBubble = ControlRedirectBubble && !cfiUpdate.br_hit && !cfiUpdate.jr_hit
680  def TAGEMissBubble = ControlRedirectBubble && cfiUpdate.br_hit && !cfiUpdate.sc_hit
681  def SCMissBubble = ControlRedirectBubble && cfiUpdate.br_hit && cfiUpdate.sc_hit
682  def ITTAGEMissBubble = ControlRedirectBubble && cfiUpdate.jr_hit && !cfiUpdate.pd.isRet
683  def RASMissBubble = ControlRedirectBubble && cfiUpdate.jr_hit && cfiUpdate.pd.isRet
684  def MemVioRedirectBubble = debugIsMemVio
685  def OtherRedirectBubble = !debugIsCtrl && !debugIsMemVio
686
687  def connectRedirect(source: Redirect): Unit = {
688    for ((name, data) <- this.elements) {
689      if (source.elements.contains(name)) {
690        data := source.elements(name)
691      }
692    }
693  }
694
695  def display(cond: Bool): Unit = {
696    XSDebug(cond, p"-----------BranchPredictionRedirect----------- \n")
697    XSDebug(cond, p"-----------cfiUpdate----------- \n")
698    XSDebug(cond, p"[pc] ${Hexadecimal(cfiUpdate.pc)}\n")
699    // XSDebug(cond, p"[hist] ${Binary(cfiUpdate.hist.predHist)}\n")
700    XSDebug(cond, p"[br_hit] ${cfiUpdate.br_hit} [isMisPred] ${cfiUpdate.isMisPred}\n")
701    XSDebug(cond, p"[pred_taken] ${cfiUpdate.predTaken} [taken] ${cfiUpdate.taken} [isMisPred] ${cfiUpdate.isMisPred}\n")
702    XSDebug(cond, p"[target] ${Hexadecimal(cfiUpdate.target)} \n")
703    XSDebug(cond, p"[shift] ${cfiUpdate.shift}\n")
704    XSDebug(cond, p"------------------------------- \n")
705    XSDebug(cond, p"[robPtr] f=${robIdx.flag} v=${robIdx.value}\n")
706    XSDebug(cond, p"[ftqPtr] f=${ftqIdx.flag} v=${ftqIdx.value} \n")
707    XSDebug(cond, p"[ftqOffset] ${ftqOffset} \n")
708    XSDebug(cond, p"[stFtqIdx] f=${stFtqIdx.flag} v=${stFtqIdx.value}\n")
709    XSDebug(cond, p"[stFtqOffset] ${stFtqOffset}\n")
710    XSDebug(cond, p"---------------------------------------------- \n")
711  }
712}
713