1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan 18 19import chipsalliance.rocketchip.config.{Field, Parameters} 20import chisel3._ 21import chisel3.util._ 22import xiangshan.backend.exu._ 23import xiangshan.backend.dispatch.DispatchParameters 24import xiangshan.cache.DCacheParameters 25import xiangshan.cache.prefetch._ 26import xiangshan.frontend.{BasePredictor, BranchPredictionResp, FTB, FakePredictor, RAS, Tage, ITTage, Tage_SC, FauFTB} 27import xiangshan.frontend.icache.ICacheParameters 28import xiangshan.cache.mmu.{L2TLBParameters, TLBParameters} 29import freechips.rocketchip.diplomacy.AddressSet 30import system.SoCParamsKey 31import huancun._ 32import huancun.debug._ 33import coupledL2._ 34import xiangshan.mem.prefetch.{PrefetcherParams, SMSParams} 35 36import scala.math.min 37 38case object XSTileKey extends Field[Seq[XSCoreParameters]] 39 40case object XSCoreParamsKey extends Field[XSCoreParameters] 41 42case class XSCoreParameters 43( 44 HasPrefetch: Boolean = false, 45 HartId: Int = 0, 46 XLEN: Int = 64, 47 VLEN: Int = 128, 48 HasMExtension: Boolean = true, 49 HasCExtension: Boolean = true, 50 HasDiv: Boolean = true, 51 HasICache: Boolean = true, 52 HasDCache: Boolean = true, 53 AddrBits: Int = 64, 54 VAddrBits: Int = 39, 55 HasFPU: Boolean = true, 56 HasCustomCSRCacheOp: Boolean = true, 57 FetchWidth: Int = 8, 58 AsidLength: Int = 16, 59 EnableBPU: Boolean = true, 60 EnableBPD: Boolean = true, 61 EnableRAS: Boolean = true, 62 EnableLB: Boolean = false, 63 EnableLoop: Boolean = true, 64 EnableSC: Boolean = true, 65 EnbaleTlbDebug: Boolean = false, 66 EnableJal: Boolean = false, 67 EnableFauFTB: Boolean = true, 68 UbtbGHRLength: Int = 4, 69 // HistoryLength: Int = 512, 70 EnableGHistDiff: Boolean = true, 71 EnableCommitGHistDiff: Boolean = true, 72 UbtbSize: Int = 256, 73 FtbSize: Int = 2048, 74 RasSize: Int = 32, 75 CacheLineSize: Int = 512, 76 FtbWays: Int = 4, 77 TageTableInfos: Seq[Tuple3[Int,Int,Int]] = 78 // Sets Hist Tag 79 // Seq(( 2048, 2, 8), 80 // ( 2048, 9, 8), 81 // ( 2048, 13, 8), 82 // ( 2048, 20, 8), 83 // ( 2048, 26, 8), 84 // ( 2048, 44, 8), 85 // ( 2048, 73, 8), 86 // ( 2048, 256, 8)), 87 Seq(( 4096, 8, 8), 88 ( 4096, 13, 8), 89 ( 4096, 32, 8), 90 ( 4096, 119, 8)), 91 ITTageTableInfos: Seq[Tuple3[Int,Int,Int]] = 92 // Sets Hist Tag 93 Seq(( 256, 4, 9), 94 ( 256, 8, 9), 95 ( 512, 13, 9), 96 ( 512, 16, 9), 97 ( 512, 32, 9)), 98 SCNRows: Int = 512, 99 SCNTables: Int = 4, 100 SCCtrBits: Int = 6, 101 SCHistLens: Seq[Int] = Seq(0, 4, 10, 16), 102 numBr: Int = 2, 103 branchPredictor: Function2[BranchPredictionResp, Parameters, Tuple2[Seq[BasePredictor], BranchPredictionResp]] = 104 ((resp_in: BranchPredictionResp, p: Parameters) => { 105 val ftb = Module(new FTB()(p)) 106 val ubtb =Module(new FauFTB()(p)) 107 // val bim = Module(new BIM()(p)) 108 val tage = Module(new Tage_SC()(p)) 109 val ras = Module(new RAS()(p)) 110 val ittage = Module(new ITTage()(p)) 111 val preds = Seq(ubtb, tage, ftb, ittage, ras) 112 preds.map(_.io := DontCare) 113 114 // ubtb.io.resp_in(0) := resp_in 115 // bim.io.resp_in(0) := ubtb.io.resp 116 // btb.io.resp_in(0) := bim.io.resp 117 // tage.io.resp_in(0) := btb.io.resp 118 // loop.io.resp_in(0) := tage.io.resp 119 ubtb.io.in.bits.resp_in(0) := resp_in 120 tage.io.in.bits.resp_in(0) := ubtb.io.out 121 ftb.io.in.bits.resp_in(0) := tage.io.out 122 ittage.io.in.bits.resp_in(0) := ftb.io.out 123 ras.io.in.bits.resp_in(0) := ittage.io.out 124 125 (preds, ras.io.out) 126 }), 127 IBufSize: Int = 48, 128 DecodeWidth: Int = 6, 129 RenameWidth: Int = 6, 130 CommitWidth: Int = 6, 131 EnableRenameSnapshot: Boolean = true, 132 RenameSnapshotNum: Int = 4, 133 FtqSize: Int = 64, 134 EnableLoadFastWakeUp: Boolean = true, // NOTE: not supported now, make it false 135 IssQueSize: Int = 16, 136 NRPhyRegs: Int = 192, 137 VirtualLoadQueueSize: Int = 80, 138 LoadQueueRARSize: Int = 80, 139 LoadQueueRAWSize: Int = 64, // NOTE: make sure that LoadQueueRAWSize is power of 2. 140 RollbackGroupSize: Int = 8, 141 LoadQueueReplaySize: Int = 72, 142 LoadUncacheBufferSize: Int = 20, 143 LoadQueueNWriteBanks: Int = 8, // NOTE: make sure that LoadQueueRARSize/LoadQueueRAWSize is divided by LoadQueueNWriteBanks 144 StoreQueueSize: Int = 64, 145 StoreQueueNWriteBanks: Int = 8, // NOTE: make sure that StoreQueueSize is divided by StoreQueueNWriteBanks 146 StoreQueueForwardWithMask: Boolean = true, 147 VlsQueueSize: Int = 8, 148 RobSize: Int = 256, 149 dpParams: DispatchParameters = DispatchParameters( 150 IntDqSize = 16, 151 FpDqSize = 16, 152 LsDqSize = 16, 153 IntDqDeqWidth = 4, 154 FpDqDeqWidth = 4, 155 LsDqDeqWidth = 4 156 ), 157 exuParameters: ExuParameters = ExuParameters( 158 JmpCnt = 1, 159 AluCnt = 4, 160 MulCnt = 0, 161 MduCnt = 2, 162 FmacCnt = 4, 163 FmiscCnt = 2, 164 FmiscDivSqrtCnt = 0, 165 LduCnt = 2, 166 StuCnt = 2 167 ), 168 prefetcher: Option[PrefetcherParams] = Some(SMSParams()), 169 LoadPipelineWidth: Int = 2, 170 StorePipelineWidth: Int = 2, 171 VecMemSrcInWidth: Int = 2, 172 VecMemInstWbWidth: Int = 1, 173 VecMemDispatchWidth: Int = 1, 174 StoreBufferSize: Int = 16, 175 StoreBufferThreshold: Int = 7, 176 EnsbufferWidth: Int = 2, 177 UncacheBufferSize: Int = 4, 178 EnableLoadToLoadForward: Boolean = true, 179 EnableFastForward: Boolean = true, 180 EnableLdVioCheckAfterReset: Boolean = true, 181 EnableSoftPrefetchAfterReset: Boolean = true, 182 EnableCacheErrorAfterReset: Boolean = true, 183 EnableDCacheWPU: Boolean = false, 184 EnableAccurateLoadError: Boolean = true, 185 EnableUncacheWriteOutstanding: Boolean = false, 186 MMUAsidLen: Int = 16, // max is 16, 0 is not supported now 187 ReSelectLen: Int = 7, // load replay queue replay select counter len 188 itlbParameters: TLBParameters = TLBParameters( 189 name = "itlb", 190 fetchi = true, 191 useDmode = false, 192 normalNWays = 32, 193 normalReplacer = Some("plru"), 194 superNWays = 4, 195 superReplacer = Some("plru") 196 ), 197 itlbPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 198 ipmpPortNum: Int = 2 + ICacheParameters().prefetchPipeNum + 1, 199 ldtlbParameters: TLBParameters = TLBParameters( 200 name = "ldtlb", 201 normalNSets = 64, 202 normalNWays = 1, 203 normalAssociative = "sa", 204 normalReplacer = Some("setplru"), 205 superNWays = 16, 206 normalAsVictim = true, 207 outReplace = false, 208 partialStaticPMP = true, 209 outsideRecvFlush = true, 210 saveLevel = true 211 ), 212 sttlbParameters: TLBParameters = TLBParameters( 213 name = "sttlb", 214 normalNSets = 64, 215 normalNWays = 1, 216 normalAssociative = "sa", 217 normalReplacer = Some("setplru"), 218 superNWays = 16, 219 normalAsVictim = true, 220 outReplace = false, 221 partialStaticPMP = true, 222 outsideRecvFlush = true, 223 saveLevel = true 224 ), 225 pftlbParameters: TLBParameters = TLBParameters( 226 name = "pftlb", 227 normalNSets = 64, 228 normalNWays = 1, 229 normalAssociative = "sa", 230 normalReplacer = Some("setplru"), 231 superNWays = 16, 232 normalAsVictim = true, 233 outReplace = false, 234 partialStaticPMP = true, 235 outsideRecvFlush = true, 236 saveLevel = true 237 ), 238 refillBothTlb: Boolean = false, 239 btlbParameters: TLBParameters = TLBParameters( 240 name = "btlb", 241 normalNSets = 1, 242 normalNWays = 64, 243 superNWays = 4, 244 ), 245 l2tlbParameters: L2TLBParameters = L2TLBParameters(), 246 NumPerfCounters: Int = 16, 247 icacheParameters: ICacheParameters = ICacheParameters( 248 tagECC = Some("parity"), 249 dataECC = Some("parity"), 250 replacer = Some("setplru"), 251 nMissEntries = 2, 252 nProbeEntries = 2, 253 nPrefetchEntries = 12, 254 nPrefBufferEntries = 64, 255 hasPrefetch = true, 256 ), 257 dcacheParametersOpt: Option[DCacheParameters] = Some(DCacheParameters( 258 tagECC = Some("secded"), 259 dataECC = Some("secded"), 260 replacer = Some("setplru"), 261 nMissEntries = 16, 262 nProbeEntries = 8, 263 nReleaseEntries = 18 264 )), 265 L2CacheParamsOpt: Option[L2Param] = Some(L2Param( 266 name = "l2", 267 ways = 8, 268 sets = 1024, // default 512KB L2 269 prefetch = Some(coupledL2.prefetch.PrefetchReceiverParams()) 270 )), 271 L2NBanks: Int = 1, 272 usePTWRepeater: Boolean = false, 273 softTLB: Boolean = false, // dpi-c l1tlb debug only 274 softPTW: Boolean = false, // dpi-c l2tlb debug only 275 softPTWDelay: Int = 1 276){ 277 val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength 278 val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now 279 280 val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg) 281 val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg) 282 283 val intExuConfigs = (Seq.fill(exuParameters.AluCnt)(AluExeUnitCfg) ++ 284 Seq.fill(exuParameters.MduCnt)(MulDivExeUnitCfg) :+ JumpCSRExeUnitCfg) 285 286 val fpExuConfigs = 287 Seq.fill(exuParameters.FmacCnt)(FmacExeUnitCfg) ++ 288 Seq.fill(exuParameters.FmiscCnt)(FmiscExeUnitCfg) 289 290 val exuConfigs: Seq[ExuConfig] = intExuConfigs ++ fpExuConfigs ++ loadExuConfigs ++ storeExuConfigs 291} 292 293case object DebugOptionsKey extends Field[DebugOptions] 294 295case class DebugOptions 296( 297 FPGAPlatform: Boolean = false, 298 EnableDifftest: Boolean = false, 299 AlwaysBasicDiff: Boolean = true, 300 EnableDebug: Boolean = false, 301 EnablePerfDebug: Boolean = true, 302 UseDRAMSim: Boolean = false, 303 EnableConstantin: Boolean = false, 304 EnableChiselDB: Boolean = false, 305 AlwaysBasicDB: Boolean = true, 306) 307 308trait HasXSParameter { 309 310 implicit val p: Parameters 311 312 val PAddrBits = p(SoCParamsKey).PAddrBits // PAddrBits is Phyical Memory addr bits 313 314 val coreParams = p(XSCoreParamsKey) 315 val env = p(DebugOptionsKey) 316 317 val XLEN = coreParams.XLEN 318 val VLEN = coreParams.VLEN 319 val minFLen = 32 320 val fLen = 64 321 def xLen = XLEN 322 323 val HasMExtension = coreParams.HasMExtension 324 val HasCExtension = coreParams.HasCExtension 325 val HasDiv = coreParams.HasDiv 326 val HasIcache = coreParams.HasICache 327 val HasDcache = coreParams.HasDCache 328 val AddrBits = coreParams.AddrBits // AddrBits is used in some cases 329 val VAddrBits = coreParams.VAddrBits // VAddrBits is Virtual Memory addr bits 330 val AsidLength = coreParams.AsidLength 331 val ReSelectLen = coreParams.ReSelectLen 332 val AddrBytes = AddrBits / 8 // unused 333 val DataBits = XLEN 334 val DataBytes = DataBits / 8 335 val VDataBytes = VLEN / 8 336 val HasFPU = coreParams.HasFPU 337 val HasCustomCSRCacheOp = coreParams.HasCustomCSRCacheOp 338 val FetchWidth = coreParams.FetchWidth 339 val PredictWidth = FetchWidth * (if (HasCExtension) 2 else 1) 340 val EnableBPU = coreParams.EnableBPU 341 val EnableBPD = coreParams.EnableBPD // enable backing predictor(like Tage) in BPUStage3 342 val EnableRAS = coreParams.EnableRAS 343 val EnableLB = coreParams.EnableLB 344 val EnableLoop = coreParams.EnableLoop 345 val EnableSC = coreParams.EnableSC 346 val EnbaleTlbDebug = coreParams.EnbaleTlbDebug 347 val HistoryLength = coreParams.HistoryLength 348 val EnableGHistDiff = coreParams.EnableGHistDiff 349 val EnableCommitGHistDiff = coreParams.EnableCommitGHistDiff 350 val UbtbGHRLength = coreParams.UbtbGHRLength 351 val UbtbSize = coreParams.UbtbSize 352 val EnableFauFTB = coreParams.EnableFauFTB 353 val FtbSize = coreParams.FtbSize 354 val FtbWays = coreParams.FtbWays 355 val RasSize = coreParams.RasSize 356 357 def getBPDComponents(resp_in: BranchPredictionResp, p: Parameters) = { 358 coreParams.branchPredictor(resp_in, p) 359 } 360 val numBr = coreParams.numBr 361 val TageTableInfos = coreParams.TageTableInfos 362 val TageBanks = coreParams.numBr 363 val SCNRows = coreParams.SCNRows 364 val SCCtrBits = coreParams.SCCtrBits 365 val SCHistLens = coreParams.SCHistLens 366 val SCNTables = coreParams.SCNTables 367 368 val SCTableInfos = Seq.fill(SCNTables)((SCNRows, SCCtrBits)) zip SCHistLens map { 369 case ((n, cb), h) => (n, cb, h) 370 } 371 val ITTageTableInfos = coreParams.ITTageTableInfos 372 type FoldedHistoryInfo = Tuple2[Int, Int] 373 val foldedGHistInfos = 374 (TageTableInfos.map{ case (nRows, h, t) => 375 if (h > 0) 376 Set((h, min(log2Ceil(nRows/numBr), h)), (h, min(h, t)), (h, min(h, t-1))) 377 else 378 Set[FoldedHistoryInfo]() 379 }.reduce(_++_).toSet ++ 380 SCTableInfos.map{ case (nRows, _, h) => 381 if (h > 0) 382 Set((h, min(log2Ceil(nRows/TageBanks), h))) 383 else 384 Set[FoldedHistoryInfo]() 385 }.reduce(_++_).toSet ++ 386 ITTageTableInfos.map{ case (nRows, h, t) => 387 if (h > 0) 388 Set((h, min(log2Ceil(nRows), h)), (h, min(h, t)), (h, min(h, t-1))) 389 else 390 Set[FoldedHistoryInfo]() 391 }.reduce(_++_) ++ 392 Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize))) 393 ).toList 394 395 396 397 val CacheLineSize = coreParams.CacheLineSize 398 val CacheLineHalfWord = CacheLineSize / 16 399 val ExtHistoryLength = HistoryLength + 64 400 val IBufSize = coreParams.IBufSize 401 val DecodeWidth = coreParams.DecodeWidth 402 val RenameWidth = coreParams.RenameWidth 403 val CommitWidth = coreParams.CommitWidth 404 val EnableRenameSnapshot = coreParams.EnableRenameSnapshot 405 val RenameSnapshotNum = coreParams.RenameSnapshotNum 406 val FtqSize = coreParams.FtqSize 407 val IssQueSize = coreParams.IssQueSize 408 val EnableLoadFastWakeUp = coreParams.EnableLoadFastWakeUp 409 val NRPhyRegs = coreParams.NRPhyRegs 410 val PhyRegIdxWidth = log2Up(NRPhyRegs) 411 val RobSize = coreParams.RobSize 412 val IntRefCounterWidth = log2Ceil(RobSize) 413 val VirtualLoadQueueSize = coreParams.VirtualLoadQueueSize 414 val LoadQueueRARSize = coreParams.LoadQueueRARSize 415 val LoadQueueRAWSize = coreParams.LoadQueueRAWSize 416 val RollbackGroupSize = coreParams.RollbackGroupSize 417 val LoadQueueReplaySize = coreParams.LoadQueueReplaySize 418 val LoadUncacheBufferSize = coreParams.LoadUncacheBufferSize 419 val LoadQueueNWriteBanks = coreParams.LoadQueueNWriteBanks 420 val StoreQueueSize = coreParams.StoreQueueSize 421 val StoreQueueNWriteBanks = coreParams.StoreQueueNWriteBanks 422 val StoreQueueForwardWithMask = coreParams.StoreQueueForwardWithMask 423 val VlsQueueSize = coreParams.VlsQueueSize 424 val dpParams = coreParams.dpParams 425 val exuParameters = coreParams.exuParameters 426 val NRMemReadPorts = exuParameters.LduCnt + 2 * exuParameters.StuCnt 427 val NRIntReadPorts = 2 * exuParameters.AluCnt + NRMemReadPorts 428 val NRIntWritePorts = exuParameters.AluCnt + exuParameters.MduCnt + exuParameters.LduCnt 429 val NRFpReadPorts = 3 * exuParameters.FmacCnt + exuParameters.StuCnt 430 val NRFpWritePorts = exuParameters.FpExuCnt + exuParameters.LduCnt 431 val LoadPipelineWidth = coreParams.LoadPipelineWidth 432 val StorePipelineWidth = coreParams.StorePipelineWidth 433 val VecMemSrcInWidth = coreParams.VecMemSrcInWidth 434 val VecMemInstWbWidth = coreParams.VecMemInstWbWidth 435 val VecMemDispatchWidth = coreParams.VecMemDispatchWidth 436 val StoreBufferSize = coreParams.StoreBufferSize 437 val StoreBufferThreshold = coreParams.StoreBufferThreshold 438 val EnsbufferWidth = coreParams.EnsbufferWidth 439 val UncacheBufferSize = coreParams.UncacheBufferSize 440 val EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward 441 val EnableFastForward = coreParams.EnableFastForward 442 val EnableLdVioCheckAfterReset = coreParams.EnableLdVioCheckAfterReset 443 val EnableSoftPrefetchAfterReset = coreParams.EnableSoftPrefetchAfterReset 444 val EnableCacheErrorAfterReset = coreParams.EnableCacheErrorAfterReset 445 val EnableDCacheWPU = coreParams.EnableDCacheWPU 446 val EnableAccurateLoadError = coreParams.EnableAccurateLoadError 447 val EnableUncacheWriteOutstanding = coreParams.EnableUncacheWriteOutstanding 448 val asidLen = coreParams.MMUAsidLen 449 val BTLBWidth = coreParams.LoadPipelineWidth + coreParams.StorePipelineWidth 450 val refillBothTlb = coreParams.refillBothTlb 451 val itlbParams = coreParams.itlbParameters 452 val ldtlbParams = coreParams.ldtlbParameters 453 val sttlbParams = coreParams.sttlbParameters 454 val pftlbParams = coreParams.pftlbParameters 455 val btlbParams = coreParams.btlbParameters 456 val l2tlbParams = coreParams.l2tlbParameters 457 val NumPerfCounters = coreParams.NumPerfCounters 458 459 val NumRs = (exuParameters.JmpCnt+1)/2 + (exuParameters.AluCnt+1)/2 + (exuParameters.MulCnt+1)/2 + 460 (exuParameters.MduCnt+1)/2 + (exuParameters.FmacCnt+1)/2 + + (exuParameters.FmiscCnt+1)/2 + 461 (exuParameters.FmiscDivSqrtCnt+1)/2 + (exuParameters.LduCnt+1)/2 + 462 (exuParameters.StuCnt+1)/2 + (exuParameters.StuCnt+1)/2 463 464 val instBytes = if (HasCExtension) 2 else 4 465 val instOffsetBits = log2Ceil(instBytes) 466 467 val icacheParameters = coreParams.icacheParameters 468 val dcacheParameters = coreParams.dcacheParametersOpt.getOrElse(DCacheParameters()) 469 470 // dcache block cacheline when lr for LRSCCycles - LRSCBackOff cycles 471 // for constrained LR/SC loop 472 val LRSCCycles = 64 473 // for lr storm 474 val LRSCBackOff = 8 475 476 // cache hierarchy configurations 477 val l1BusDataWidth = 256 478 479 // load violation predict 480 val ResetTimeMax2Pow = 20 //1078576 481 val ResetTimeMin2Pow = 10 //1024 482 // wait table parameters 483 val WaitTableSize = 1024 484 val MemPredPCWidth = log2Up(WaitTableSize) 485 val LWTUse2BitCounter = true 486 // store set parameters 487 val SSITSize = WaitTableSize 488 val LFSTSize = 32 489 val SSIDWidth = log2Up(LFSTSize) 490 val LFSTWidth = 4 491 val StoreSetEnable = true // LWT will be disabled if SS is enabled 492 val LFSTEnable = false 493 val loadExuConfigs = coreParams.loadExuConfigs 494 val storeExuConfigs = coreParams.storeExuConfigs 495 496 val intExuConfigs = coreParams.intExuConfigs 497 498 val fpExuConfigs = coreParams.fpExuConfigs 499 500 val exuConfigs = coreParams.exuConfigs 501 502 val PCntIncrStep: Int = 6 503 val numPCntHc: Int = 25 504 val numPCntPtw: Int = 19 505 506 val numCSRPCntFrontend = 8 507 val numCSRPCntCtrl = 8 508 val numCSRPCntLsu = 8 509 val numCSRPCntHc = 5 510} 511