1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.frontend.icache 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util.{DecoupledIO, _} 22import freechips.rocketchip.diplomacy.{IdRange, LazyModule, LazyModuleImp, TransferSizes} 23import freechips.rocketchip.tilelink._ 24import freechips.rocketchip.util.BundleFieldBase 25import coupledL2.{AliasField, DirtyField, PrefetchField} 26import xiangshan._ 27import xiangshan.frontend._ 28import xiangshan.cache._ 29import utils._ 30import utility._ 31import xiangshan.backend.fu.PMPReqBundle 32import xiangshan.cache.mmu.{TlbRequestIO, TlbReq} 33import difftest._ 34 35case class ICacheParameters( 36 nSets: Int = 256, 37 nWays: Int = 4, 38 rowBits: Int = 64, 39 nTLBEntries: Int = 32, 40 tagECC: Option[String] = None, 41 dataECC: Option[String] = None, 42 replacer: Option[String] = Some("random"), 43 nMissEntries: Int = 2, 44 nReleaseEntries: Int = 1, 45 nProbeEntries: Int = 2, 46 nPrefetchEntries: Int = 12, 47 nPrefBufferEntries: Int = 32, 48 hasPrefetch: Boolean = true, 49 prefetchPipeNum: Int = 1, 50 nMMIOs: Int = 1, 51 blockBytes: Int = 64 52)extends L1CacheParameters { 53 54 val setBytes = nSets * blockBytes 55 val aliasBitsOpt = DCacheParameters().aliasBitsOpt //if(setBytes > pageSize) Some(log2Ceil(setBytes / pageSize)) else None 56 val reqFields: Seq[BundleFieldBase] = Seq( 57 PrefetchField(), 58 ReqSourceField() 59 ) ++ aliasBitsOpt.map(AliasField) 60 val echoFields: Seq[BundleFieldBase] = Nil 61 def tagCode: Code = Code.fromString(tagECC) 62 def dataCode: Code = Code.fromString(dataECC) 63 def replacement = ReplacementPolicy.fromString(replacer,nWays,nSets) 64} 65 66trait HasICacheParameters extends HasL1CacheParameters with HasInstrMMIOConst with HasIFUConst{ 67 val cacheParams = icacheParameters 68 val dataCodeUnit = 16 69 val dataCodeUnitNum = blockBits/dataCodeUnit 70 71 def highestIdxBit = log2Ceil(nSets) - 1 72 def encDataUnitBits = cacheParams.dataCode.width(dataCodeUnit) 73 def dataCodeBits = encDataUnitBits - dataCodeUnit 74 def dataCodeEntryBits = dataCodeBits * dataCodeUnitNum 75 76 val ICacheSets = cacheParams.nSets 77 val ICacheWays = cacheParams.nWays 78 79 val ICacheSameVPAddrLength = 12 80 val ReplaceIdWid = 5 81 82 val ICacheWordOffset = 0 83 val ICacheSetOffset = ICacheWordOffset + log2Up(blockBytes) 84 val ICacheAboveIndexOffset = ICacheSetOffset + log2Up(ICacheSets) 85 val ICacheTagOffset = ICacheAboveIndexOffset min ICacheSameVPAddrLength 86 87 def PortNumber = 2 88 89 def partWayNum = 2 90 def pWay = nWays/partWayNum 91 92 def nPrefetchEntries = cacheParams.nPrefetchEntries 93 def totalMSHRNum = PortNumber + nPrefetchEntries 94 def nIPFBufferSize = cacheParams.nPrefBufferEntries 95 def maxIPFMoveConf = 1 // temporary use small value to cause more "move" operation 96 def prefetchPipeNum = ICacheParameters().prefetchPipeNum 97 98 def getBits(num: Int) = log2Ceil(num).W 99 100 101 def generatePipeControl(lastFire: Bool, thisFire: Bool, thisFlush: Bool, lastFlush: Bool): Bool = { 102 val valid = RegInit(false.B) 103 when(thisFlush) {valid := false.B} 104 .elsewhen(lastFire && !lastFlush) {valid := true.B} 105 .elsewhen(thisFire) {valid := false.B} 106 valid 107 } 108 109 def ResultHoldBypass[T<:Data](data: T, valid: Bool): T = { 110 Mux(valid, data, RegEnable(data, valid)) 111 } 112 113 def holdReleaseLatch(valid: Bool, release: Bool, flush: Bool): Bool ={ 114 val bit = RegInit(false.B) 115 when(flush) { bit := false.B } 116 .elsewhen(valid && !release) { bit := true.B } 117 .elsewhen(release) { bit := false.B } 118 bit || valid 119 } 120 121 def blockCounter(block: Bool, flush: Bool, threshold: Int): Bool = { 122 val counter = RegInit(0.U(log2Up(threshold + 1).W)) 123 when (block) { counter := counter + 1.U } 124 when (flush) { counter := 0.U} 125 counter > threshold.U 126 } 127 128 require(isPow2(nSets), s"nSets($nSets) must be pow2") 129 require(isPow2(nWays), s"nWays($nWays) must be pow2") 130} 131 132abstract class ICacheBundle(implicit p: Parameters) extends XSBundle 133 with HasICacheParameters 134 135abstract class ICacheModule(implicit p: Parameters) extends XSModule 136 with HasICacheParameters 137 138abstract class ICacheArray(implicit p: Parameters) extends XSModule 139 with HasICacheParameters 140 141class ICacheMetadata(implicit p: Parameters) extends ICacheBundle { 142 val tag = UInt(tagBits.W) 143} 144 145object ICacheMetadata { 146 def apply(tag: Bits)(implicit p: Parameters) = { 147 val meta = Wire(new ICacheMetadata) 148 meta.tag := tag 149 meta 150 } 151} 152 153 154class ICacheMetaArray()(implicit p: Parameters) extends ICacheArray 155{ 156 def onReset = ICacheMetadata(0.U) 157 val metaBits = onReset.getWidth 158 val metaEntryBits = cacheParams.tagCode.width(metaBits) 159 160 val io=IO{new Bundle{ 161 val write = Flipped(DecoupledIO(new ICacheMetaWriteBundle)) 162 val read = Flipped(DecoupledIO(new ICacheReadBundle)) 163 val readResp = Output(new ICacheMetaRespBundle) 164 val cacheOp = Flipped(new L1CacheInnerOpIO) // customized cache op port 165 val fencei = Input(Bool()) 166 }} 167 168 io.read.ready := !io.write.valid 169 170 val port_0_read_0 = io.read.valid && !io.read.bits.vSetIdx(0)(0) 171 val port_0_read_1 = io.read.valid && io.read.bits.vSetIdx(0)(0) 172 val port_1_read_1 = io.read.valid && io.read.bits.vSetIdx(1)(0) && io.read.bits.isDoubleLine 173 val port_1_read_0 = io.read.valid && !io.read.bits.vSetIdx(1)(0) && io.read.bits.isDoubleLine 174 175 val port_0_read_0_reg = RegEnable(next = port_0_read_0, enable = io.read.fire()) 176 val port_0_read_1_reg = RegEnable(next = port_0_read_1, enable = io.read.fire()) 177 val port_1_read_1_reg = RegEnable(next = port_1_read_1, enable = io.read.fire()) 178 val port_1_read_0_reg = RegEnable(next = port_1_read_0, enable = io.read.fire()) 179 180 val bank_0_idx = Mux(port_0_read_0, io.read.bits.vSetIdx(0), io.read.bits.vSetIdx(1)) 181 val bank_1_idx = Mux(port_0_read_1, io.read.bits.vSetIdx(0), io.read.bits.vSetIdx(1)) 182 val bank_idx = Seq(bank_0_idx, bank_1_idx) 183 184 val write_bank_0 = io.write.valid && !io.write.bits.bankIdx 185 val write_bank_1 = io.write.valid && io.write.bits.bankIdx 186 187 val write_meta_bits = Wire(UInt(metaEntryBits.W)) 188 189 val tagArrays = (0 until 2) map { bank => 190 val tagArray = Module(new SRAMTemplate( 191 UInt(metaEntryBits.W), 192 set=nSets/2, 193 way=nWays, 194 shouldReset = true, 195 holdRead = true, 196 singlePort = true 197 )) 198 199 //meta connection 200 if(bank == 0) { 201 tagArray.io.r.req.valid := port_0_read_0 || port_1_read_0 202 tagArray.io.r.req.bits.apply(setIdx=bank_0_idx(highestIdxBit,1)) 203 tagArray.io.w.req.valid := write_bank_0 204 tagArray.io.w.req.bits.apply(data=write_meta_bits, setIdx=io.write.bits.virIdx(highestIdxBit,1), waymask=io.write.bits.waymask) 205 } 206 else { 207 tagArray.io.r.req.valid := port_0_read_1 || port_1_read_1 208 tagArray.io.r.req.bits.apply(setIdx=bank_1_idx(highestIdxBit,1)) 209 tagArray.io.w.req.valid := write_bank_1 210 tagArray.io.w.req.bits.apply(data=write_meta_bits, setIdx=io.write.bits.virIdx(highestIdxBit,1), waymask=io.write.bits.waymask) 211 } 212 213 tagArray 214 } 215 216 val read_set_idx_next = RegEnable(next = io.read.bits.vSetIdx, enable = io.read.fire) 217 val valid_array = RegInit(VecInit(Seq.fill(nWays)(0.U(nSets.W)))) 218 val valid_metas = Wire(Vec(PortNumber, Vec(nWays, Bool()))) 219 // valid read 220 (0 until PortNumber).foreach( i => 221 (0 until nWays).foreach( way => 222 valid_metas(i)(way) := valid_array(way)(read_set_idx_next(i)) 223 )) 224 io.readResp.entryValid := valid_metas 225 226 io.read.ready := !io.write.valid && !io.fencei && tagArrays.map(_.io.r.req.ready).reduce(_&&_) 227 228 //Parity Decode 229 val read_metas = Wire(Vec(2,Vec(nWays,new ICacheMetadata()))) 230 for((tagArray,i) <- tagArrays.zipWithIndex){ 231 val read_meta_bits = tagArray.io.r.resp.asTypeOf(Vec(nWays,UInt(metaEntryBits.W))) 232 val read_meta_decoded = read_meta_bits.map{ way_bits => cacheParams.tagCode.decode(way_bits)} 233 val read_meta_wrong = read_meta_decoded.map{ way_bits_decoded => way_bits_decoded.error} 234 val read_meta_corrected = VecInit(read_meta_decoded.map{ way_bits_decoded => way_bits_decoded.corrected}) 235 read_metas(i) := read_meta_corrected.asTypeOf(Vec(nWays,new ICacheMetadata())) 236 (0 until nWays).map{ w => io.readResp.errors(i)(w) := RegNext(read_meta_wrong(w)) && RegNext(RegNext(io.read.fire))} 237 } 238 239 //Parity Encode 240 val write = io.write.bits 241 write_meta_bits := cacheParams.tagCode.encode(ICacheMetadata(tag = write.phyTag).asUInt) 242 243 // valid write 244 val way_num = OHToUInt(io.write.bits.waymask) 245 when (io.write.valid) { 246 valid_array(way_num) := valid_array(way_num).bitSet(io.write.bits.virIdx, true.B) 247 } 248 249 XSPerfAccumulate("meta_refill_num", io.write.valid) 250 251 io.readResp.metaData <> DontCare 252 when(port_0_read_0_reg){ 253 io.readResp.metaData(0) := read_metas(0) 254 }.elsewhen(port_0_read_1_reg){ 255 io.readResp.metaData(0) := read_metas(1) 256 } 257 258 when(port_1_read_0_reg){ 259 io.readResp.metaData(1) := read_metas(0) 260 }.elsewhen(port_1_read_1_reg){ 261 io.readResp.metaData(1) := read_metas(1) 262 } 263 264 265 io.write.ready := true.B // TODO : has bug ? should be !io.cacheOp.req.valid 266 // deal with customized cache op 267 require(nWays <= 32) 268 io.cacheOp.resp.bits := DontCare 269 val cacheOpShouldResp = WireInit(false.B) 270 when(io.cacheOp.req.valid){ 271 when( 272 CacheInstrucion.isReadTag(io.cacheOp.req.bits.opCode) || 273 CacheInstrucion.isReadTagECC(io.cacheOp.req.bits.opCode) 274 ){ 275 for (i <- 0 until 2) { 276 tagArrays(i).io.r.req.valid := true.B 277 tagArrays(i).io.r.req.bits.apply(setIdx = io.cacheOp.req.bits.index) 278 } 279 cacheOpShouldResp := true.B 280 } 281 when(CacheInstrucion.isWriteTag(io.cacheOp.req.bits.opCode)){ 282 for (i <- 0 until 2) { 283 tagArrays(i).io.w.req.valid := true.B 284 tagArrays(i).io.w.req.bits.apply( 285 data = io.cacheOp.req.bits.write_tag_low, 286 setIdx = io.cacheOp.req.bits.index, 287 waymask = UIntToOH(io.cacheOp.req.bits.wayNum(4, 0)) 288 ) 289 } 290 cacheOpShouldResp := true.B 291 } 292 // TODO 293 // when(CacheInstrucion.isWriteTagECC(io.cacheOp.req.bits.opCode)){ 294 // for (i <- 0 until readPorts) { 295 // array(i).io.ecc_write.valid := true.B 296 // array(i).io.ecc_write.bits.idx := io.cacheOp.req.bits.index 297 // array(i).io.ecc_write.bits.way_en := UIntToOH(io.cacheOp.req.bits.wayNum(4, 0)) 298 // array(i).io.ecc_write.bits.ecc := io.cacheOp.req.bits.write_tag_ecc 299 // } 300 // cacheOpShouldResp := true.B 301 // } 302 } 303 io.cacheOp.resp.valid := RegNext(io.cacheOp.req.valid && cacheOpShouldResp) 304 io.cacheOp.resp.bits.read_tag_low := Mux(io.cacheOp.resp.valid, 305 tagArrays(0).io.r.resp.asTypeOf(Vec(nWays, UInt(tagBits.W)))(io.cacheOp.req.bits.wayNum), 306 0.U 307 ) 308 io.cacheOp.resp.bits.read_tag_ecc := DontCare // TODO 309 // TODO: deal with duplicated array 310 311 // fencei logic : reset valid_array 312 when (io.fencei) { 313 (0 until nWays).foreach( way => 314 valid_array(way) := 0.U 315 ) 316 } 317} 318 319 320 321class ICacheDataArray(implicit p: Parameters) extends ICacheArray 322{ 323 324 def getECCFromEncUnit(encUnit: UInt) = { 325 require(encUnit.getWidth == encDataUnitBits) 326 if (encDataUnitBits == dataCodeUnit) { 327 0.U.asTypeOf(UInt(1.W)) 328 } else { 329 encUnit(encDataUnitBits - 1, dataCodeUnit) 330 } 331 } 332 333 def getECCFromBlock(cacheblock: UInt) = { 334 // require(cacheblock.getWidth == blockBits) 335 VecInit((0 until dataCodeUnitNum).map { w => 336 val unit = cacheblock(dataCodeUnit * (w + 1) - 1, dataCodeUnit * w) 337 getECCFromEncUnit(cacheParams.dataCode.encode(unit)) 338 }) 339 } 340 341 val io=IO{new Bundle{ 342 val write = Flipped(DecoupledIO(new ICacheDataWriteBundle)) 343 val read = Flipped(DecoupledIO(Vec(partWayNum, new ICacheReadBundle))) 344 val readResp = Output(new ICacheDataRespBundle) 345 val cacheOp = Flipped(new L1CacheInnerOpIO) // customized cache op port 346 }} 347 348 val write_data_bits = Wire(UInt(blockBits.W)) 349 350 val port_0_read_0_reg = RegEnable(next = io.read.valid && io.read.bits.head.port_0_read_0, enable = io.read.fire()) 351 val port_0_read_1_reg = RegEnable(next = io.read.valid && io.read.bits.head.port_0_read_1, enable = io.read.fire()) 352 val port_1_read_1_reg = RegEnable(next = io.read.valid && io.read.bits.head.port_1_read_1, enable = io.read.fire()) 353 val port_1_read_0_reg = RegEnable(next = io.read.valid && io.read.bits.head.port_1_read_0, enable = io.read.fire()) 354 355 val bank_0_idx_vec = io.read.bits.map(copy => Mux(io.read.valid && copy.port_0_read_0, copy.vSetIdx(0), copy.vSetIdx(1))) 356 val bank_1_idx_vec = io.read.bits.map(copy => Mux(io.read.valid && copy.port_0_read_1, copy.vSetIdx(0), copy.vSetIdx(1))) 357 358 val dataArrays = (0 until partWayNum).map{ i => 359 val dataArray = Module(new ICachePartWayArray( 360 UInt(blockBits.W), 361 pWay, 362 )) 363 364 dataArray.io.read.req(0).valid := io.read.bits(i).read_bank_0 && io.read.valid 365 dataArray.io.read.req(0).bits.ridx := bank_0_idx_vec(i)(highestIdxBit,1) 366 dataArray.io.read.req(1).valid := io.read.bits(i).read_bank_1 && io.read.valid 367 dataArray.io.read.req(1).bits.ridx := bank_1_idx_vec(i)(highestIdxBit,1) 368 369 370 dataArray.io.write.valid := io.write.valid 371 dataArray.io.write.bits.wdata := write_data_bits 372 dataArray.io.write.bits.widx := io.write.bits.virIdx(highestIdxBit,1) 373 dataArray.io.write.bits.wbankidx := io.write.bits.bankIdx 374 dataArray.io.write.bits.wmask := io.write.bits.waymask.asTypeOf(Vec(partWayNum, Vec(pWay, Bool())))(i) 375 376 dataArray 377 } 378 379 val read_datas = Wire(Vec(2,Vec(nWays,UInt(blockBits.W) ))) 380 381 (0 until PortNumber).map { port => 382 (0 until nWays).map { w => 383 read_datas(port)(w) := dataArrays(w / pWay).io.read.resp.rdata(port).asTypeOf(Vec(pWay, UInt(blockBits.W)))(w % pWay) 384 } 385 } 386 387 io.readResp.datas(0) := Mux( port_0_read_1_reg, read_datas(1) , read_datas(0)) 388 io.readResp.datas(1) := Mux( port_1_read_0_reg, read_datas(0) , read_datas(1)) 389 390 val write_data_code = Wire(UInt(dataCodeEntryBits.W)) 391 val write_bank_0 = WireInit(io.write.valid && !io.write.bits.bankIdx) 392 val write_bank_1 = WireInit(io.write.valid && io.write.bits.bankIdx) 393 394 val bank_0_idx = bank_0_idx_vec.last 395 val bank_1_idx = bank_1_idx_vec.last 396 397 val codeArrays = (0 until 2) map { i => 398 val codeArray = Module(new SRAMTemplate( 399 UInt(dataCodeEntryBits.W), 400 set=nSets/2, 401 way=nWays, 402 shouldReset = true, 403 holdRead = true, 404 singlePort = true 405 )) 406 407 if(i == 0) { 408 codeArray.io.r.req.valid := io.read.valid && io.read.bits.last.read_bank_0 409 codeArray.io.r.req.bits.apply(setIdx=bank_0_idx(highestIdxBit,1)) 410 codeArray.io.w.req.valid := write_bank_0 411 codeArray.io.w.req.bits.apply(data=write_data_code, setIdx=io.write.bits.virIdx(highestIdxBit,1), waymask=io.write.bits.waymask) 412 } 413 else { 414 codeArray.io.r.req.valid := io.read.valid && io.read.bits.last.read_bank_1 415 codeArray.io.r.req.bits.apply(setIdx=bank_1_idx(highestIdxBit,1)) 416 codeArray.io.w.req.valid := write_bank_1 417 codeArray.io.w.req.bits.apply(data=write_data_code, setIdx=io.write.bits.virIdx(highestIdxBit,1), waymask=io.write.bits.waymask) 418 } 419 420 codeArray 421 } 422 423 io.read.ready := !io.write.valid && 424 dataArrays.map(_.io.read.req.map(_.ready).reduce(_&&_)).reduce(_&&_) && 425 codeArrays.map(_.io.r.req.ready).reduce(_ && _) 426 427 //Parity Decode 428 val read_codes = Wire(Vec(2,Vec(nWays,UInt(dataCodeEntryBits.W) ))) 429 for(((dataArray,codeArray),i) <- dataArrays.zip(codeArrays).zipWithIndex){ 430 read_codes(i) := codeArray.io.r.resp.asTypeOf(Vec(nWays,UInt(dataCodeEntryBits.W))) 431 } 432 433 //Parity Encode 434 val write = io.write.bits 435 val write_data = WireInit(write.data) 436 write_data_code := getECCFromBlock(write_data).asUInt 437 write_data_bits := write_data 438 439 io.readResp.codes(0) := Mux( port_0_read_1_reg, read_codes(1) , read_codes(0)) 440 io.readResp.codes(1) := Mux( port_1_read_0_reg, read_codes(0) , read_codes(1)) 441 442 io.write.ready := true.B 443 444 // deal with customized cache op 445 require(nWays <= 32) 446 io.cacheOp.resp.bits := DontCare 447 io.cacheOp.resp.valid := false.B 448 val cacheOpShouldResp = WireInit(false.B) 449 val dataresp = Wire(Vec(nWays,UInt(blockBits.W) )) 450 dataresp := DontCare 451 when(io.cacheOp.req.valid){ 452 when( 453 CacheInstrucion.isReadData(io.cacheOp.req.bits.opCode) 454 ){ 455 for (i <- 0 until partWayNum) { 456 dataArrays(i).io.read.req.zipWithIndex.map{ case(port,i) => 457 if(i ==0) port.valid := !io.cacheOp.req.bits.bank_num(0) 458 else port.valid := io.cacheOp.req.bits.bank_num(0) 459 port.bits.ridx := io.cacheOp.req.bits.index(highestIdxBit,1) 460 } 461 } 462 cacheOpShouldResp := dataArrays.head.io.read.req.map(_.fire()).reduce(_||_) 463 dataresp :=Mux(io.cacheOp.req.bits.bank_num(0).asBool, read_datas(1), read_datas(0)) 464 } 465 when(CacheInstrucion.isWriteData(io.cacheOp.req.bits.opCode)){ 466 for (i <- 0 until partWayNum) { 467 dataArrays(i).io.write.valid := true.B 468 dataArrays(i).io.write.bits.wdata := io.cacheOp.req.bits.write_data_vec.asTypeOf(write_data.cloneType) 469 dataArrays(i).io.write.bits.wbankidx := io.cacheOp.req.bits.bank_num(0) 470 dataArrays(i).io.write.bits.widx := io.cacheOp.req.bits.index(highestIdxBit,1) 471 dataArrays(i).io.write.bits.wmask := UIntToOH(io.cacheOp.req.bits.wayNum(4, 0)).asTypeOf(Vec(partWayNum, Vec(pWay, Bool())))(i) 472 } 473 cacheOpShouldResp := true.B 474 } 475 } 476 477 io.cacheOp.resp.valid := RegNext(cacheOpShouldResp) 478 val numICacheLineWords = blockBits / 64 479 require(blockBits >= 64 && isPow2(blockBits)) 480 for (wordIndex <- 0 until numICacheLineWords) { 481 io.cacheOp.resp.bits.read_data_vec(wordIndex) := dataresp(io.cacheOp.req.bits.wayNum(4, 0))(64*(wordIndex+1)-1, 64*wordIndex) 482 } 483 484} 485 486 487class ICacheIO(implicit p: Parameters) extends ICacheBundle 488{ 489 val hartId = Input(UInt(8.W)) 490 val prefetch = Flipped(new FtqPrefechBundle) 491 val stop = Input(Bool()) 492 val fetch = new ICacheMainPipeBundle 493 val toIFU = Output(Bool()) 494 val pmp = Vec(PortNumber + prefetchPipeNum, new ICachePMPBundle) 495 val itlb = Vec(PortNumber + prefetchPipeNum, new TlbRequestIO) 496 val perfInfo = Output(new ICachePerfInfo) 497 val error = new L1CacheErrorInfo 498 /* Cache Instruction */ 499 val csr = new L1CacheToCsrIO 500 /* CSR control signal */ 501 val csr_pf_enable = Input(Bool()) 502 val csr_parity_enable = Input(Bool()) 503 val fencei = Input(Bool()) 504} 505 506class ICache()(implicit p: Parameters) extends LazyModule with HasICacheParameters { 507 override def shouldBeInlined: Boolean = false 508 509 val clientParameters = TLMasterPortParameters.v1( 510 Seq(TLMasterParameters.v1( 511 name = "icache", 512 sourceId = IdRange(0, cacheParams.nMissEntries + cacheParams.nPrefetchEntries), 513 )), 514 requestFields = cacheParams.reqFields, 515 echoFields = cacheParams.echoFields 516 ) 517 518 val clientNode = TLClientNode(Seq(clientParameters)) 519 520 lazy val module = new ICacheImp(this) 521} 522 523class ICacheImp(outer: ICache) extends LazyModuleImp(outer) with HasICacheParameters with HasPerfEvents { 524 val io = IO(new ICacheIO) 525 526 println("ICache:") 527 println(" ICacheSets: " + cacheParams.nSets) 528 println(" ICacheWays: " + cacheParams.nWays) 529 println(" ICacheBanks: " + PortNumber) 530 println(" hasPrefetch: " + cacheParams.hasPrefetch) 531 if(cacheParams.hasPrefetch){ 532 println(" nPrefetchEntries: " + cacheParams.nPrefetchEntries) 533 println(" nPrefetchBufferEntries: " + cacheParams.nPrefBufferEntries) 534 println(" prefetchPipeNum: " + cacheParams.prefetchPipeNum) 535 } 536 537 val (bus, edge) = outer.clientNode.out.head 538 539 val metaArray = Module(new ICacheMetaArray) 540 val dataArray = Module(new ICacheDataArray) 541 val prefetchMetaArray = Module(new ICacheBankedMetaArray(prefetchPipeNum)) // need add 1 port for IPF filter 542 val mainPipe = Module(new ICacheMainPipe) 543 val missUnit = Module(new ICacheMissUnit(edge)) 544 val fdipPrefetch = Module(new FDIPPrefetch(edge)) 545 546 fdipPrefetch.io.hartId := io.hartId 547 fdipPrefetch.io.fencei := io.fencei 548 fdipPrefetch.io.ftqReq <> io.prefetch 549 fdipPrefetch.io.metaReadReq <> prefetchMetaArray.io.read(0) 550 fdipPrefetch.io.metaReadResp <> prefetchMetaArray.io.readResp(0) 551 fdipPrefetch.io.mshrInfo <> missUnit.io.mshrInfo 552 fdipPrefetch.io.mainPipeMissInfo <> mainPipe.io.mainPipeMissInfo 553 fdipPrefetch.io.IPFBufferRead <> mainPipe.io.IPFBufferRead 554 fdipPrefetch.io.IPFReplacer <> mainPipe.io.IPFReplacer 555 fdipPrefetch.io.PIQRead <> mainPipe.io.PIQRead 556 557 // Meta Array. Priority: missUnit > fdipPrefetch 558 val meta_write_arb = Module(new Arbiter(new ICacheMetaWriteBundle(), 2)) 559 meta_write_arb.io.in(0) <> missUnit.io.meta_write 560 meta_write_arb.io.in(1) <> fdipPrefetch.io.metaWrite 561 meta_write_arb.io.out <> metaArray.io.write 562 563 // Data Array. Priority: missUnit > fdipPrefetch 564 val data_write_arb = Module(new Arbiter(new ICacheDataWriteBundle(), 2)) 565 data_write_arb.io.in(0) <> missUnit.io.data_write 566 data_write_arb.io.in(1) <> fdipPrefetch.io.dataWrite 567 data_write_arb.io.out <> dataArray.io.write 568 569 // prefetch Meta Array. Connect meta_write_arb to ensure the data is same as metaArray 570 prefetchMetaArray.io.write <> meta_write_arb.io.out 571 572 mainPipe.io.dataArray.toIData <> dataArray.io.read 573 mainPipe.io.dataArray.fromIData <> dataArray.io.readResp 574 mainPipe.io.metaArray.toIMeta <> metaArray.io.read 575 mainPipe.io.metaArray.fromIMeta <> metaArray.io.readResp 576 mainPipe.io.metaArray.fromIMeta <> metaArray.io.readResp 577 mainPipe.io.respStall := io.stop 578 mainPipe.io.csr_parity_enable := io.csr_parity_enable 579 mainPipe.io.hartId := io.hartId 580 581 io.pmp(0) <> mainPipe.io.pmp(0) 582 io.pmp(1) <> mainPipe.io.pmp(1) 583 if(cacheParams.hasPrefetch) { 584 io.pmp(2) <> fdipPrefetch.io.pmp 585 } 586 587 io.itlb(0) <> mainPipe.io.itlb(0) 588 io.itlb(1) <> mainPipe.io.itlb(1) 589 if(cacheParams.hasPrefetch) { 590 io.itlb(2) <> fdipPrefetch.io.iTLBInter 591 } 592 593 //notify IFU that Icache pipeline is available 594 io.toIFU := mainPipe.io.fetch.req.ready 595 io.perfInfo := mainPipe.io.perfInfo 596 597 io.fetch.resp <> mainPipe.io.fetch.resp 598 io.fetch.topdownIcacheMiss := mainPipe.io.fetch.topdownIcacheMiss 599 io.fetch.topdownItlbMiss := mainPipe.io.fetch.topdownItlbMiss 600 601 for(i <- 0 until PortNumber){ 602 missUnit.io.req(i) <> mainPipe.io.mshr(i).toMSHR 603 mainPipe.io.mshr(i).fromMSHR <> missUnit.io.resp(i) 604 } 605 606 missUnit.io.hartId := io.hartId 607 missUnit.io.fencei := io.fencei 608 missUnit.io.fdip_acquire <> fdipPrefetch.io.mem_acquire 609 missUnit.io.fdip_grant <> fdipPrefetch.io.mem_grant 610 611 bus.b.ready := false.B 612 bus.c.valid := false.B 613 bus.c.bits := DontCare 614 bus.e.valid := false.B 615 bus.e.bits := DontCare 616 617 bus.a <> missUnit.io.mem_acquire 618 619 // connect bus d 620 missUnit.io.mem_grant.valid := false.B 621 missUnit.io.mem_grant.bits := DontCare 622 623 //Parity error port 624 val errors = mainPipe.io.errors 625 io.error <> RegNext(Mux1H(errors.map(e => e.valid -> e))) 626 627 628 mainPipe.io.fetch.req <> io.fetch.req 629 bus.d.ready := false.B 630 missUnit.io.mem_grant <> bus.d 631 632 // fencei connect 633 metaArray.io.fencei := io.fencei 634 prefetchMetaArray.io.fencei := io.fencei 635 636 val perfEvents = Seq( 637 ("icache_miss_cnt ", false.B), 638 ("icache_miss_penty", BoolStopWatch(start = false.B, stop = false.B || false.B, startHighPriority = true)), 639 ) 640 generatePerfEvent() 641 642 // Customized csr cache op support 643 val cacheOpDecoder = Module(new CSRCacheOpDecoder("icache", CacheInstrucion.COP_ID_ICACHE)) 644 cacheOpDecoder.io.csr <> io.csr 645 dataArray.io.cacheOp.req := cacheOpDecoder.io.cache.req 646 metaArray.io.cacheOp.req := cacheOpDecoder.io.cache.req 647 prefetchMetaArray.io.cacheOp.req := cacheOpDecoder.io.cache.req 648 cacheOpDecoder.io.cache.resp.valid := 649 dataArray.io.cacheOp.resp.valid || 650 metaArray.io.cacheOp.resp.valid 651 cacheOpDecoder.io.cache.resp.bits := Mux1H(List( 652 dataArray.io.cacheOp.resp.valid -> dataArray.io.cacheOp.resp.bits, 653 metaArray.io.cacheOp.resp.valid -> metaArray.io.cacheOp.resp.bits, 654 )) 655 cacheOpDecoder.io.error := io.error 656 assert(!((dataArray.io.cacheOp.resp.valid +& metaArray.io.cacheOp.resp.valid) > 1.U)) 657} 658 659class ICachePartWayReadBundle[T <: Data](gen: T, pWay: Int)(implicit p: Parameters) 660 extends ICacheBundle 661{ 662 val req = Flipped(Vec(PortNumber, Decoupled(new Bundle{ 663 val ridx = UInt((log2Ceil(nSets) - 1).W) 664 }))) 665 val resp = Output(new Bundle{ 666 val rdata = Vec(PortNumber,Vec(pWay, gen)) 667 }) 668} 669 670class ICacheWriteBundle[T <: Data](gen: T, pWay: Int)(implicit p: Parameters) 671 extends ICacheBundle 672{ 673 val wdata = gen 674 val widx = UInt((log2Ceil(nSets) - 1).W) 675 val wbankidx = Bool() 676 val wmask = Vec(pWay, Bool()) 677} 678 679class ICachePartWayArray[T <: Data](gen: T, pWay: Int)(implicit p: Parameters) extends ICacheArray 680{ 681 682 //including part way data 683 val io = IO{new Bundle { 684 val read = new ICachePartWayReadBundle(gen,pWay) 685 val write = Flipped(ValidIO(new ICacheWriteBundle(gen, pWay))) 686 }} 687 688 io.read.req.map(_.ready := !io.write.valid) 689 690 val srams = (0 until PortNumber) map { bank => 691 val sramBank = Module(new SRAMTemplate( 692 gen, 693 set=nSets/2, 694 way=pWay, 695 shouldReset = true, 696 holdRead = true, 697 singlePort = true 698 )) 699 700 sramBank.io.r.req.valid := io.read.req(bank).valid 701 sramBank.io.r.req.bits.apply(setIdx= io.read.req(bank).bits.ridx) 702 703 if(bank == 0) sramBank.io.w.req.valid := io.write.valid && !io.write.bits.wbankidx 704 else sramBank.io.w.req.valid := io.write.valid && io.write.bits.wbankidx 705 sramBank.io.w.req.bits.apply(data=io.write.bits.wdata, setIdx=io.write.bits.widx, waymask=io.write.bits.wmask.asUInt()) 706 707 sramBank 708 } 709 710 io.read.req.map(_.ready := !io.write.valid && srams.map(_.io.r.req.ready).reduce(_&&_)) 711 712 io.read.resp.rdata := VecInit(srams.map(bank => bank.io.r.resp.asTypeOf(Vec(pWay,gen)))) 713 714} 715