fix(StoreQueue): fix bug in `uncacheState` FSM (#3728)

`scommit` from RoB represents the number of store instructions committed
in this cycle, excluding the stores that raise exceptions. However th

fix(StoreQueue): fix bug in `uncacheState` FSM (#3728)

`scommit` from RoB represents the number of store instructions committed
in this cycle, excluding the stores that raise exceptions. However the
FSM for uncache store transitions from `s_wait` to `s_idle` only when
`scommit > 0.U`. Therefore when a non-data error is raised from error
device and an access fault is reported, the FSM gets blocked on `s_wait`
state. Supposing that the next store in SQ raises another exception, the
uncache FSM will get into deadlock.

This pr fixes the bug by a little modification on the uncache FSM, that
is, when a mmio store that is detected for a non-data error writes back
to backend, the FSM will transition into `s_idle` directly, skipping the
state of `s_wait`.

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fix(lsq): uncache req can be assigned only in idle state (#3732)

**Bug Description:**

When an uncache store (st) is immediately followed by an uncache load
(ld), due to the `AddPipelineReg` in M

fix(lsq): uncache req can be assigned only in idle state (#3732)

**Bug Description:**

When an uncache store (st) is immediately followed by an uncache load
(ld), due to the `AddPipelineReg` in MemBlock when the LSQ transfers
data with the Uncache, even though Uncache is handling the store
request, `MemBlock.uncacheReq.ready` is still true. Under the original
assignment conditions, the ld request(ld req) from LQ will be received
by `MemBlock.uncacheReq` in the `s_store` state. So when
`MemBlock.uncacheReq` is received by Uncache, the LSQ state has already
transitioned from `s_store` to `s_idle`, without switching to `s_load`.
As a result, the load response (ld resp) from Uncache can never be
received by the LSQ. The process is briefly described as follows:

1. SQ: st req
2. Uncache: st req received
3. LQ: ld req in `s_store` state
4. Uncache: st resp
5. SQ: st resp received; Uncache: ld req received
6. LSQ: state to `s_idle`
7. Uncache: ld resp
8. **ERROR**: LSQ can not receive ld resp in `s_idle` state

**Fix**：In LSQ, uncache req can be assigned only in idle state.
<img width="1179" alt="image"
src="https://github.com/user-attachments/assets/1d2d417d-06d6-43bf-a876-5cc53d0ff9ed">

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fix(StoreQueue): commitLastFlow should be true when the port 1 has no exception (#3704)

When an exception is thrown by vector store:

* If not the last flow triggers an exception, then pull up the

fix(StoreQueue): commitLastFlow should be true when the port 1 has no exception (#3704)

When an exception is thrown by vector store:

* If not the last flow triggers an exception, then pull up the
vecExceptionFlag and do not allow subsequent flows to actually
* write to the sbuffer, but can exit the queue from the sq normally.

* If it is the last flow that triggered the exception, then there is no
need to pull up vecExceptionFlag.

The vecExceptionFlag affects the vecvalid signal passed into the
sbuffer, and only when vecvalid is high can data actually be written to
the sbuffer.

Based on the current ports of the sbuffer, we list the cases as shown in
the implementation:

* When only the first port is valid, we only need to see if the first
port is lastflow.

* When both ports are valid, we need to judge based on whether robidx is
equal or not:
* When equal, the first port is definitely not lastflow, so we only need
to judge whether the second port is lastflow.

* When unequal, the first port is definitely lastflow, so we need to
pull up vecCommitLastFlow when the second port
* doesn't trigger an exception, and we need to judge whether the second
port is lastflow when the second port triggers
* an exception.

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fix(LoadMisalignBuffer): all exception from misalignbuffer should overwrite (#3699)

In our previous design, we would only overwrite from misalignbuffer for
cross-page requests; misalign requests th

fix(LoadMisalignBuffer): all exception from misalignbuffer should overwrite (#3699)

In our previous design, we would only overwrite from misalignbuffer for
cross-page requests; misalign requests that don't cross pages would
still be written back from exceptionbuffer. However, exception messages
such as gpaddr, which require a TLB hit to return, need to be written
back from the misalignbuffer instead.

This commit writes back all exceptions of misalign requests from the
misalignbuffer.

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fix(StoreQueue): the condition of last flow is just related to the second entry

* This temp commit fix the condition of vector last flow.
* Only support EnsbufferWidth == 2.
* When 0 and 1 robidx eq

fix(StoreQueue): the condition of last flow is just related to the second entry

* This temp commit fix the condition of vector last flow.
* Only support EnsbufferWidth == 2.
* When 0 and 1 robidx equal, just check if 1 is last flow.
* When not equal, 0 must be the last flow, just check if 1 is last flow when 1 has exception.

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fix(storequeue): cancel the vExceptionFlag when the last flow dequeue

feat(rv64v): support first only fault instruction

feat(VLSU): set vstart when the support vector accesses anomalies

feat(Trigger): add vector memory access Trigger logic

fix(cmo): support DiffTest with cbo.inval instruction (#3662)

When the DUT executes a cbo.inval, a set in Difftest is used to record
its cacheline address.
Later, if there is a data mismatch betwe

fix(cmo): support DiffTest with cbo.inval instruction (#3662)

When the DUT executes a cbo.inval, a set in Difftest is used to record
its cacheline address.
Later, if there is a data mismatch between DUT and GoldenMem in the
address space operated by the cbo.inval instruction, the Pmem of REF and
GoldenMem will be directly updated using the data of DUT.

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fix(exception): fix exception vaddr generate logic (#3639)

In LSU, for exceptions that can be detected before address
translation(`preaf`, `prepf` or `pregpf`), the original vaddr should be
retain

fix(exception): fix exception vaddr generate logic (#3639)

In LSU, for exceptions that can be detected before address
translation(`preaf`, `prepf` or `pregpf`), the original vaddr should be
retained. And for exceptions detected after address translation, the
48-bit vaddr needs to be zero-extended or sign-extended according to
different modes(`GenExceptionVa`), and then write to *tval.

Also fix some connection bugs.

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fix(exception): connect new address port for vector access exceptions (#3626)

The vector exception address comes from the VMergebuffer, which needs to
store all 64 bits addresses and connect to the

fix(exception): connect new address port for vector access exceptions (#3626)

The vector exception address comes from the VMergebuffer, which needs to
store all 64 bits addresses and connect to the LSQ exception processing.

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feat(trap): support m/htinst for specific G-stage translation (#3604)

According to RISC-V priv spec, mtinst/htinst could be always written
zero on trap into M/HS-mode, except for Guest-Page-Fault t

feat(trap): support m/htinst for specific G-stage translation (#3604)

According to RISC-V priv spec, mtinst/htinst could be always written
zero on trap into M/HS-mode, except for Guest-Page-Fault traps that meet
both of the following conditions:
- the trap is caused by a G-stage translation which supports VS-stage
translation
- a nonzero value is written to mtval2/htval

"isForVSnonLeafPTE" is used only in exceptional circumstances that gpf
happens in the G-stage translation which supports VS-stage translation,
such as searching the non-leaf pte of VS-stage.

This patch adds support for writing proper value to mtinst/htinst when
specific trap occurs. And bump the nemu.

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fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exc

fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exceptions in such cases.

Commit
https://github.com/OpenXiangShan/XiangShan/commit/c1b28b66879239a5b3a44741376f3b002e8ac834
has already fixed high address bits checking of jump target. This commit
fixes lsu part, checking full address in tlb and passing full address
directly to csr.

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timing(LsqEnqCtrl): fix timing of lqAllocNumber and sqAllocNumber

fix(StoreQueue): fix difftestBuffer enqueue condition (#3592)

This buffer is for difftest only, and when dataBuffer enqueue,
difftestbuffer should enqueue as well.

fix(LoadQueueReplay): fix blocking logic (#3590)

StoreQueue: write vaddr into exception buffer when SoC af is detected

This commit adds an extra port in store exception buffer for store queue
to write exception vaddr in order to update mtval CSR.

StoreQueue: fix bug in updating non-data error into `uncacheUop`

When a system level non-data error such as an attempt to access a
location that does not exist is generated, store queue should updat

StoreQueue: fix bug in updating non-data error into `uncacheUop`

When a system level non-data error such as an attempt to access a
location that does not exist is generated, store queue should update
`exceptionVec` in `uncacheUop` instead of updating the `uop` directly.

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fix(exception): Add guest page fault logic of misalign and vlsu (#3537)

In our previous design, we did not consider the handling of gpf of
unaligned & vector load and stores. This commit adds a fix

fix(exception): Add guest page fault logic of misalign and vlsu (#3537)

In our previous design, we did not consider the handling of gpf of
unaligned & vector load and stores. This commit adds a fix to correctly
return the guest paddr when gpf happens in the above instructions.

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fix(StoreQueue): deq exception checking need comparing robidx (#3477)

Fixed the bugs introduced by this commit
(https://github.com/OpenXiangShan/XiangShan/pull/3464)

Deq exception checking need

fix(StoreQueue): deq exception checking need comparing robidx (#3477)

Fixed the bugs introduced by this commit
(https://github.com/OpenXiangShan/XiangShan/pull/3464)

Deq exception checking need comparing robidx.
We need to find other ways to mitigate the timing here.

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fix(Zicclsm, trigger): fix the problem of missing breakpoint exception (#3470)

+ @wissygh Refactored Trigger check code of Memblock.
+ Move Trigger address cmp from load S3 to S1. In addition, the

fix(Zicclsm, trigger): fix the problem of missing breakpoint exception (#3470)

+ @wissygh Refactored Trigger check code of Memblock.
+ Move Trigger address cmp from load S3 to S1. In addition, the
detection of trigger is moved from Memblock to LoadUnit.
- Once the breakpoint exception is detected, enter the exception Buffer
directly to handle the exception (previously, the
load instruction was executed first and then the exception was handled,
which would cause the mmio load to change the
status of the peripheral).
+ If Trigger address matches and the action is to enter debug mode, both
loadUnit and storeUnit will directly write this instruction back without
any execution (by setting this instruction as an exception).
+ Match trigger addresses for vector instructions in LoadUnit.
+ If both a misalign exception and a breakpoint occur, the breakpoint
exception will be processed first.

---------

Co-authored-by: chengguanghui <[email protected]>

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fix(LoadQueue): software prefetch should always be ready to deq (#3484)

A software prefetch instruction is similar to a normal load instruction
in that it allocates loadqueue entries, and we need t

fix(LoadQueue): software prefetch should always be ready to deq (#3484)

A software prefetch instruction is similar to a normal load instruction
in that it allocates loadqueue entries, and we need to write them back
to the backend through loadunit. Unlike normal load instructions,
software prefetch instructions will not be replayed, and will be written
directly back to the backend. At the same time in loadqueue, as long as
this instruction is at the head of the queue, it can deq.

In the past design, although the software prefetch instruction will not
enter load replay queue, it still needs to wait for both addrvalid and
datavalid to be ready before it can deq from loadqueue, which in fact
will cause the entry to never deq from loadqueue, resulting in a
deadlock. This commit fixes this bug: addrvalid and datavalid will
always be considered true for software prefetch instructions.

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timing(MemBlock): optimize MemBlock timing (#3467)

This PR optimizes the timing of MemBlock. Specific optimizations include
but are not limited to:
+ TLB use the redirect for the next cycle
+ Opt

timing(MemBlock): optimize MemBlock timing (#3467)

This PR optimizes the timing of MemBlock. Specific optimizations include
but are not limited to:
+ TLB use the redirect for the next cycle
+ Optimize VLSU feedback and redirect
+ Optimise ldCancel and writeback signal generation
+ Optimise TLB Query Vaddr/hlv/hlvx/valid etc
+ Delay MMIO Store writeback for 1 Cycle
+ Fix tlbNoQuery and pmp logic
+ Remove clock gating for s3_fast_rep
+ Remove wbq conflict check to LoadPipe/MainPipe
+ Remove Mux in dcache resp data
+ Optimise data generation logic of LoadUnit
+ Duplicate Register in LoadUnit for data writeback
+ Duplicate Register in loadPipe for missQueue enq
+ Add skid buffer in VLSU
+ Select data from metaArray at S1
+ Simplify the enqueuing logic of missQueue
+ Separately generate the ready logic of miss Queue
+ Relax the conditions valid for bankdataArray reads
+ Add Reg between Dcache Mainpipe with sms prefetcher
+ Optimise store exceptionBuffer pipeline

---------

Co-authored-by: weiding liu <[email protected]>
Co-authored-by: Charlie Liu <[email protected]>
Co-authored-by: good-circle <[email protected]>

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timing(StoreQueue): deq exception checking not comparing robidx (#3464)