1package xiangshan.backend.fu.NewCSR.CSREvents 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import utility.SignExt 7import xiangshan.ExceptionNO 8import xiangshan.backend.fu.NewCSR.CSRBundles.{CauseBundle, OneFieldBundle, PrivState} 9import xiangshan.backend.fu.NewCSR.CSRConfig.{VaddrMaxWidth, XLEN} 10import xiangshan.backend.fu.NewCSR._ 11import xiangshan.AddrTransType 12 13 14class TrapEntryMEventOutput extends Bundle with EventUpdatePrivStateOutput with EventOutputBase { 15 16 val mstatus = ValidIO((new MstatusBundle ).addInEvent(_.MPV, _.MPP, _.GVA, _.MPIE, _.MIE)) 17 val mepc = ValidIO((new Epc ).addInEvent(_.epc)) 18 val mcause = ValidIO((new CauseBundle ).addInEvent(_.Interrupt, _.ExceptionCode)) 19 val mtval = ValidIO((new OneFieldBundle).addInEvent(_.ALL)) 20 val mtval2 = ValidIO((new OneFieldBundle).addInEvent(_.ALL)) 21 val mtinst = ValidIO((new OneFieldBundle).addInEvent(_.ALL)) 22 val tcontrol = ValidIO((new TcontrolBundle).addInEvent(_.MPTE, _.MTE)) 23 val targetPc = ValidIO(new TargetPCBundle) 24} 25 26class TrapEntryMEventModule(implicit val p: Parameters) extends Module with CSREventBase { 27 val in = IO(new TrapEntryEventInput) 28 val out = IO(new TrapEntryMEventOutput) 29 30 private val current = in 31 private val iMode = current.iMode 32 private val dMode = current.dMode 33 private val satp = current.satp 34 private val vsatp = current.vsatp 35 private val hgatp = current.hgatp 36 37 private val highPrioTrapNO = in.causeNO.ExceptionCode.asUInt 38 private val isException = !in.causeNO.Interrupt.asBool 39 private val isInterrupt = in.causeNO.Interrupt.asBool 40 41 private val trapPC = genTrapVA( 42 iMode, 43 satp, 44 vsatp, 45 hgatp, 46 in.trapPc, 47 ) 48 49 private val trapPCGPA = SignExt(in.trapPcGPA, XLEN) 50 51 private val trapMemVA = in.memExceptionVAddr 52 53 private val trapMemGPA = in.memExceptionGPAddr 54 55 private val trapInst = Mux(in.trapInst.valid, in.trapInst.bits, 0.U) 56 57 private val fetchIsVirt = iMode.isVirtual 58 private val memIsVirt = dMode.isVirtual 59 60 private val isFetchExcp = isException && ExceptionNO.getFetchFault.map(_.U === highPrioTrapNO).reduce(_ || _) 61 private val isMemExcp = isException && (ExceptionNO.getLoadFault ++ ExceptionNO.getStoreFault).map(_.U === highPrioTrapNO).reduce(_ || _) 62 private val isBpExcp = isException && ExceptionNO.EX_BP.U === highPrioTrapNO 63 private val isHlsExcp = isException && in.isHls 64 private val fetchCrossPage = in.isCrossPageIPF 65 private val isFetchMalAddr = in.isFetchMalAddr 66 private val isIllegalInst = isException && (ExceptionNO.EX_II.U === highPrioTrapNO || ExceptionNO.EX_VI.U === highPrioTrapNO) 67 68 private val isLSGuestExcp = isException && ExceptionNO.getLSGuestPageFault.map(_.U === highPrioTrapNO).reduce(_ || _) 69 private val isFetchGuestExcp = isException && ExceptionNO.EX_IGPF.U === highPrioTrapNO 70 // Software breakpoint exceptions are permitted to write either 0 or the pc to xtval 71 // We fill pc here 72 private val tvalFillPc = (isFetchExcp || isFetchGuestExcp) && !fetchCrossPage || isBpExcp 73 private val tvalFillPcPlus2 = (isFetchExcp || isFetchGuestExcp) && fetchCrossPage 74 private val tvalFillMemVaddr = isMemExcp 75 private val tvalFillGVA = 76 isHlsExcp && isMemExcp || 77 isLSGuestExcp|| isFetchGuestExcp || 78 (isFetchExcp || isBpExcp) && fetchIsVirt || 79 isMemExcp && memIsVirt 80 private val tvalFillInst = isIllegalInst 81 82 private val tval = Mux1H(Seq( 83 (tvalFillPc ) -> trapPC, 84 (tvalFillPcPlus2 ) -> (trapPC + 2.U), 85 (tvalFillMemVaddr && !memIsVirt ) -> trapMemVA, 86 (tvalFillMemVaddr && memIsVirt ) -> trapMemVA, 87 (isLSGuestExcp ) -> trapMemVA, 88 (tvalFillInst ) -> trapInst, 89 )) 90 91 private val tval2 = Mux1H(Seq( 92 (isFetchGuestExcp && isFetchMalAddr ) -> in.fetchMalTval, 93 (isFetchGuestExcp && !isFetchMalAddr && !fetchCrossPage) -> trapPCGPA, 94 (isFetchGuestExcp && !isFetchMalAddr && fetchCrossPage ) -> (trapPCGPA + 2.U), 95 (isLSGuestExcp ) -> trapMemGPA, 96 )) 97 98 out := DontCare 99 100 out.privState.valid := valid 101 out.mstatus .valid := valid 102 out.mepc .valid := valid 103 out.mcause .valid := valid 104 out.mtval .valid := valid 105 out.mtval2 .valid := valid 106 out.mtinst .valid := valid 107 out.tcontrol .valid := valid 108 out.targetPc .valid := valid 109 110 out.privState.bits := PrivState.ModeM 111 out.mstatus.bits.MPV := current.privState.V 112 out.mstatus.bits.MPP := current.privState.PRVM 113 out.mstatus.bits.GVA := tvalFillGVA 114 out.mstatus.bits.MPIE := current.mstatus.MIE 115 out.mstatus.bits.MIE := 0.U 116 out.mepc.bits.epc := Mux(isFetchMalAddr, in.fetchMalTval(63, 1), trapPC(63, 1)) 117 out.mcause.bits.Interrupt := isInterrupt 118 out.mcause.bits.ExceptionCode := highPrioTrapNO 119 out.mtval.bits.ALL := Mux(isFetchMalAddr, in.fetchMalTval, tval) 120 out.mtval2.bits.ALL := tval2 >> 2 121 out.mtinst.bits.ALL := Mux(isFetchGuestExcp && in.trapIsForVSnonLeafPTE || isLSGuestExcp && in.memExceptionIsForVSnonLeafPTE, 0x3000.U, 0.U) 122 out.tcontrol.bits.MPTE := in.tcontrol.MTE 123 out.tcontrol.bits.MTE := 0.U 124 out.targetPc.bits.pc := in.pcFromXtvec 125 out.targetPc.bits.raiseIPF := false.B 126 out.targetPc.bits.raiseIAF := AddrTransType(bare = true).checkAccessFault(in.pcFromXtvec) 127 out.targetPc.bits.raiseIGPF := false.B 128 129 dontTouch(isLSGuestExcp) 130 dontTouch(tvalFillGVA) 131} 132 133trait TrapEntryMEventSinkBundle extends EventSinkBundle { self: CSRModule[_ <: CSRBundle] => 134 val trapToM = IO(Flipped(new TrapEntryMEventOutput)) 135 136 addUpdateBundleInCSREnumType(trapToM.getBundleByName(self.modName.toLowerCase())) 137 138 reconnectReg() 139} 140