1package xiangshan.backend.fu.wrapper 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import utility._ 7import xiangshan._ 8import xiangshan.backend.fu.NewCSR._ 9import xiangshan.backend.fu.util._ 10import xiangshan.backend.fu.{FuConfig, FuncUnit} 11import device._ 12import system.HasSoCParameter 13import xiangshan.ExceptionNO._ 14import xiangshan.backend.Bundles.TrapInstInfo 15import xiangshan.backend.decode.Imm_Z 16import xiangshan.backend.fu.NewCSR.CSRBundles.PrivState 17import xiangshan.backend.fu.NewCSR.CSRDefines.PrivMode 18import xiangshan.frontend.FtqPtr 19 20class CSR(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) 21 with HasCircularQueuePtrHelper 22{ 23 val csrIn = io.csrio.get 24 val csrOut = io.csrio.get 25 val csrToDecode = io.csrToDecode.get 26 27 val setFsDirty = csrIn.fpu.dirty_fs 28 val setFflags = csrIn.fpu.fflags 29 30 val setVsDirty = csrIn.vpu.dirty_vs 31 val setVstart = csrIn.vpu.set_vstart 32 val setVtype = csrIn.vpu.set_vtype 33 val setVxsat = csrIn.vpu.set_vxsat 34 val vlFromPreg = csrIn.vpu.vl 35 36 val flushPipe = Wire(Bool()) 37 val flush = io.flush.valid 38 39 /** Alias of input signals */ 40 val (valid, src1, imm, func) = ( 41 io.in.valid, 42 io.in.bits.data.src(0), 43 io.in.bits.data.imm(Imm_Z().len - 1, 0), 44 io.in.bits.ctrl.fuOpType 45 ) 46 47 // split imm/src1/rd from IMM_Z: src1/rd for tval 48 val addr = Imm_Z().getCSRAddr(imm) 49 val rd = Imm_Z().getRD(imm) 50 val rs1 = Imm_Z().getRS1(imm) 51 val imm5 = Imm_Z().getImm5(imm) 52 val csri = ZeroExt(imm5, XLEN) 53 54 import CSRConst._ 55 56 private val isEcall = CSROpType.isSystemOp(func) && addr === privEcall 57 private val isEbreak = CSROpType.isSystemOp(func) && addr === privEbreak 58 private val isMNret = CSROpType.isSystemOp(func) && addr === privMNret 59 private val isMret = CSROpType.isSystemOp(func) && addr === privMret 60 private val isSret = CSROpType.isSystemOp(func) && addr === privSret 61 private val isDret = CSROpType.isSystemOp(func) && addr === privDret 62 private val isWfi = CSROpType.isWfi(func) 63 private val isCSRAcc = CSROpType.isCsrAccess(func) 64 65 val csrMod = Module(new NewCSR) 66 val trapInstMod = Module(new TrapInstMod) 67 val trapTvalMod = Module(new TrapTvalMod) 68 69 private val privState = csrMod.io.status.privState 70 // The real reg value in CSR, with no read mask 71 private val regOut = csrMod.io.out.bits.regOut 72 private val src = Mux(CSROpType.needImm(func), csri, src1) 73 private val wdata = LookupTree(func, Seq( 74 CSROpType.wrt -> src1, 75 CSROpType.set -> (regOut | src1), 76 CSROpType.clr -> (regOut & (~src1).asUInt), 77 CSROpType.wrti -> csri, 78 CSROpType.seti -> (regOut | csri), 79 CSROpType.clri -> (regOut & (~csri).asUInt), 80 )) 81 82 private val csrAccess = valid && CSROpType.isCsrAccess(func) 83 private val csrWen = valid && ( 84 CSROpType.isCSRRW(func) || 85 CSROpType.isCSRRSorRC(func) && rs1 =/= 0.U 86 ) 87 private val csrRen = valid && ( 88 CSROpType.isCSRRW(func) && rd =/= 0.U || 89 CSROpType.isCSRRSorRC(func) 90 ) 91 92 csrMod.io.in match { 93 case in => 94 in.valid := valid 95 in.bits.wen := csrWen 96 in.bits.ren := csrRen 97 in.bits.op := CSROpType.getCSROp(func) 98 in.bits.addr := addr 99 in.bits.src := src 100 in.bits.wdata := wdata 101 in.bits.mret := isMret 102 in.bits.mnret := isMNret 103 in.bits.sret := isSret 104 in.bits.dret := isDret 105 } 106 csrMod.io.trapInst := trapInstMod.io.currentTrapInst 107 csrMod.io.fetchMalTval := trapTvalMod.io.tval 108 csrMod.io.fromMem.excpVA := csrIn.memExceptionVAddr 109 csrMod.io.fromMem.excpGPA := csrIn.memExceptionGPAddr 110 111 csrMod.io.fromRob.trap.valid := csrIn.exception.valid 112 csrMod.io.fromRob.trap.bits.pc := csrIn.exception.bits.pc 113 csrMod.io.fromRob.trap.bits.instr := csrIn.exception.bits.instr 114 csrMod.io.fromRob.trap.bits.pcGPA := csrIn.exception.bits.gpaddr 115 // Todo: shrink the width of trap vector. 116 // We use 64bits trap vector in CSR, and 24 bits exceptionVec in exception bundle. 117 csrMod.io.fromRob.trap.bits.trapVec := csrIn.exception.bits.exceptionVec.asUInt 118 csrMod.io.fromRob.trap.bits.singleStep := csrIn.exception.bits.singleStep 119 csrMod.io.fromRob.trap.bits.crossPageIPFFix := csrIn.exception.bits.crossPageIPFFix 120 csrMod.io.fromRob.trap.bits.isInterrupt := csrIn.exception.bits.isInterrupt 121 csrMod.io.fromRob.trap.bits.trigger := csrIn.exception.bits.trigger 122 csrMod.io.fromRob.trap.bits.isHls := csrIn.exception.bits.isHls 123 csrMod.io.fromRob.trap.bits.isFetchMalAddr := csrIn.exception.bits.isFetchMalAddr 124 125 csrMod.io.fromRob.commit.fflags := setFflags 126 csrMod.io.fromRob.commit.fsDirty := setFsDirty 127 csrMod.io.fromRob.commit.vxsat.valid := setVxsat.valid 128 csrMod.io.fromRob.commit.vxsat.bits := setVxsat.bits 129 csrMod.io.fromRob.commit.vsDirty := setVsDirty 130 csrMod.io.fromRob.commit.vstart := setVstart 131 csrMod.io.fromRob.commit.vl := vlFromPreg 132 // Todo: correct vtype 133 csrMod.io.fromRob.commit.vtype.valid := setVtype.valid 134 csrMod.io.fromRob.commit.vtype.bits.VILL := setVtype.bits(XLEN - 1) 135 csrMod.io.fromRob.commit.vtype.bits.VMA := setVtype.bits(7) 136 csrMod.io.fromRob.commit.vtype.bits.VTA := setVtype.bits(6) 137 csrMod.io.fromRob.commit.vtype.bits.VSEW := setVtype.bits(5, 3) 138 csrMod.io.fromRob.commit.vtype.bits.VLMUL := setVtype.bits(2, 0) 139 140 csrMod.io.fromRob.commit.instNum.valid := true.B // Todo: valid control signal 141 csrMod.io.fromRob.commit.instNum.bits := csrIn.perf.retiredInstr 142 143 csrMod.io.fromRob.robDeqPtr := csrIn.robDeqPtr 144 145 csrMod.io.perf := csrIn.perf 146 147 csrMod.platformIRP.MEIP := csrIn.externalInterrupt.meip 148 csrMod.platformIRP.MTIP := csrIn.externalInterrupt.mtip 149 csrMod.platformIRP.MSIP := csrIn.externalInterrupt.msip 150 csrMod.platformIRP.SEIP := csrIn.externalInterrupt.seip 151 csrMod.platformIRP.STIP := false.B 152 csrMod.platformIRP.VSEIP := false.B // Todo 153 csrMod.platformIRP.VSTIP := false.B // Todo 154 csrMod.platformIRP.debugIP := csrIn.externalInterrupt.debug 155 csrMod.nonMaskableIRP.NMI := csrIn.externalInterrupt.nmi.nmi 156 157 csrMod.io.fromTop.hartId := io.csrin.get.hartId 158 csrMod.io.fromTop.clintTime := io.csrin.get.clintTime 159 private val csrModOutValid = csrMod.io.out.valid 160 private val csrModOut = csrMod.io.out.bits 161 162 trapInstMod.io.fromDecode.trapInstInfo := RegNextWithEnable(io.csrin.get.trapInstInfo, hasInit = true) 163 trapInstMod.io.fromRob.flush.valid := io.flush.valid 164 trapInstMod.io.fromRob.flush.bits.ftqPtr := io.flush.bits.ftqIdx 165 trapInstMod.io.fromRob.flush.bits.ftqOffset := io.flush.bits.ftqOffset 166 trapInstMod.io.faultCsrUop.valid := csrMod.io.out.valid && (csrMod.io.out.bits.EX_II || csrMod.io.out.bits.EX_VI) 167 trapInstMod.io.faultCsrUop.bits.fuOpType := DataHoldBypass(io.in.bits.ctrl.fuOpType, io.in.fire) 168 trapInstMod.io.faultCsrUop.bits.imm := DataHoldBypass(io.in.bits.data.imm, io.in.fire) 169 trapInstMod.io.faultCsrUop.bits.ftqInfo.ftqPtr := DataHoldBypass(io.in.bits.ctrl.ftqIdx.get, io.in.fire) 170 trapInstMod.io.faultCsrUop.bits.ftqInfo.ftqOffset := DataHoldBypass(io.in.bits.ctrl.ftqOffset.get, io.in.fire) 171 // Clear trap instruction when instruction fault trap(EX_II, EX_VI) occurs. 172 trapInstMod.io.readClear := (csrMod.io.fromRob.trap match { 173 case t => 174 t.valid && !t.bits.isInterrupt && (t.bits.trapVec(EX_II) || t.bits.trapVec(EX_VI)) 175 }) 176 177 trapTvalMod.io.targetPc.valid := csrMod.io.out.bits.targetPcUpdate 178 trapTvalMod.io.targetPc.bits := csrMod.io.out.bits.targetPc 179 trapTvalMod.io.clear := csrIn.exception.valid && csrIn.exception.bits.isFetchMalAddr 180 trapTvalMod.io.fromCtrlBlock.flush := io.flush 181 trapTvalMod.io.fromCtrlBlock.robDeqPtr := io.csrio.get.robDeqPtr 182 183 private val imsic = Module(new IMSIC(NumVSIRFiles = 5, NumHart = 1, XLEN = 64, NumIRSrc = 256)) 184 imsic.i.hartId := io.csrin.get.hartId 185 imsic.i.msiInfo := io.csrin.get.msiInfo 186 imsic.i.csr.addr.valid := csrMod.toAIA.addr.valid 187 imsic.i.csr.addr.bits.addr := csrMod.toAIA.addr.bits.addr 188 imsic.i.csr.addr.bits.prvm := csrMod.toAIA.addr.bits.prvm.asUInt 189 imsic.i.csr.addr.bits.v := csrMod.toAIA.addr.bits.v.asUInt 190 imsic.i.csr.vgein := csrMod.toAIA.vgein 191 imsic.i.csr.mClaim := csrMod.toAIA.mClaim 192 imsic.i.csr.sClaim := csrMod.toAIA.sClaim 193 imsic.i.csr.vsClaim := csrMod.toAIA.vsClaim 194 imsic.i.csr.wdata.valid := csrMod.toAIA.wdata.valid 195 imsic.i.csr.wdata.bits.op := csrMod.toAIA.wdata.bits.op 196 imsic.i.csr.wdata.bits.data := csrMod.toAIA.wdata.bits.data 197 198 csrMod.fromAIA.rdata.valid := imsic.o.csr.rdata.valid 199 csrMod.fromAIA.rdata.bits.data := imsic.o.csr.rdata.bits.rdata 200 csrMod.fromAIA.rdata.bits.illegal := imsic.o.csr.rdata.bits.illegal 201 csrMod.fromAIA.meip := imsic.o.meip 202 csrMod.fromAIA.seip := imsic.o.seip 203 csrMod.fromAIA.vseip := imsic.o.vseip 204 csrMod.fromAIA.mtopei := imsic.o.mtopei 205 csrMod.fromAIA.stopei := imsic.o.stopei 206 csrMod.fromAIA.vstopei := imsic.o.vstopei 207 208 private val exceptionVec = WireInit(0.U.asTypeOf(ExceptionVec())) // Todo: 209 210 exceptionVec(EX_BP ) := isEbreak 211 exceptionVec(EX_MCALL ) := isEcall && privState.isModeM 212 exceptionVec(EX_HSCALL) := isEcall && privState.isModeHS 213 exceptionVec(EX_VSCALL) := isEcall && privState.isModeVS 214 exceptionVec(EX_UCALL ) := isEcall && privState.isModeHUorVU 215 exceptionVec(EX_II ) := csrMod.io.out.bits.EX_II 216 exceptionVec(EX_VI ) := csrMod.io.out.bits.EX_VI 217 218 val isXRet = valid && func === CSROpType.jmp && !isEcall && !isEbreak 219 220 // ctrl block will use theses later for flush // Todo: optimize isXRetFlag's DelayN 221 val isXRetFlag = RegInit(false.B) 222 isXRetFlag := Mux1H(Seq( 223 DelayN(flush, 5) -> false.B, 224 isXRet -> true.B, 225 )) 226 227 flushPipe := csrMod.io.out.bits.flushPipe 228 229 // tlb 230 val tlb = Wire(new TlbCsrBundle) 231 tlb.satp.changed := csrMod.io.tlb.satpASIDChanged 232 tlb.satp.mode := csrMod.io.tlb.satp.MODE.asUInt 233 tlb.satp.asid := csrMod.io.tlb.satp.ASID.asUInt 234 tlb.satp.ppn := csrMod.io.tlb.satp.PPN.asUInt 235 tlb.vsatp.changed := csrMod.io.tlb.vsatpASIDChanged 236 tlb.vsatp.mode := csrMod.io.tlb.vsatp.MODE.asUInt 237 tlb.vsatp.asid := csrMod.io.tlb.vsatp.ASID.asUInt 238 tlb.vsatp.ppn := csrMod.io.tlb.vsatp.PPN.asUInt 239 tlb.hgatp.changed := csrMod.io.tlb.hgatpVMIDChanged 240 tlb.hgatp.mode := csrMod.io.tlb.hgatp.MODE.asUInt 241 tlb.hgatp.vmid := csrMod.io.tlb.hgatp.VMID.asUInt 242 tlb.hgatp.ppn := csrMod.io.tlb.hgatp.PPN.asUInt 243 244 // expose several csr bits for tlb 245 tlb.priv.mxr := csrMod.io.tlb.mxr 246 tlb.priv.sum := csrMod.io.tlb.sum 247 tlb.priv.vmxr := csrMod.io.tlb.vmxr 248 tlb.priv.vsum := csrMod.io.tlb.vsum 249 tlb.priv.spvp := csrMod.io.tlb.spvp 250 tlb.priv.virt := csrMod.io.tlb.dvirt 251 tlb.priv.imode := csrMod.io.tlb.imode 252 tlb.priv.dmode := csrMod.io.tlb.dmode 253 254 // Svpbmt extension enable 255 tlb.mPBMTE := csrMod.io.tlb.mPBMTE 256 tlb.hPBMTE := csrMod.io.tlb.hPBMTE 257 258 /** Since some CSR read instructions are allowed to be pipelined, ready/valid signals should be modified */ 259 io.in.ready := csrMod.io.in.ready // Todo: Async read imsic may block CSR 260 io.out.valid := csrModOutValid 261 io.out.bits.ctrl.exceptionVec.get := exceptionVec 262 io.out.bits.ctrl.flushPipe.get := flushPipe 263 io.out.bits.res.data := csrMod.io.out.bits.rData 264 265 /** initialize NewCSR's io_out_ready from wrapper's io */ 266 csrMod.io.out.ready := io.out.ready 267 268 io.out.bits.res.redirect.get.valid := isXRet 269 val redirect = io.out.bits.res.redirect.get.bits 270 redirect := 0.U.asTypeOf(redirect) 271 redirect.level := RedirectLevel.flushAfter 272 redirect.robIdx := io.in.bits.ctrl.robIdx 273 redirect.ftqIdx := io.in.bits.ctrl.ftqIdx.get 274 redirect.ftqOffset := io.in.bits.ctrl.ftqOffset.get 275 redirect.cfiUpdate.predTaken := true.B 276 redirect.cfiUpdate.taken := true.B 277 redirect.cfiUpdate.target := csrMod.io.out.bits.targetPc.pc 278 redirect.cfiUpdate.backendIPF := csrMod.io.out.bits.targetPc.raiseIPF 279 redirect.cfiUpdate.backendIAF := csrMod.io.out.bits.targetPc.raiseIAF 280 redirect.cfiUpdate.backendIGPF := csrMod.io.out.bits.targetPc.raiseIGPF 281 // Only mispred will send redirect to frontend 282 redirect.cfiUpdate.isMisPred := true.B 283 284 connect0LatencyCtrlSingal 285 286 // Todo: summerize all difftest skip condition 287 csrOut.isPerfCnt := csrMod.io.out.bits.isPerfCnt && csrModOutValid && func =/= CSROpType.jmp 288 csrOut.fpu.frm := csrMod.io.status.fpState.frm.asUInt 289 csrOut.vpu.vstart := csrMod.io.status.vecState.vstart.asUInt 290 csrOut.vpu.vxrm := csrMod.io.status.vecState.vxrm.asUInt 291 292 csrOut.isXRet := isXRetFlag 293 294 csrOut.trapTarget := csrMod.io.out.bits.targetPc 295 csrOut.interrupt := csrMod.io.status.interrupt 296 csrOut.wfi_event := csrMod.io.status.wfiEvent 297 298 csrOut.tlb := tlb 299 300 csrOut.debugMode := csrMod.io.status.debugMode 301 302 csrOut.customCtrl match { 303 case custom => 304 custom.l1I_pf_enable := csrMod.io.status.custom.l1I_pf_enable 305 custom.l2_pf_enable := csrMod.io.status.custom.l2_pf_enable 306 custom.l1D_pf_enable := csrMod.io.status.custom.l1D_pf_enable 307 custom.l1D_pf_train_on_hit := csrMod.io.status.custom.l1D_pf_train_on_hit 308 custom.l1D_pf_enable_agt := csrMod.io.status.custom.l1D_pf_enable_agt 309 custom.l1D_pf_enable_pht := csrMod.io.status.custom.l1D_pf_enable_pht 310 custom.l1D_pf_active_threshold := csrMod.io.status.custom.l1D_pf_active_threshold 311 custom.l1D_pf_active_stride := csrMod.io.status.custom.l1D_pf_active_stride 312 custom.l1D_pf_enable_stride := csrMod.io.status.custom.l1D_pf_enable_stride 313 custom.l2_pf_store_only := csrMod.io.status.custom.l2_pf_store_only 314 // ICache 315 custom.icache_parity_enable := csrMod.io.status.custom.icache_parity_enable 316 // Load violation predictor 317 custom.lvpred_disable := csrMod.io.status.custom.lvpred_disable 318 custom.no_spec_load := csrMod.io.status.custom.no_spec_load 319 custom.storeset_wait_store := csrMod.io.status.custom.storeset_wait_store 320 custom.storeset_no_fast_wakeup := csrMod.io.status.custom.storeset_no_fast_wakeup 321 custom.lvpred_timeout := csrMod.io.status.custom.lvpred_timeout 322 // Branch predictor 323 custom.bp_ctrl := csrMod.io.status.custom.bp_ctrl 324 // Memory Block 325 custom.sbuffer_threshold := csrMod.io.status.custom.sbuffer_threshold 326 custom.ldld_vio_check_enable := csrMod.io.status.custom.ldld_vio_check_enable 327 custom.soft_prefetch_enable := csrMod.io.status.custom.soft_prefetch_enable 328 custom.cache_error_enable := csrMod.io.status.custom.cache_error_enable 329 custom.uncache_write_outstanding_enable := csrMod.io.status.custom.uncache_write_outstanding_enable 330 custom.hd_misalign_st_enable := csrMod.io.status.custom.hd_misalign_st_enable 331 custom.hd_misalign_ld_enable := csrMod.io.status.custom.hd_misalign_ld_enable 332 // Rename 333 custom.fusion_enable := csrMod.io.status.custom.fusion_enable 334 custom.wfi_enable := csrMod.io.status.custom.wfi_enable 335 // distribute csr write signal 336 // write to frontend and memory 337 custom.distribute_csr.w.valid := csrWen 338 custom.distribute_csr.w.bits.addr := addr 339 custom.distribute_csr.w.bits.data := wdata 340 // rename single step 341 custom.singlestep := csrMod.io.status.singleStepFlag 342 // trigger 343 custom.frontend_trigger := csrMod.io.status.frontendTrigger 344 custom.mem_trigger := csrMod.io.status.memTrigger 345 // virtual mode 346 custom.virtMode := csrMod.io.status.privState.V.asBool 347 } 348 349 csrOut.instrAddrTransType := csrMod.io.status.instrAddrTransType 350 351 csrToDecode := csrMod.io.toDecode 352} 353 354class CSRInput(implicit p: Parameters) extends XSBundle with HasSoCParameter{ 355 val hartId = Input(UInt(8.W)) 356 val msiInfo = Input(ValidIO(new MsiInfoBundle)) 357 val clintTime = Input(ValidIO(UInt(64.W))) 358 val trapInstInfo = Input(ValidIO(new TrapInstInfo)) 359} 360 361class CSRToDecode(implicit p: Parameters) extends XSBundle { 362 val illegalInst = new Bundle { 363 /** 364 * illegal sfence.vma, sinval.vma 365 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 366 */ 367 val sfenceVMA = Bool() 368 369 /** 370 * illegal sfence.w.inval sfence.inval.ir 371 * raise EX_II when isModeHU 372 */ 373 val sfencePart = Bool() 374 375 /** 376 * illegal hfence.gvma, hinval.gvma 377 * raise EX_II when isModeHS && mstatus.TVM=1 || isModeHU 378 * the condition is the same as sfenceVMA 379 */ 380 val hfenceGVMA = Bool() 381 382 /** 383 * illegal hfence.vvma, hinval.vvma 384 * raise EX_II when isModeHU 385 */ 386 val hfenceVVMA = Bool() 387 388 /** 389 * illegal hlv, hlvx, and hsv 390 * raise EX_II when isModeHU && hstatus.HU=0 391 */ 392 val hlsv = Bool() 393 394 /** 395 * decode all fp inst or all vecfp inst 396 * raise EX_II when FS=Off 397 */ 398 val fsIsOff = Bool() 399 400 /** 401 * decode all vec inst 402 * raise EX_II when VS=Off 403 */ 404 val vsIsOff = Bool() 405 406 /** 407 * illegal wfi 408 * raise EX_II when isModeHU || !isModeM && mstatus.TW=1 409 */ 410 val wfi = Bool() 411 412 /** 413 * frm reserved 414 * raise EX_II when frm.data > 4 415 */ 416 val frm = Bool() 417 418 /** 419 * illegal CBO.ZERO 420 * raise [[EX_II]] when !isModeM && !MEnvCfg.CBZE || isModeHU && !SEnvCfg.CBZE 421 */ 422 val cboZ = Bool() 423 424 /** 425 * illegal CBO.CLEAN/FLUSH 426 * raise [[EX_II]] when !isModeM && !MEnvCfg.CBCFE || isModeHU && !SEnvCfg.CBCFE 427 */ 428 val cboCF = Bool() 429 430 /** 431 * illegal CBO.INVAL 432 * raise [[EX_II]] when !isModeM && MEnvCfg.CBIE = EnvCBIE.Off || isModeHU && SEnvCfg.CBIE = EnvCBIE.Off 433 */ 434 val cboI = Bool() 435 } 436 437 val virtualInst = new Bundle { 438 /** 439 * illegal sfence.vma, svinval.vma 440 * raise EX_VI when isModeVS && hstatus.VTVM=1 || isModeVU 441 */ 442 val sfenceVMA = Bool() 443 444 /** 445 * illegal sfence.w.inval sfence.inval.ir 446 * raise EX_VI when isModeVU 447 */ 448 val sfencePart = Bool() 449 450 /** 451 * illegal hfence.gvma, hinval.gvma, hfence.vvma, hinval.vvma 452 * raise EX_VI when isModeVS || isModeVU 453 */ 454 val hfence = Bool() 455 456 /** 457 * illegal hlv, hlvx, and hsv 458 * raise EX_VI when isModeVS || isModeVU 459 */ 460 val hlsv = Bool() 461 462 /** 463 * illegal wfi 464 * raise EX_VI when isModeVU && mstatus.TW=0 || isModeVS && mstatus.TW=0 && hstatus.VTW=1 465 */ 466 val wfi = Bool() 467 468 /** 469 * illegal CBO.ZERO 470 * raise [[EX_VI]] when MEnvCfg.CBZE && (isModeVS && !HEnvCfg.CBZE || isModeVU && (!HEnvCfg.CBZE || !SEnvCfg.CBZE)) 471 */ 472 val cboZ = Bool() 473 474 /** 475 * illegal CBO.CLEAN/FLUSH 476 * raise [[EX_VI]] when MEnvCfg.CBZE && (isModeVS && !HEnvCfg.CBCFE || isModeVU && (!HEnvCfg.CBCFE || !SEnvCfg.CBCFE)) 477 */ 478 val cboCF = Bool() 479 480 /** 481 * illegal CBO.INVAL <br/> 482 * raise [[EX_VI]] when MEnvCfg.CBIE =/= EnvCBIE.Off && ( <br/> 483 * isModeVS && HEnvCfg.CBIE === EnvCBIE.Off || <br/> 484 * isModeVU && (HEnvCfg.CBIE === EnvCBIE.Off || SEnvCfg.CBIE === EnvCBIE.Off) <br/> 485 * ) <br/> 486 */ 487 val cboI = Bool() 488 } 489 490 val special = new Bundle { 491 /** 492 * execute CBO.INVAL and perform flush operation when <br/> 493 * isModeHS && MEnvCfg.CBIE === EnvCBIE.Flush || <br/> 494 * isModeHU && (MEnvCfg.CBIE === EnvCBIE.Flush || SEnvCfg.CBIE === EnvCBIE.Flush) <br/> 495 * isModeVS && (MEnvCfg.CBIE === EnvCBIE.Flush || HEnvCfg.CBIE === EnvCBIE.Flush) <br/> 496 * isModeVU && (MEnvCfg.CBIE === EnvCBIE.Flush || HEnvCfg.CBIE === EnvCBIE.Flush || SEnvCfg.CBIE === EnvCBIE.Flush) <br/> 497 */ 498 val cboI2F = Bool() 499 } 500}