1package xiangshan.backend.fu.NewCSR.CSREvents 2 3import chisel3._ 4import chisel3.util._ 5import org.chipsalliance.cde.config.Parameters 6import utility.SignExt 7import xiangshan.ExceptionNO 8import xiangshan.backend.fu.NewCSR.CSRBundles.{CauseBundle, OneFieldBundle, PrivState} 9import xiangshan.backend.fu.NewCSR.CSRConfig.{VaddrMaxWidth, XLEN} 10import xiangshan.backend.fu.NewCSR._ 11import xiangshan.AddrTransType 12 13 14class TrapEntryMEventOutput extends Bundle with EventUpdatePrivStateOutput with EventOutputBase { 15 16 val mstatus = ValidIO((new MstatusBundle ).addInEvent(_.MPV, _.MPP, _.GVA, _.MPIE, _.MIE)) 17 val mepc = ValidIO((new Epc ).addInEvent(_.epc)) 18 val mcause = ValidIO((new CauseBundle ).addInEvent(_.Interrupt, _.ExceptionCode)) 19 val mtval = ValidIO((new OneFieldBundle).addInEvent(_.ALL)) 20 val mtval2 = ValidIO((new OneFieldBundle).addInEvent(_.ALL)) 21 val mtinst = ValidIO((new OneFieldBundle).addInEvent(_.ALL)) 22 val tcontrol = ValidIO((new TcontrolBundle).addInEvent(_.MPTE, _.MTE)) 23 val targetPc = ValidIO(new TargetPCBundle) 24 25 def getBundleByName(name: String): Valid[CSRBundle] = { 26 name match { 27 case "mstatus" => this.mstatus 28 case "mepc" => this.mepc 29 case "mcause" => this.mcause 30 case "mtval" => this.mtval 31 case "mtval2" => this.mtval2 32 case "mtinst" => this.mtinst 33 case "tcontrol" => this.tcontrol 34 } 35 } 36} 37 38class TrapEntryMEventModule(implicit val p: Parameters) extends Module with CSREventBase { 39 val in = IO(new TrapEntryEventInput) 40 val out = IO(new TrapEntryMEventOutput) 41 42 private val current = in 43 private val iMode = current.iMode 44 private val dMode = current.dMode 45 private val satp = current.satp 46 private val vsatp = current.vsatp 47 private val hgatp = current.hgatp 48 49 private val highPrioTrapNO = in.causeNO.ExceptionCode.asUInt 50 private val isException = !in.causeNO.Interrupt.asBool 51 private val isInterrupt = in.causeNO.Interrupt.asBool 52 53 private val trapPC = genTrapVA( 54 iMode, 55 satp, 56 vsatp, 57 hgatp, 58 in.trapPc, 59 ) 60 61 private val trapPCGPA = SignExt(in.trapPcGPA, XLEN) 62 63 private val trapMemVA = in.memExceptionVAddr 64 65 private val trapMemGPA = in.memExceptionGPAddr 66 67 private val trapInst = Mux(in.trapInst.valid, in.trapInst.bits, 0.U) 68 69 private val fetchIsVirt = iMode.isVirtual 70 private val memIsVirt = dMode.isVirtual 71 72 private val isFetchExcp = isException && ExceptionNO.getFetchFault.map(_.U === highPrioTrapNO).reduce(_ || _) 73 private val isMemExcp = isException && (ExceptionNO.getLoadFault ++ ExceptionNO.getStoreFault).map(_.U === highPrioTrapNO).reduce(_ || _) 74 private val isBpExcp = isException && ExceptionNO.EX_BP.U === highPrioTrapNO 75 private val isHlsExcp = isException && in.isHls 76 private val fetchCrossPage = in.isCrossPageIPF 77 private val isFetchMalAddr = in.isFetchMalAddr 78 private val isIllegalInst = isException && (ExceptionNO.EX_II.U === highPrioTrapNO || ExceptionNO.EX_VI.U === highPrioTrapNO) 79 80 private val isLSGuestExcp = isException && ExceptionNO.getLSGuestPageFault.map(_.U === highPrioTrapNO).reduce(_ || _) 81 private val isFetchGuestExcp = isException && ExceptionNO.EX_IGPF.U === highPrioTrapNO 82 // Software breakpoint exceptions are permitted to write either 0 or the pc to xtval 83 // We fill pc here 84 private val tvalFillPc = (isFetchExcp || isFetchGuestExcp) && !fetchCrossPage || isBpExcp 85 private val tvalFillPcPlus2 = (isFetchExcp || isFetchGuestExcp) && fetchCrossPage 86 private val tvalFillMemVaddr = isMemExcp 87 private val tvalFillGVA = 88 isHlsExcp && isMemExcp || 89 isLSGuestExcp|| isFetchGuestExcp || 90 (isFetchExcp || isBpExcp) && fetchIsVirt || 91 isMemExcp && memIsVirt 92 private val tvalFillInst = isIllegalInst 93 94 private val tval = Mux1H(Seq( 95 (tvalFillPc ) -> trapPC, 96 (tvalFillPcPlus2 ) -> (trapPC + 2.U), 97 (tvalFillMemVaddr && !memIsVirt ) -> trapMemVA, 98 (tvalFillMemVaddr && memIsVirt ) -> trapMemVA, 99 (isLSGuestExcp ) -> trapMemVA, 100 (tvalFillInst ) -> trapInst, 101 )) 102 103 private val tval2 = Mux1H(Seq( 104 (isFetchGuestExcp && isFetchMalAddr ) -> in.fetchMalTval, 105 (isFetchGuestExcp && !isFetchMalAddr && !fetchCrossPage) -> trapPCGPA, 106 (isFetchGuestExcp && !isFetchMalAddr && fetchCrossPage ) -> (trapPCGPA + 2.U), 107 (isLSGuestExcp ) -> trapMemGPA, 108 )) 109 110 out := DontCare 111 112 out.privState.valid := valid 113 out.mstatus .valid := valid 114 out.mepc .valid := valid 115 out.mcause .valid := valid 116 out.mtval .valid := valid 117 out.mtval2 .valid := valid 118 out.mtinst .valid := valid 119 out.tcontrol .valid := valid 120 out.targetPc .valid := valid 121 122 out.privState.bits := PrivState.ModeM 123 out.mstatus.bits.MPV := current.privState.V 124 out.mstatus.bits.MPP := current.privState.PRVM 125 out.mstatus.bits.GVA := tvalFillGVA 126 out.mstatus.bits.MPIE := current.mstatus.MIE 127 out.mstatus.bits.MIE := 0.U 128 out.mepc.bits.epc := Mux(isFetchMalAddr, in.fetchMalTval(63, 1), trapPC(63, 1)) 129 out.mcause.bits.Interrupt := isInterrupt 130 out.mcause.bits.ExceptionCode := highPrioTrapNO 131 out.mtval.bits.ALL := Mux(isFetchMalAddr, in.fetchMalTval, tval) 132 out.mtval2.bits.ALL := tval2 >> 2 133 out.mtinst.bits.ALL := 0.U 134 out.tcontrol.bits.MPTE := in.tcontrol.MTE 135 out.tcontrol.bits.MTE := 0.U 136 out.targetPc.bits.pc := in.pcFromXtvec 137 out.targetPc.bits.raiseIPF := false.B 138 out.targetPc.bits.raiseIAF := AddrTransType(bare = true).checkAccessFault(in.pcFromXtvec) 139 out.targetPc.bits.raiseIGPF := false.B 140 141 dontTouch(isLSGuestExcp) 142 dontTouch(tvalFillGVA) 143} 144 145trait TrapEntryMEventSinkBundle { self: CSRModule[_] => 146 val trapToM = IO(Flipped(new TrapEntryMEventOutput)) 147 148 private val updateBundle: ValidIO[CSRBundle] = trapToM.getBundleByName(self.modName.toLowerCase()) 149 150 (reg.asInstanceOf[CSRBundle].getFields zip updateBundle.bits.getFields).foreach { case (sink, source) => 151 if (updateBundle.bits.eventFields.contains(source)) { 152 when(updateBundle.valid) { 153 sink := source 154 } 155 } 156 } 157} 158